阅读说明：本技术 时钟相位控制电路、方法、功率放大装置及音频设备 (Clock phase control circuit, clock phase control method, power amplification device and audio equipment ) 是由 刘�东 姚炜 于 2020-04-09 设计创作，主要内容包括：本申请涉及一种时钟相位控制电路、方法、功率放大装置及音频设备。所述电路包括：接口模块,用于基于接收的时钟信号和时钟相位参数设置信号生成同步指示信号、时钟使能信号和时钟相位控制信号；时钟产生模块,用于基于接收的所述时钟使能信号生成系统时钟信号；相位控制模块,用于基于接收的所述时钟相位控制信号、所述同步指示信号和所述系统时钟信号生成置位信号和复位信号；第一时钟分频器用于基于接收的所述系统时钟信号及所述复位信号生成控制后一级电路在预设的时刻启动的第一工作时钟信号；第二时钟分频器用于基于接收的所述系统时钟信号及所述置位信号生成能够精准控制后一级电路相位延迟的第二工作时钟信号。(The application relates to a clock phase control circuit, a clock phase control method, a power amplification device and audio equipment. The circuit comprises: the interface module is used for generating a synchronization indication signal, a clock enable signal and a clock phase control signal based on the received clock signal and the clock phase parameter setting signal; a clock generation module for generating a system clock signal based on the received clock enable signal; a phase control module for generating a set signal and a reset signal based on the received clock phase control signal, the synchronization indication signal and the system clock signal; the first clock frequency divider is used for generating a first working clock signal for controlling a next-stage circuit to start at a preset time based on the received system clock signal and the reset signal; and the second clock frequency divider is used for generating a second working clock signal capable of accurately controlling the phase delay of the next-stage circuit based on the received system clock signal and the setting signal.)

1. A clock phase control circuit, comprising:

the interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating a synchronization indication signal, a clock enable signal and a clock phase control signal according to the clock signal and the clock phase parameter setting signal;

the clock generation module is connected with the interface module and used for receiving the clock enabling signal and generating a system clock signal according to the clock enabling signal;

the phase control module is respectively connected with the interface module and the clock generation module, and is used for receiving the clock phase control signal, the synchronous indication signal and the system clock signal and generating a set signal and a reset signal according to the clock phase control signal, the synchronous indication signal and the system clock signal;

the first clock frequency divider is respectively connected with the phase control module and the clock generation module and used for receiving the system clock signal and the reset signal and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time;

and the second clock frequency divider is respectively connected with the phase control module and the clock generation module and used for receiving the system clock signal and the setting signal and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit.

2. The clock phase control circuit of claim 1, wherein the interface module comprises:

the I2C general interface module is used for receiving the clock signal and the clock phase parameter setting signal and generating the clock enable signal, the enable signal and the address selection signal according to the clock signal and the clock phase parameter setting signal;

the I2C special interface module is connected with the I2C general interface module and used for receiving the clock signal, the enable signal and the address selection signal and generating the synchronization indication signal according to the clock signal, the enable signal and the address selection signal.

3. The clock phase control circuit of claim 2, wherein the I2C specific interface module comprises:

the I2C protocol analysis interface is connected with the I2C universal interface module and is used for receiving the clock signal, the enable signal and the address selection signal and generating an I2C protocol analysis signal according to the clock signal, the enable signal and the address selection signal;

a synchronization indication signal generator connected with the I2C protocol resolution interface for generating the synchronization indication signal based on the received I2C protocol resolution signal.

4. The clock phase control circuit of claim 3, wherein the I2C protocol resolution signal at least comprises an I2C bus read/write flag signal, a register address signal, a data transmission stop signal and an I2C bus clock signal, and the synchronization indication signal generator comprises:

the write judging unit is connected with the I2C protocol analysis interface and is used for generating a write confirmation signal when the I2C bus read-write mark signal is a write operation mark signal;

the address judgment unit is connected with the I2C protocol analysis interface and used for generating an address confirmation signal when the register address signal is a preset address signal;

the data judgment unit is connected with the I2C protocol analysis interface and used for generating a data confirmation signal when the data signal is a synchronization instruction signal;

the digital logic circuit is respectively connected with the writing judgment unit, the address judgment unit and the data judgment unit and is used for generating a synchronous indication trigger signal when the received writing confirmation signal, the address confirmation signal and the data confirmation signal are all preset signals; and

and the logic control circuit is respectively connected with the I2C protocol analysis interface, the digital logic circuit and the phase control module, and is used for receiving the data transmission stop signal, the I2C bus clock signal and the synchronization indication trigger signal, generating the synchronization indication signal according to the data transmission stop signal, the I2C bus clock signal and the synchronization indication trigger signal, and sending the synchronization indication signal to the phase control module.

5. The clock phase control circuit of claim 4, wherein the phase control module comprises:

a data input end D of the first quarter divider is connected to an output end of the logic control circuit, two reset ends of the first quarter divider are both connected to an input system reset signal, two clock signal input ends clk of the first quarter divider are both connected to a system clock signal output end of the clock generation module, and a first data latch output end Q of the first quarter divider is used for sending a set signal;

the input end of the phase inverter is connected with the output end of the logic control circuit;

and a data input end D of the second quarter frequency divider is connected with an output end of the direct-current power supply DVDD, two reset ends of the second quarter frequency divider are respectively connected with an output end of the phase inverter, two clock signal input ends clk of the second quarter frequency divider are respectively connected with a system clock signal output end of the clock generation module, and a first data latch output end Q of the second quarter frequency divider is used for sending out a reset signal.

6. The clock phase control circuit of claim 5, wherein the phase control module further comprises:

an input end of the edge detection unit is connected with a first data latch output end Q of the first quarter frequency divider, and an output end of the edge detection unit is used for outputting a set signal; or

And the input end of the pulse stretching unit is connected with the first data latch output end Q of the first quartering frequency divider, and the output end of the pulse stretching unit is used for outputting a setting signal.

7. The clock phase control circuit of claim 1, wherein the interface module comprises:

the I2C general interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating the clock enable signal and the clock phase control signal according to the clock signal and the clock phase parameter setting signal;

the I2S interface module, the output end of the I2S interface module is connected with the phase control module, the I2S interface module is used for receiving an I2S bus signal and generating the synchronization indication signal according to the I2S bus signal.

8. The clock phase control circuit of claim 1, wherein the interface module comprises:

the I2C general interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating the clock enable signal and the clock phase control signal according to the clock signal and the clock phase parameter setting signal;

and a synchronous interface module, a synchronous pin of which is connected with the phase control module, and the synchronous interface module provides the synchronous indication signal to the phase control module via the synchronous pin.

9. A power amplification device, comprising:

boost converter circuit, and

the clock phase control circuit of any one of claims 1-8, wherein the first operating clock signal output by the clock phase control circuit is used for controlling the power amplification device to start at a preset time, and the second operating clock signal output by the clock phase control circuit is used for controlling the phase delay of the boost converter circuit.

10. The power amplification apparatus according to claim 9, further comprising:

the starting module is used for starting the power amplifying device;

the output end of the first clock frequency divider is connected with the input end of the starting module and used for providing the first working clock signal for the starting module so as to control the starting module to start the power amplification device at a preset time, the output end of the second clock frequency divider is connected with the input end of the boost conversion circuit, and the second clock frequency divider provides the second working clock signal for the boost conversion circuit so as to control the boost conversion circuit to generate a preset phase delay.

11. An audio device, comprising:

the power amplification circuits comprise boost conversion circuits;

a plurality of clock phase control circuits according to any one of claims 1 to 8, the number of the clock phase control circuits being the same as the number of the power amplification circuits and the number of the boost converter circuits, the clock phase control circuits being connected to the power amplification circuits in a one-to-one manner, and the clock phase control circuits being connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, for controlling the power amplification circuits and the boost converter circuits therein, respectively;

the first working clock signal output by each clock phase control circuit is used for respectively controlling each power amplification circuit to start at a preset moment, and the second working clock signal output by each clock phase control circuit is used for respectively controlling each boost conversion circuit to generate a preset phase delay.

12. The audio device according to claim 11, wherein each of the first operating clock signals controls each of the power amplifying circuits to start up synchronously at a predetermined time, and each of the second operating clock signals controls each of the boost converting circuits to generate a predetermined phase delay starting from the predetermined time.

13. A clock phase control method is applied to a clock phase control circuit, the clock phase control circuit comprises an interface module, a clock generation module, a phase control module, a first clock frequency divider and a second clock frequency divider, and the method comprises the following steps:

controlling the interface module to generate a synchronization indication signal, a clock enable signal and a clock phase control signal based on the received clock signal and the clock phase parameter setting signal;

controlling the clock generation module to generate a system clock signal according to the clock enable signal;

controlling the phase control module to generate a set signal and a reset signal according to the clock phase control signal, the synchronous indication signal and the system clock signal;

controlling the first clock frequency divider to generate a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time;

and controlling the second clock frequency divider to generate a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit.

14. A clock phase control method applied to an audio apparatus including a plurality of power amplification circuits having boost conversion circuits, and a plurality of clock phase control circuits according to any one of claims 1 to 8, the number of the clock phase control circuits being the same as the number of the power amplification circuits and the number of the boost conversion circuits, the clock phase control circuits being connected to the power amplification circuits in a one-to-one manner, and the clock phase control circuits being connected to the boost conversion circuits of the power amplification circuits in a one-to-one manner, the method comprising:

generating a first working clock signal and a second working clock signal respectively by utilizing each clock phase control circuit according to the received clock signal and the clock phase parameter setting signal;

and respectively controlling the power amplifying circuits to start at a preset moment by using the first working clock signals, and respectively controlling the boosting conversion circuits to generate a preset phase delay by using the second working clock signals.

15. The clock phase control method of claim 14, wherein the controlling the power amplifier circuits to be activated at a predetermined time by the first operating clock signals and the generating the predetermined phase delay by the boost converter circuits by the second operating clock signals comprises:

and respectively controlling the power amplifying circuits to synchronously start at a preset moment by using the first working clock signals, and respectively controlling the boost converting circuits to generate a preset phase delay by using the preset moment as a starting point by using the second working clock signals.

16. The clock phase control method of claim 14, wherein the controlling the boost converter circuits to generate the predetermined phase delay by using the second operation clock signals respectively comprises:

respectively controlling N boosting conversion circuits to generate preset phase delay by utilizing N second working clock signals;

wherein the angle value α of the phase delay of the ith boost converter circuit_iCalculated according to the following formula:

in the above formula, i and N are positive integers, and N is the total number of the clock phase control circuits.

Technical Field

The present disclosure relates to the field of integrated circuit clock control technologies, and in particular, to a clock phase control circuit, a clock phase control method, a power amplifier, and an audio device.

Background

With the development of multimedia intelligent equipment and the improvement of the intelligent level of life of people, a plurality of audio power amplifiers are generally adopted in an audio system to realize a stereo effect, and the stereo equipment puts higher requirements on the setting of a working clock in a power amplifying circuit.

However, in the conventional stereo device, since the start time of each audio power amplifier is in sequence and the play delay of each independent audio power amplifier may have a difference, the data transmitted by the upper computer through the integrated circuit audio bus (inter sound, I2S) has a phase difference after being played by different audio power amplifiers, which results in a deterioration of sound effect. In addition, if the boost conversion circuits in different audio amplifiers in the stereo system are switched in phase, the load may increase the voltage generated by the load, which may cause the battery to be overloaded, and cause the device carrying the stereo system, such as a mobile phone or a tablet computer, to be turned off.

Disclosure of Invention

In view of the above, it is necessary to provide a clock phase control circuit, a method, a power amplification device, and an audio device capable of controlling a clock phase delay in order to solve the above-described problems in the related art.

A first aspect of the present application provides a clock phase control circuit, comprising:

the interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating a synchronization indication signal, a clock enable signal and a clock phase control signal according to the clock signal and the clock phase parameter setting signal;

the clock generation module is connected with the interface module and used for receiving the clock enabling signal and generating a system clock signal according to the clock enabling signal;

the phase control module is respectively connected with the interface module and the clock generation module, and is used for receiving the clock phase control signal, the synchronous indication signal and the system clock signal and generating a set signal and a reset signal according to the clock phase control signal, the synchronous indication signal and the system clock signal;

the first clock frequency divider is respectively connected with the phase control module and the clock generation module and used for receiving the system clock signal and the reset signal and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time;

and the second clock frequency divider is respectively connected with the phase control module and the clock generation module and used for receiving the system clock signal and the setting signal and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit.

In the clock phase control circuit in the above embodiment, an interface module receives a clock signal and a clock phase parameter setting signal, and generates a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; setting a clock generation module to receive the clock enabling signal and generate a system clock signal according to the clock enabling signal; a phase control module is arranged for receiving the clock phase control signal, the synchronous indication signal and the system clock signal, and generating a setting signal and a resetting signal according to the clock phase control signal, the synchronous indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit, such as a load, to start at a preset time; and receiving the system clock signal and the setting signal by using a second clock frequency divider, and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit. The first working clock signal can control the next-stage circuit to start at a preset moment, so that a reference is provided for controlling the clock phase delay of the next-stage circuit, and the second working clock signal can control the next-stage circuit to generate a preset phase delay.

In one embodiment, the interface module comprises:

the I2C general interface module is used for receiving the clock signal and the clock phase parameter setting signal and generating the clock enable signal, the enable signal and the address selection signal according to the clock signal and the clock phase parameter setting signal;

the I2C special interface module is connected with the I2C general interface module and used for receiving the clock signal, the enable signal and the address selection signal and generating the synchronization indication signal according to the clock signal, the enable signal and the address selection signal.

In the clock phase control circuit in the above embodiment, the setting interface module includes an I2C general interface module and an I2C special interface module, the I2C general interface module is used to receive the clock signal and the clock phase parameter setting signal, and the clock enable signal, the enable signal and the address selection signal are generated according to the clock signal and the clock phase parameter setting signal; the clock enable signal is used for controlling the clock generation module to generate a system clock signal so as to provide working clock signals for the phase control module, the first clock frequency divider and the second clock frequency divider; the enable signal and the address selection signal are used for enabling the I2C special interface module to generate the synchronization indication signal according to the received clock signal, the enable signal and the address selection signal, to control the phase control module to generate a set signal and a reset signal according to the received clock phase control signal, the synchronization indication signal and the system clock signal, therefore, the first clock frequency divider and the second clock frequency divider are further controlled to respectively generate the first working clock signal and the second working clock signal, the first working clock signal is utilized to control a subsequent circuit, such as a load, to be started at a preset time, the second working clock signal is utilized to control a subsequent circuit, such as a boost conversion circuit, to be phase-delayed, and the situation that the boost conversion circuit and the load extract current in the same direction to cause equipment battery overload and to cause equipment overheating and/or equipment automatic shutdown is avoided.

In one embodiment, the I2C specific interface module comprises:

an Inter-Integrated Circuit (I2C) protocol parsing interface, connected to the I2C universal interface module, for receiving the clock signal, the enable signal, and the address selection signal, and generating an I2C protocol parsing signal according to the clock signal, the enable signal, and the address selection signal;

a synchronization indication signal generator connected with the I2C protocol resolution interface for generating the synchronization indication signal based on the received I2C protocol resolution signal.

In the clock phase control circuit in the above embodiment, for example, the clock phase control circuit may be applied to phase delay control of a boost converter circuit in an audio power amplifier, since the operating clock of an I2C dedicated interface module including an I2C protocol analysis interface and a synchronization indication signal generator inside different audio power amplifiers is a clock signal of an I2C bus. Data can be input into the I2C protocol resolution interface through an I2C bus, an enable signal and an address selection signal can be input into the I2C protocol resolution interface through an I2C universal interface module, causing a synchronization indication signal generator to generate a synchronization indication signal based on the received I2C protocol resolution signal, to control a phase control module to output a set signal and a reset signal, therefore, the first clock frequency divider and the second clock frequency divider are further controlled to respectively generate the first working clock signal and the second working clock signal, the first working clock signal is utilized to control a subsequent circuit, such as a load, to be started at a preset time, the second working clock signal is utilized to control a subsequent circuit, such as a boost conversion circuit, to be phase-delayed, and the situation that the boost conversion circuit and the load extract current in the same direction to cause equipment battery overload and to cause equipment overheating and/or equipment automatic shutdown is avoided.

In one embodiment, the I2C protocol resolution signal at least comprises an I2C bus read/write flag signal, a register address signal, a data transmission stop signal and an I2C bus clock signal, and the synchronization indication signal generator comprises:

the write judging unit is connected with the I2C protocol analysis interface and is used for generating a write confirmation signal when the I2C bus read-write mark signal is a write operation mark signal;

the address judgment unit is connected with the I2C protocol analysis interface and used for generating an address confirmation signal when the register address signal is a preset address signal;

the data judgment unit is connected with the I2C protocol analysis interface and used for generating a data confirmation signal when the data signal is a synchronization instruction signal;

the digital logic circuit is respectively connected with the writing judgment unit, the address judgment unit and the data judgment unit and is used for generating a synchronous indication trigger signal when the received writing confirmation signal, the address confirmation signal and the data confirmation signal are all preset signals; and

and the logic control circuit is respectively connected with the I2C protocol analysis interface, the digital logic circuit and the phase control module, and is used for receiving the data transmission stop signal, the I2C bus clock signal and the synchronization indication trigger signal, generating the synchronization indication signal according to the data transmission stop signal, the I2C bus clock signal and the synchronization indication trigger signal, and sending the synchronization indication signal to the phase control module.

In the clock phase control circuit in the above embodiment, the write determining unit is configured to send a write acknowledge signal when the I2C bus read-write flag signal is a write operation flag signal; the setting address judgment unit sends an address confirmation signal when the register address signal is a preset address signal; the data setting judgment unit sends out a data confirmation signal when the data signal is a synchronous indication instruction signal; setting a digital logic circuit to generate a synchronous indication trigger signal when the write acknowledgement signal, the address acknowledgement signal and the data acknowledgement signal are all corresponding preset signals; a logic control circuit is arranged to generate a synchronous indication signal based on an I2C bus clock signal and a data transmission stop signal sent by an I2C protocol analysis interface and the synchronous indication trigger signal, so that a phase control module can generate a set signal and a reset signal based on the synchronous indication signal, and then a first clock frequency divider is used to generate a first working clock signal based on a received system clock signal and the reset signal, so as to control a next-stage circuit to start at a preset time; and generating a second working clock signal by using a second clock frequency divider based on the received system clock signal and the setting signal so as to control a next-stage circuit to generate a preset phase delay.

In one embodiment, the phase control module comprises:

a data input end D of the first quarter divider is connected to an output end of the logic control circuit, two reset ends of the first quarter divider are both connected to an input system reset signal, two clock signal input ends clk of the first quarter divider are both connected to a system clock signal output end of the clock generation module, and a first data latch output end Q of the first quarter divider is used for sending a set signal;

the input end of the phase inverter is connected with the output end of the logic control circuit;

and a data input end D of the second quarter frequency divider is connected with an output end of the direct-current power supply DVDD, two reset ends of the second quarter frequency divider are respectively connected with an output end of the phase inverter, two clock signal input ends clk of the second quarter frequency divider are respectively connected with a system clock signal output end of the clock generation module, and a first data latch output end Q of the second quarter frequency divider is used for sending out a reset signal.

In the clock phase control circuit in the above embodiment, the second quarter frequency divider is configured to send a system clock signal to send a reset signal based on the obtained inverted signal of the synchronization indication signal and the clock generation module, so that the first clock frequency divider generates a first working clock signal based on the received system clock signal and the reset signal to control the subsequent stage of circuit to start at a preset time; the first four-frequency divider is arranged to send out a set signal based on the obtained synchronous indication signal and the system clock signal sent by the clock generation module, so that the second clock frequency divider generates a second working clock signal based on the received system clock signal and the set signal to control the next-stage circuit to generate a preset phase delay.

In one embodiment, the phase control module further comprises:

an input end of the edge detection unit is connected with a first data latch output end Q of the first quarter frequency divider, and an output end of the edge detection unit is used for outputting a set signal; or

And the input end of the pulse stretching unit is connected with the first data latch output end Q of the first quartering frequency divider, and the output end of the pulse stretching unit is used for outputting a setting signal.

In the clock phase control circuit in the above embodiment, an edge detection unit is added to the phase control module to detect a rising edge or a falling edge in the set signal output by the first divide-by-four divider; or a pulse stretching unit is added in the phase control module to stretch the pulse in the setting signal output by the first quartering frequency divider, so as to improve the width of the pulse in the setting signal, and improve the accuracy of the second clock frequency divider for generating the second working clock signal based on the setting signal to control the next-stage circuit to generate the preset phase delay.

In one embodiment, the interface module comprises:

the I2C general interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating the clock enable signal and the clock phase control signal according to the clock signal and the clock phase parameter setting signal;

the I2S interface module, the output end of the I2S interface module is connected with the phase control module, the I2S interface module is used for receiving an I2S bus signal and generating the synchronization indication signal according to the I2S bus signal.

In the clock phase control circuit in the above embodiment, the I2S interface module may be utilized to generate the synchronous indication signal based on the received I2S bus signal, so as to provide the synchronous indication signal to the phase control module, and may control the boost converter circuits in a plurality of different power amplifier circuits to generate phase delays according to preset phase differences, so as to implement accurate control of the phase delays of the boost converter circuits in different power amplifier circuits, and avoid the occurrence of a situation that the phase delays of the boost converter circuits cannot be accurately controlled due to asynchronous starting of the boost converter circuits in the case of controlling the boost converter circuits in a plurality of power amplifier circuits simultaneously.

In one embodiment, the interface module comprises:

the I2C general interface module is used for receiving a clock signal and a clock phase parameter setting signal and generating the clock enable signal and the clock phase control signal according to the clock signal and the clock phase parameter setting signal;

and a synchronous interface module, a synchronous pin of which is connected with the phase control module, and the synchronous interface module provides the synchronous indication signal to the phase control module via the synchronous pin.

In the clock phase control circuit in the above embodiment, a synchronization pin of the synchronization interface module may be connected to the phase control module to provide the synchronization indication signal to the phase control module, and the boost converter circuits in the different power amplifier circuits may be controlled to generate phase delays according to preset phase differences, so as to implement accurate control of the phase delays of the boost converter circuits in the different power amplifier circuits, and avoid occurrence of a situation that the phase delays of the boost converter circuits cannot be accurately controlled due to asynchronous start of each power amplifier circuit when the boost converter circuits in the multiple power amplifier circuits are controlled simultaneously.

A second aspect of the present application provides a power amplifying device comprising:

boost converter circuit, and

in any of the embodiments of the present application, the first working clock signal output by the clock phase control circuit is used to control the power amplification device to start at a preset time, and the second working clock signal output by the clock phase control circuit is used to control the phase delay of the boost converter circuit.

In the power amplifying device in the above embodiment, an interface module may receive a clock signal and a clock phase parameter setting signal, and generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; setting a clock generation module to receive the clock enabling signal and generate a system clock signal according to the clock enabling signal; a phase control module is arranged for receiving the clock phase control signal, the synchronous indication signal and the system clock signal, and generating a setting signal and a resetting signal according to the clock phase control signal, the synchronous indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a power amplification device to start at a preset time; and receiving the system clock signal and the setting signal by using a second clock frequency divider, and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of the boost conversion circuit. The power amplifying device can be controlled to start at a preset time by the first working clock signal, so that a reference is provided for controlling the clock phase delay of the boost conversion circuit, and the boost conversion circuit is controlled to generate the preset phase delay by the second working clock signal.

In one embodiment, the power amplifying device further comprises a starting module, wherein the starting module is used for starting the power amplifying device; the output end of the first clock frequency divider is connected with the input end of the starting module and used for providing the first working clock signal for the starting module so as to control the starting module to start the power amplification device at a preset time, the output end of the second clock frequency divider is connected with the input end of the boost conversion circuit, and the second clock frequency divider provides the second working clock signal for the boost conversion circuit so as to control the boost conversion circuit to generate a preset phase delay.

A third aspect of the present application provides an audio device comprising:

the power amplification circuits comprise boost conversion circuits;

a plurality of clock phase control circuits according to any one of the embodiments of the present application, where the number of the clock phase control circuits is the same as the number of the power amplification circuits and the number of the boost converter circuits, the clock phase control circuits are connected to the power amplification circuits in a one-to-one manner, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, so as to control the power amplification circuits and the boost converter circuits therein, respectively;

the first working clock signal output by each clock phase control circuit is used for respectively controlling each power amplification circuit to start at a preset moment, and the second working clock signal output by each clock phase control circuit is used for respectively controlling each boost conversion circuit to generate a preset phase delay.

In the audio device in the above embodiment, an interface module may receive a clock signal and a clock phase parameter setting signal, and generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; setting a clock generation module to receive the clock enabling signal and generate a system clock signal according to the clock enabling signal; a phase control module is arranged for receiving the clock phase control signal, the synchronous indication signal and the system clock signal, and generating a setting signal and a resetting signal according to the clock phase control signal, the synchronous indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal; and receiving the system clock signal and the setting signal by using a second clock frequency divider, and generating a second working clock signal according to the system clock signal and the setting signal. The first working clock signal output by each clock phase control circuit can respectively control each power amplifying circuit to start at a preset moment, and the second working clock signal output by each clock phase control circuit can respectively control the boost conversion circuit in each power amplifying circuit to delay according to a preset phase difference, so that the delay control of the clock phases of the boost conversion circuits in a plurality of different power amplifying circuits is realized, and the overload phenomenon caused by the same-direction switching of each boost conversion circuit is avoided.

In one embodiment, each of the first operating clock signals respectively controls each of the power amplifying circuits to start up synchronously at a preset time, and each of the second operating clock signals respectively controls each of the boost converting circuits to generate a preset phase delay with the preset time as a starting point.

In the audio device in the above embodiment, the first working clock signal output by each clock phase control circuit respectively controls each power amplification circuit to start synchronously at a preset time, and the second working clock signal output by each clock phase control circuit respectively controls the boost conversion circuit in each power amplification circuit to generate a preset phase delay with the preset time as a starting point, so as to implement accurate delay control on the clock phases of the boost conversion circuits in a plurality of different power amplification circuits, and avoid overload phenomenon caused by same-direction switching of each boost conversion circuit.

A fourth aspect of the present application provides a clock phase control method applied to a clock phase control circuit, where the clock phase control circuit includes an interface module, a clock generation module, a phase control module, a first clock divider, and a second clock divider, and the method includes:

controlling the interface module to generate a synchronization indication signal, a clock enable signal and a clock phase control signal based on the received clock signal and the clock phase parameter setting signal;

controlling the clock generation module to generate a system clock signal according to the clock enable signal;

controlling the phase control module to generate a set signal and a reset signal according to the clock phase control signal, the synchronous indication signal and the system clock signal;

controlling the first clock frequency divider to generate a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time;

and controlling the second clock frequency divider to generate a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit.

In the clock phase control method in the foregoing embodiment, a control interface module may receive a clock signal and a clock phase parameter setting signal, and control the interface module to generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; controlling a clock generation module to generate a system clock signal based on the received clock enable signal; the control phase control module generates a set signal and a reset signal based on the received clock phase control signal, the synchronization indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time; and receiving the system clock signal and the setting signal by using a second clock frequency divider, and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit. The first working clock signal can control the next-stage circuit to start at a preset moment, so that a reference is provided for controlling the clock phase delay of the next-stage circuit, and the second working clock signal can control the next-stage circuit to generate a preset phase delay.

A fifth aspect of the present application provides a clock phase control method, which is applied to an audio device, where the audio device includes a plurality of power amplification circuits having boost converter circuits, and a plurality of clock phase control circuits as described in any of the embodiments of the present application, the number of the clock phase control circuits is the same as the number of the power amplification circuits and the number of the boost converter circuits, the clock phase control circuits are connected to the power amplification circuits in a one-to-one manner, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, where the method includes:

generating a first working clock signal and a second working clock signal respectively by utilizing each clock phase control circuit according to the received clock signal and the clock phase parameter setting signal;

and respectively controlling the power amplifying circuits to start at a preset moment by using the first working clock signals, and respectively controlling the boosting conversion circuits to generate a preset phase delay by using the second working clock signals.

In the clock phase control method in the above embodiment, an interface module may receive a clock signal and a clock phase parameter setting signal, and generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; setting a clock generation module to receive the clock enabling signal and generate a system clock signal according to the clock enabling signal; a phase control module is arranged for receiving the clock phase control signal, the synchronous indication signal and the system clock signal, and generating a setting signal and a resetting signal according to the clock phase control signal, the synchronous indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal can respectively control each power amplification circuit to start at a preset time; and a second clock frequency divider is used for receiving the system clock signal and the setting signal and generating a second working clock signal according to the system clock signal and the setting signal, and the second working clock signal can respectively control each boost conversion circuit to generate preset phase delay so as to realize delay control of the clock phase of the boost conversion circuit in a plurality of different power amplification circuits and avoid overload phenomenon caused by same-direction switching of each boost conversion circuit.

In one embodiment, the respectively controlling the power amplifying circuits to start at a preset time by using the first operating clock signals and the respectively controlling the boost converting circuits to generate a preset phase delay by using the second operating clock signals includes:

and respectively controlling the power amplifying circuits to synchronously start at a preset moment by using the first working clock signals, and respectively controlling the boost converting circuits to generate a preset phase delay by using the preset moment as a starting point by using the second working clock signals.

In the clock phase control method in the above embodiment, the first working clock signal output by each clock phase control circuit is used to control each power amplification circuit to start synchronously at a preset time, so as to control each boost conversion circuit to generate a preset phase delay with the preset time as a starting point by using the second working clock signal, thereby implementing accurate control of the phase delay of the boost conversion circuit in different power amplification circuits, and avoiding the occurrence of the situation that the phase delay of each boost conversion circuit cannot be accurately controlled due to asynchronous starting of each power amplification circuit under the condition that the boost conversion circuits in a plurality of power amplification circuits are controlled simultaneously.

In one embodiment, the controlling, by the second operating clock signal, the boost converter circuits to generate the predetermined phase delay includes:

respectively controlling N boosting conversion circuits to generate preset phase delay by utilizing N second working clock signals;

wherein the angle value α of the phase delay of the ith boost converter circuit_iCalculated according to the following formula:

in the above formula, i and N are positive integers, and N is the total number of the clock phase control circuits.

In the clock phase control method in the above embodiment, under the condition of simultaneously controlling the boost converter circuits in one or more different power amplifier circuits, a specific setting formula for the phase delay angle value of each boost converter circuit is provided, so as to more conveniently and reasonably control the phase delay angle of each boost converter circuit, and better control the next stage of circuit, such as load peak shifting current extraction, and ensure the stability of current or voltage output to the load.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.

Fig. 1 is a schematic circuit diagram of a clock phase control circuit provided in a first embodiment of the present application.

Fig. 2 is a schematic circuit diagram of a clock phase control circuit provided in a second embodiment of the present application.

Fig. 3 is a schematic circuit diagram of an I2C specific interface module in a clock phase control circuit provided in a third embodiment of the present application.

Fig. 4 is a schematic circuit diagram of an I2C specific interface module in a clock phase control circuit provided in a fourth embodiment of the present application.

Fig. 5 is a schematic circuit diagram of a phase control module in a clock phase control circuit provided in a fifth embodiment of the present application.

Fig. 6 is a schematic circuit diagram of a phase control module in a clock phase control circuit according to a sixth embodiment of the present application.

Fig. 7 is a schematic circuit diagram of a phase control module in a clock phase control circuit according to a seventh embodiment of the present application.

Fig. 8 is a schematic circuit diagram of a clock phase control circuit provided in an eighth embodiment of the present application.

Fig. 9 is a schematic circuit diagram of a clock phase control circuit provided in a ninth embodiment of the present application.

Fig. 10 is a schematic diagram of an architecture of a power amplifying device provided in a tenth embodiment of the present application.

Fig. 11 is a schematic diagram of a power amplifying device according to an eleventh embodiment of the present application.

Fig. 12 is a schematic structural diagram of an audio device provided in a twelfth embodiment of the present application.

Fig. 13 is a timing diagram of clock phase control of an audio device according to a thirteenth embodiment of the present application.

Fig. 14 is a flowchart illustrating a clock phase control method according to a fourteenth embodiment of the present application.

Fig. 15 is a flowchart illustrating a clock phase control method according to a fifteenth embodiment of the present application.

Fig. 16 is a flowchart illustrating a clock phase control method according to a sixteenth embodiment of the present application.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or several of the associated listed items.

Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.

In this application, unless otherwise expressly stated or limited, the terms "connected" and "connecting" are used broadly and encompass, for example, direct connection, indirect connection via an intermediary, communication between two elements, or interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, the term "number" may be one or more.

As shown in fig. 1, a clock phase control circuit 100 provided in an embodiment of the present application includes an interface module 10, a clock generation module 20, a phase control module 30, a first clock divider 40 and a second clock divider 50, the interface module 10 is configured to receive a clock signal and a clock phase parameter setting signal, and generate a synchronization indication signal, a clock enable signal and a clock phase control signal according to the clock signal and the clock phase parameter setting signal, the clock generation module 20 is connected to the interface module 10 and is configured to receive the clock enable signal and generate a system clock signal SC L according to the clock enable signal, the phase control module 30 is connected to the interface module 10 and the clock generation module 20 respectively and is configured to receive the clock phase control signal, the synchronization indication signal and the system clock signal, and is configured to generate a set signal ZW or a reset signal FW according to the clock phase control signal, the first clock divider 40 is connected to the phase control module 30 and the clock generation module 20 respectively and is configured to receive the system clock signal SC 634 and the reset signal, and is configured to generate a set signal FW or reset signal FW 48 according to a clock signal sw 465 and a clock signal sw 4648, the clock signal sw 5 and a clock signal sw 4648 after a first clock signal is connected to control a first stage of a BOOST load control circuit, and a stage of a BOOST load control circuit, which is configured to generate a BOOST load control signal, and a stage of a BOOST load control circuit, such as a BOOST load control circuit, a BOOST load control circuit according to generate a BOOST load control circuit, a load control circuit working.

Furthermore, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 2, an interface module 10 includes an I2C general interface module 11 and an I2C specific interface module 12, the I2C general interface module 11 is configured to receive a clock signal and a clock phase parameter setting signal sent by an I2C bus 60, the I2C general interface module 11 generates a clock enable signal and a clock phase control signal according to the received clock signal and the clock phase parameter setting signal, the clock generation module 20 is connected to the I2C general interface module 11 and is configured to receive the clock enable signal and generate a system clock signal SC L according to the received clock signal and the received clock phase parameter setting signal, the I2C specific interface module 12 is connected to the I2C general interface module 11, the I2C specific interface module 12 receives the clock signal and the clock phase parameter setting signal of an I2C bus 60 and generates a synchronization indication signal TZ 36z based on the received clock signal and the received clock phase parameter setting signal, the clock signal L is a clock signal indicating a clock signal of an I2 signal and a clock signal after a clock signal sw C and a clock signal sw C and a clock signal sw C and a reset signal sw C and a set C, and a clock signal sw and a clock signal sw and a signal sw and a signal sw and a signal sw and a signal sw.

For example, the clock Phase control circuit in the above embodiment may be applied to an audio power amplification apparatus (audio power amplifier circuit for short), the BOOST conversion circuit in the audio power amplifier circuit is taken as an example to illustrate the operating principle of this embodiment, the subsequent stage circuit in this embodiment is an audio power amplifier circuit, a clock signal and a clock Phase parameter setting signal may be provided to the I2C universal interface module 11 through the I2C bus 60, register parameter configuration of the audio power amplifier circuit is realized by using the clock Phase parameter setting signal, for example, an operating clock Phase control parameter of the BOOST conversion circuit of the audio power amplifier circuit, a device address of the I2C specific interface module 12 and an enable switch of the clock generation module 20 may be configured, the clock generation module 20 may issue a system clock signal SC L based on a clock enable signal issued by the I2C universal interface module 11, the system clock signal SC L serves as the clock signal of the Phase control module 30, the first clock frequency divider 40 and the operating clock signal of the second clock frequency divider 50, the Phase control module 30 may issue a clock signal as a clock signal for generating a clock signal according to a clock signal for generating a clock signal sw C, a clock signal sw 466 and a clock signal for generating a set signal, a clock signal sw 465 signal, a set signal, and a clock signal connected to generate a clock signal, a clock signal FW., a clock signal, and a clock signal for generating signal according to a clock signal, a clock signal set signal sw 465 signal sw 2 signal, a clock signal sw 466 signal, a clock signal set signal, a clock signal.

Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 3, the I2C dedicated interface module 12 may include an I2C protocol parsing interface 121 and a synchronization indication signal generator 122. The I2C protocol resolution interface 121 is connected to the I2C universal interface module 11 shown in fig. 2, and is configured to receive an enable signal and an address selection signal sent by the I2C universal interface module 11, and the I2C protocol resolution interface 121 generates an I2C protocol resolution signal according to the enable signal and the address selection signal; the synchronization indication signal generator 122 is connected to the I2C protocol parsing interface 121, and is configured to generate a synchronization indication signal TZ based on the received I2C protocol parsing signal. The synchronization indication signal TZ may be a high level signal or a low level signal to trigger the phase control module to generate the set signal ZW or the reset signal FW. The reset signal FW may be an asynchronous reset signal, and the first clock divider generates a first working clock signal based on the received system clock signal and the reset signal to control a subsequent circuit, such as a power amplifier, to start at a preset time; the setting signal ZW may be a synchronous setting signal, so that the second clock divider generates a second working clock signal based on the received system clock signal and the setting signal, and according to the system clock signal and the setting signal, so as to control a subsequent stage of circuit, such as a boost converter circuit in the power amplifier device, to generate a preset phase delay. The first working clock signal can control the power amplification device to start at a preset moment, so that a reference is provided for controlling the clock phase delay of the boost conversion circuit in the power amplification device, the boost conversion circuit is controlled to generate the preset phase delay through the second working clock signal, and the condition that the device battery is overloaded and the device is overheated and/or the device is automatically shut down due to the fact that the boost conversion circuit and the power amplification device extract current in the same direction is avoided.

Further, in the clock phase control circuit in the above embodiment, the I2C protocol analyzing signal at least includes an I2C bus read/write flag signal, a register address signal, a data transmission stop signal, and an I2C bus clock signal. As shown in fig. 3, the synchronization indication signal generator 122 includes a write judging unit 1221, an address judging unit 1222, a data judging unit 1223, a digital logic circuit 1224, and a logic control circuit 1225. The write determining unit 1221 is connected to the I2C protocol parsing interface 121, and configured to generate a write confirmation signal when the read/write flag signal of the I2C bus 60 is a write operation flag signal; the address determining unit 1222 is connected to the I2C protocol resolution interface 121, and configured to generate an address acknowledgement signal when the register address signal is a preset address signal; the data determining unit 1223 is connected to the I2C protocol parsing interface 121, and is configured to generate a data acknowledgement signal when the data signal is a synchronization instruction signal; the digital logic circuit 1224 is respectively connected to the write determining unit 1221, the address determining unit 1222 and the data determining unit 1223, and configured to generate a synchronization indication trigger signal when the received write acknowledge signal, the address acknowledge signal and the data acknowledge signal are all preset signals; the logic control circuit 1225 is respectively connected to the I2C protocol parsing interface 121, the digital logic circuit 1224, and the phase control module, and is configured to receive the data transmission stop signal, the I2C bus clock signal, and the synchronization indication trigger signal, generate the synchronization indication signal according to the data transmission stop signal, the I2C bus clock signal, and the synchronization indication trigger signal, and send the synchronization indication signal TZ to the phase control module.

Specifically, in the clock phase control circuit in the above embodiment, as shown in fig. 3, the write determining unit 1221 is configured to send a write confirmation signal, for example, a high level signal, when the read/write flag signal of the I2C bus 60 is the write operation flag signal; the set address determining unit 1222 sends an address acknowledge signal, such as a high level signal, when the register address signal is a preset address signal; the setting data judgment unit 1223 sends a data confirmation signal, for example, a high level signal, when the data signal is a synchronization instruction signal; setting the digital logic circuit 1224 to generate a synchronization indication trigger signal when the write acknowledge signal, the address acknowledge signal and the data acknowledge signal are all preset signals, such as high level signals; a logic control circuit 1225 is set to send a synchronization indication signal TZ based on an I2C bus clock signal and a data transmission stop signal sent by the I2C protocol analysis interface 121, and the synchronization indication trigger signal, so that the phase control module can generate a set signal and a reset signal based on the synchronization indication signal, and further generate a first working clock signal based on a received system clock signal and the reset signal by using a first clock frequency divider to control a next stage circuit to start at a preset time; and generating a second working clock signal by using a second clock frequency divider based on the received system clock signal and the setting signal so as to control a next-stage circuit to generate a preset phase delay. For example, the synchronization indication signal may be set to be a high level signal, and the duration value of the high level may be set to be greater than or equal to a period value of one I2C bus clock, so that the I2C specific interface module may completely acquire the enable signal and the address selection signal sent by the I2C general interface module, thereby improving the accuracy of clock phase control.

Further, in a clock phase control circuit provided in an embodiment of the present application, as shown in fig. 4, the synchronization indication signal generator 122 may be configured to include a write determining unit 1221, an address determining unit 1222, a data determining unit 1223, an and gate and a first D flip-flop DFF1, where the and gate is a specific implementation of the digital logic circuit 1224, and the first D flip-flop DFF1 is a specific implementation of the logic control circuit 1225. The write judging unit 1221 is configured to send a write confirmation signal when the read/write flag signal of the I2C bus is a write operation flag signal; the address determining unit 1222 is configured to send an address acknowledge signal when the register address signal is a preset address signal; the data determining unit 1223 is configured to send a data confirmation signal when the data signal is a synchronization instruction signal; the AND gate is used for generating a synchronous indication trigger signal when the write confirmation signal, the address confirmation signal and the data confirmation signal are all high-level signals; a data input end D of the first D flip-flop DFF1 is connected with an output end of the AND gate, a clock signal input end clk of the first D flip-flop DFF1 is connected with an I2C bus clock signal output end of the I2C protocol analysis interface 121, and a first data latch output end Q of the first D flip-flop DFF1 is connected with the phase control module to provide a synchronization indication signal for the phase control module; the reset terminal of the first D flip-flop DFF1 is connected to the data transmission stop signal output terminal of the I2C protocol parsing interface 121, for example, the synchronization indication signal may be set to be a high level signal when the data transmission stop signal is 1, when the data transmission stop signal is reset to zero, the synchronization indication signal is reset to zero, and the duration of the high level of the synchronization indication signal is greater than or equal to one cycle of the system clock signal, so that the integrity and validity of data transmission by the write determining unit 1221, the address determining unit 1222, and the data determining unit 1223 are ensured, and the I2C dedicated interface module can completely acquire the enable signal and the address selection signal sent by the I2C universal interface module.

Further, in a clock phase control circuit provided in an embodiment of the present application, as shown in fig. 5, the phase control module 30 includes a first divide-by-four unit 31, an inverter 33, and a second divide-by-four unit 32. A data input end D of the first fourth frequency divider 31 is connected with a first data latch output end Q of the first D flip-flop DFF1, two reset ends of the first fourth frequency divider 31 are respectively used for inputting a system reset signal, two clock signal input ends clk of the first fourth frequency divider 31 are respectively connected with a system clock signal output end of the clock generation module, and the first data latch output end Q of the first fourth frequency divider 31 is used for sending a set signal ZW; a data input end D of the second quarter frequency divider 32 is connected with an output end of the dc power supply DVDD, two reset ends of the second quarter frequency divider 32 are respectively connected with an output end of the inverter 33, two clock signal input ends clk of the second quarter frequency divider 32 are respectively connected with a system clock signal output end of the clock generation module, and a first data latch output end Q of the second quarter frequency divider 32 is used for sending out a reset signal FW; an input terminal of the inverter 33 is connected to the first data latch output terminal Q of the first D flip-flop DFF 1. In this embodiment, the system reset signal may be issued by system reset terminal 34.

In the clock phase control circuit in the above embodiment, the first four-frequency divider is configured to send out the set signal based on the obtained synchronization indication signal and the clock generation module to send out the system clock signal, so that the first clock frequency divider generates the first operating clock signal C L K48K based on the received system clock signal SC L and the reset signal FW, the first operating clock signal C L K48K is used to control the subsequent stage circuit, for example, the load is started at a preset time, and the second clock frequency divider generates the second operating clock signal BOOST _ C L K based on the received system clock signal SC L and the set signal ZW, so as to control the subsequent stage circuit, for example, the BOOST converter circuit, to generate a preset phase delay.

Further, as shown in fig. 5, the first fourth frequency divider 31 includes a second D flip-flop DFF2 and a third D flip-flop DFF3, a first data latch output Q of the second D flip-flop DFF2 is connected to a data input D of the third D flip-flop DFF3, clock signal inputs clk of the second D flip-flop DFF2 and the third D flip-flop DFF3 are both connected to a system clock signal output of the clock generation module, reset terminals of the second D flip-flop DFF2 and the third D flip-flop DFF3 are both connected to the system reset terminal 34, a data input D of the second D flip-flop DFF2 is connected to a first data latch output Q of the first D flip-flop DFF1, and a first data latch output Q of the third D flip-flop DFF3 is connected to the second clock frequency divider. The synchronization indication signal output from the first data latch output Q of the first D flip-flop DFF1 is processed by the second D flip-flop DFF2 and the third D flip-flop DFF3 in sequence, and then the set signal ZW is output from the first data latch output Q of the third D flip-flop DFF 3. The second fourth frequency divider 32 includes a fourth D flip-flop DFF4 and a fifth D flip-flop DFF5, a first data latch output Q of the fourth D flip-flop DFF4 is connected to a data input D of the fifth D flip-flop DFF5, clock signal inputs clk of the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are connected to a system clock signal output terminal of the clock generation module, reset terminals of the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 are connected to an output terminal of the inverter 33, the data input D of the fourth D flip-flop DFF4 is connected to an output terminal of the dc power source DVDD, and a first data latch output Q of the fifth D flip-flop DFF5 is connected to an input terminal of the first clock frequency divider to output the reset signal FW to the first clock frequency divider. The sync indication signal output from the first data latch output Q of the first D flip-flop DFF1 passes through the inverter, the fourth D flip-flop DFF4 and the fifth D flip-flop DFF5 in sequence, and then the reset signal FW is output from the first data latch output Q of the fifth D flip-flop DFF 5.

Further, in a clock phase control circuit provided in an embodiment of the present application, as shown in fig. 6, the phase control block 30 further includes an edge detection unit 35, an input terminal of the edge detection unit 35 is connected to the first data latch output terminal Q of the third D flip-flop DFF3, and an output terminal of the edge detection unit 35 is configured to output the set signal ZW. By adding the edge detection unit in the phase control module for detecting the rising edge or the falling edge in the set signal output by the first quarter frequency divider, the accuracy of the second clock frequency divider for generating the second working clock signal based on the set signal to control the phase delay of the subsequent stage circuit, such as the boost converter circuit, can be improved.

Further, in a clock phase control circuit provided in an embodiment of the present application, as shown in fig. 7, the phase control module 30 further includes a pulse stretching unit 36, an input terminal of the pulse stretching unit 36 is connected to the first data latch output terminal Q of the third D flip-flop DFF3, and an output terminal of the pulse stretching unit 36 is configured to output the set signal ZW. By adding the pulse stretching unit in the phase control module, the pulse in the setting signal output by the first quartering frequency divider is stretched to improve the width of the pulse in the setting signal, so that the accuracy of the second clock frequency divider for generating the second working clock signal based on the setting signal to control the phase delay of the subsequent stage circuit, such as the boost conversion circuit, can be improved.

Furthermore, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 8, an interface module 10 includes an I2C universal interface module 11 and an I2S interface module 13, an output terminal of the I2S interface module 13 is connected to a phase control module 30, the I2S interface module 13 may receive a signal sent from an I2S bus 70 and generate a synchronization indication signal TZ according to a received I2S bus signal, the I2C universal interface module 11 is configured to receive a clock signal and a clock phase parameter setting signal sent from an I2C bus 60, the I2C universal interface module 11 generates a clock enable signal and a clock phase control signal according to the received clock signal and the clock phase parameter setting signal, the clock generation module 20 is connected to the I2C universal interface module 11 and is configured to receive the clock enable signal and generate a system clock signal SC 5 according to the clock enable signal, the clock generation module 30 is connected to the I2C universal interface module 11, the I S interface module 13 and the clock generation module 20 is configured to generate a clock signal SC 5 according to a clock enable signal and a clock signal, the clock signal after receiving a clock signal, the clock signal is connected to a clock phase control signal, the clock phase control module 30 is connected to a clock signal sw 595, the clock signal sw S and a clock signal sw 3648, the clock signal sw 3648 is connected to generate a clock signal sw 3648, the clock signal sw 3648 is connected to generate a clock signal, the clock signal after receiving a clock signal, the clock signal sw 59k signal, the clock signal sw 59k signal and the clock signal sw 59k signal sw 27 signal, the clock signal sw 59k signal sw 27 signal sw 27 is connected to generate a clock signal, the clock signal sw 59k signal sw 27 and the clock signal sw 27 and the clock signal sw 59k signal sw 27 and the.

Further, in a clock phase control circuit 100 provided in an embodiment of the present application, as shown in fig. 9, the interface module 10 includes an I2C general interface module 11 and a synchronization interface module 14, the synchronization interface module 14, which may be a synchronization pin, for example, is connected to the phase control module 30, and the synchronization interface module 14 provides a synchronization indication signal TZ to the phase control module 30 via the synchronization pin. In this embodiment, the synchronization interface module 14 is used to replace the I2S interface module 13 shown in fig. 8 to provide the synchronization indication signal TZ to the phase control module 30, so that the working principle of this embodiment may refer to the working principle of the embodiment shown in fig. 8, and is not described here again.

In a power amplifying device 200 provided in an embodiment of the present application, as shown in fig. 10, a boost converter circuit 201 and a clock phase control circuit 100 described in any of the embodiments of the present application are included. The clock phase control circuit 100 generates a first working clock signal and a second working clock signal based on the received clock signal and the clock phase parameter setting signal, the first working clock signal is used for controlling the power amplification device 200 to start at a preset time, the second working clock signal output by the clock phase control circuit 100 is used for controlling the phase delay of the boost converter circuit 201, and since the power amplification device 200 can be controlled to start at the preset time by the first working clock signal, a reference is provided for controlling the phase delay of the boost converter circuit 201, so that the boost converter circuit 201 is controlled to generate the preset phase delay by the second working clock signal.

Further, in a power amplifying device 200 provided in an embodiment of the present application, as shown in fig. 11, a starting module 202 is further included, where the starting module 202 is configured to start the power amplifying device 200; the output end of the first clock frequency divider 40 in the clock phase control circuit 100 is connected to the input end of the start module 202, and is configured to provide the first working clock signal to the start module 202, so as to control the start module 202 to start the power amplification apparatus 200 at a preset time, the output end of the second clock frequency divider 50 is connected to the input end of the boost converter circuit 201, and the second clock frequency divider 50 provides the second working clock signal to the boost converter circuit 201, so as to control the boost converter circuit 201 to generate a preset phase delay, and avoid that the current drawn by the boost converter circuit and the current drawn by the power amplification apparatus 200 start to be superposed in the same direction, so that the power supply battery is overloaded.

In an embodiment of the present application, an audio device includes a plurality of power amplifying circuits, for example, one or at least two power amplifying circuits, and a plurality of clock phase control circuits, where the number of the clock phase control circuits is the same as the number of the power amplifying circuits and the number of the boost converter circuits in the power amplifying circuits, the clock phase control circuits are connected to the power amplifying circuits in a one-to-one manner, and the clock phase control circuits are connected to the boost converter circuits of the power amplifying circuits in a one-to-one manner. A plurality of power amplifying circuits are taken as an example for explanation, wherein each power amplifying circuit comprises a boost conversion circuit; a plurality of clock phase control circuits as provided in any of the embodiments of the present application, configured to control the corresponding power amplification circuits and the boost conversion circuits therein, respectively; the first working clock signal output by each clock phase control circuit is used for controlling each power amplification circuit to start at a preset time, and the second working clock signal output by each clock phase control circuit is used for controlling each boost conversion circuit to generate a preset phase delay.

Preferably, each of the first operating clock signals respectively controls each of the power amplifying circuits to start synchronously at a preset time, and each of the second operating clock signals respectively controls each of the boost converting circuits to generate a preset phase delay with the preset time as a starting point.

Preferably, the N second working clock signals are used for respectively controlling the N boost conversion circuits to generate preset phase delay, wherein the angle value α of the phase delay of the ith boost conversion circuit_iCalculated according to the following formula:

in the above formula, i and N are positive integers, and N is the total number of the clock phase control circuits, that is, the number of the clock phase control circuits, the number of the power amplification circuits, and the number of the boost conversion circuits in the power amplification circuits are both N.

Specifically, as shown in fig. 12, in an audio device 300 provided in an embodiment of the present application, the audio device includes a power amplifier circuit a, a power amplifier circuit B, a power amplifier circuit C, a power amplifier circuit D, and a clock phase control circuit a, a clock phase control circuit B, a clock phase control circuit C, and a clock phase control circuit D. the power amplifier circuit a, the power amplifier circuit B, the power amplifier circuit C, and the clock phase control circuit D may transmit data via an I2C bus 60 respectively through a control circuit 80 to complete configuration of parameters of the power amplifier circuit a, the power amplifier circuit B, the power amplifier circuit C, and the power amplifier circuit D. taking the configuration of the power amplifier circuit a as an example, the control circuit 80 may transmit configuration parameters of an address transfer register of a device of an I2C general interface module of the power amplifier circuit a, including a clock phase control parameter of the power amplifier circuit a in the power amplifier circuit a, the device address parameter of an I2C specific interface module, and an enable switch parameter of a clock generation module, such as a clock phase control signal 3648, the power amplifier circuit B, a clock phase control circuit B, a circuit C, a clock phase control circuit B, a clock phase control circuit C, a clock phase control circuit B, a clock phase control circuit C, a clock phase control circuit B, a clock phase control circuit C, a clock phase control circuit B, a circuit C, a circuit B, a clock phase control circuit C, a circuit B, a circuit C, a clock phase control circuit C, a circuit B, a clock phase control circuit C, a circuit B, a circuit C, a circuit B, a circuit C circuit B, a circuit C circuit B, a circuit C, a circuit B, a circuit C circuit B, a circuit C circuit B, a circuit C circuit B, a.

In the audio device in the above embodiment, each clock phase control circuit outputs the first working clock signal to respectively control each corresponding power amplification circuit to start at a preset time, and then the second working clock signal respectively controls each boost conversion circuit to generate a preset phase delay, so that the output current/voltage of each boost conversion circuit generates a preset phase difference, thereby realizing peak-shifting current extraction when each power amplification circuit in the audio device works, and avoiding overheating or shutdown of a product due to battery overload.

Further, in the audio device in the above embodiment, as shown in fig. 12 to 13, the first operating clock signals output by the clock phase control circuit a, the clock phase control circuit B, the clock phase control circuit C, and the clock phase control circuit D may be configured to control the power amplification circuit a, the power amplification circuit B, the power amplification circuit C, and the power amplification circuit D to start synchronously at a preset time, and the second operating clock signals output by the clock phase control circuit a, the clock phase control circuit B, the clock phase control circuit C, and the clock phase control circuit D may be configured to control the boost converter circuit a, the boost converter circuit B, the boost converter circuit C, and the boost converter circuit D to generate a preset phase delay with the preset time as a starting point. The second operation clock signal may be set to control the phase delay angles generated by the boost converter circuit a, the boost converter circuit B, the boost converter circuit C and the boost converter circuit D with the preset time as a starting point to be 0 degree, 90 degrees, 180 degrees and 270 degrees, respectively.

In the audio device in the above embodiment, the first working clock signal output by each clock phase control circuit respectively controls the power amplification circuit a, the power amplification circuit B, the power amplification circuit C, and the power amplification circuit D to start synchronously at a preset time, and the second working clock signal output by each clock phase control circuit respectively controls the boost conversion circuit in each power amplification circuit to generate a preset phase delay with the preset time as a starting point, so as to implement accurate delay control on the clock phases of the boost conversion circuits in a plurality of different power amplification circuits, and avoid overload phenomenon caused by the same-direction switching of each boost conversion circuit.

In an embodiment of the present application, there is provided a clock phase control method applied to a clock phase control circuit, where the clock phase control circuit may be the clock phase control circuit in any embodiment of the present application, and the clock phase control circuit includes an interface module, a clock generation module, a phase control module, a first clock divider, and a second clock divider, as shown in fig. 14, and the method includes:

step 202: and controlling the interface module to generate a synchronization indication signal, a clock enable signal and a clock phase control signal based on the received clock signal and the clock phase parameter setting signal.

Step 204: and controlling the clock generation module to generate a system clock signal according to the clock enable signal.

Step 206: and controlling the phase control module to generate a set signal and a reset signal according to the clock phase control signal, the synchronous indication signal and the system clock signal.

Step 208: and controlling the first clock frequency divider to generate a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time.

Step 2010: and controlling the second clock frequency divider to generate a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit.

In the clock phase control method in the foregoing embodiment, a control interface module may receive a clock signal and a clock phase parameter setting signal, and control the interface module to generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; controlling a clock generation module to generate a system clock signal based on the received clock enable signal; the control phase control module generates a set signal and a reset signal based on the received clock phase control signal, the synchronization indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal is used for controlling a next-stage circuit to start at a preset time; and receiving the system clock signal and the setting signal by using a second clock frequency divider, and generating a second working clock signal according to the system clock signal and the setting signal, wherein the second working clock signal is used for controlling the phase delay of a next-stage circuit. The first working clock signal can control the next-stage circuit to start at a preset moment, so that a reference is provided for controlling the clock phase delay of the next-stage circuit, and the second working clock signal can control the next-stage circuit to generate a preset phase delay.

In an embodiment of the present application, there is provided a clock phase control method applied to an audio device, the audio device includes a plurality of power amplification circuits having boost converter circuits, and a plurality of clock phase control circuits as described in any of the embodiments of the present application, the number of the clock phase control circuits is the same as the number of the power amplification circuits and the number of the boost converter circuits, the clock phase control circuits are connected to the power amplification circuits in a one-to-one manner, and the clock phase control circuits are connected to the boost converter circuits of the power amplification circuits in a one-to-one manner, as shown in fig. 15, the method includes:

step 302: and respectively generating a first working clock signal and a second working clock signal by utilizing each clock phase control circuit according to the received clock signal and the clock phase parameter setting signal.

Step 304: and respectively controlling the power amplifying circuits to start at a preset moment by using the first working clock signals, and respectively controlling the boosting conversion circuits to generate a preset phase delay by using the second working clock signals.

In the clock phase control method in the above embodiment, an interface module may receive a clock signal and a clock phase parameter setting signal, and generate a synchronization indication signal, a clock enable signal, and a clock phase control signal according to the clock signal and the clock phase parameter setting signal; setting a clock generation module to receive the clock enabling signal and generate a system clock signal according to the clock enabling signal; a phase control module is arranged for receiving the clock phase control signal, the synchronous indication signal and the system clock signal, and generating a setting signal and a resetting signal according to the clock phase control signal, the synchronous indication signal and the system clock signal; receiving the system clock signal and the reset signal by using a first clock frequency divider, and generating a first working clock signal according to the system clock signal and the reset signal, wherein the first working clock signal can respectively control each power amplification circuit to start at a preset time; and a second clock frequency divider is used for receiving the system clock signal and the setting signal and generating a second working clock signal according to the system clock signal and the setting signal, and the second working clock signal can respectively control each boost conversion circuit to generate preset phase delay so as to realize delay control of the clock phase of the boost conversion circuit in a plurality of different power amplification circuits and avoid overheating or shutdown of products caused by overload of batteries due to same-direction switching of each boost conversion circuit.

Further, in a clock phase control method provided in an embodiment of the present application, as shown in fig. 16, step 304 includes:

step 3041: and respectively controlling the power amplifying circuits to synchronously start at a preset moment by using the first working clock signals, and respectively controlling the boost converting circuits to generate a preset phase delay by using the preset moment as a starting point by using the second working clock signals.

Further, in the clock phase control method in the foregoing embodiment, the controlling the boost converter circuits to generate the predetermined phase delay by using the second operating clock signals respectively includes:

respectively controlling N boosting conversion circuits to generate preset phase delay by utilizing N second working clock signals;

wherein the angle value α of the phase delay of the ith boost converter circuit_iCalculated according to the following formula:

in the above formula, i and N are positive integers, and N is the total number of the clock phase control circuits, that is, the number of the clock phase control circuits, the number of the power amplification circuits, and the number of the boost conversion circuits in the power amplification circuits are both N.

In the clock phase control method in the above embodiment, under the condition of simultaneously controlling the boost converter circuits in one or more different power amplifier circuits, a specific setting formula for the phase delay angle value of each boost converter circuit is provided, so as to more conveniently and reasonably control the phase delay angle of each boost converter circuit, and better control the next stage of circuit, such as load peak shifting current extraction, and ensure the stability of current or voltage output to the load.

For specific limitations of the clock phase control method in the above embodiments, reference may be made to the limitations of the clock phase control circuit, which are not described herein again.

It should be understood that although the various steps in the flow charts of fig. 14-16 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 14-16 may include sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.