阅读说明：本技术 一种应用于集成电路的时序控制电路及一种服务器板卡 (Time sequence control circuit applied to integrated circuit and server board card ) 是由 冯子秋 于 2020-03-06 设计创作，主要内容包括：本申请公开了一种应用于集成电路的时序控制电路,包括：N个VR,N-1个PNP型三极管以及N-2个或门,N≥3；其中,N个VR的Vin分别连接Vin电源,N个VR的Vout分别与目标集成电路的Pin相连,第i个VR的PG与第i+1个VR的EN相连,N-1个PNP型三极管的集电极均接地,N-2个或门的第一输入端均与Vin电源相连,第j个或门的第二输入端与第j+2个VR的PG相连,第j个或门的输出端与第j个PNP型三极管的基极相连,第j个PNP型三极管的发射极与第j+1个VR的Vout相连,第N-1个PNP型三极管的基极与Vin电源相连,第N-1个PNP型三极管的发射极与第N个VR的Vout相连；1≤i≤N-1,1≤j≤N-2。显然,通过此种设置方式就可以显著降低时序控制电路所占用的空间体积。(The application discloses be applied to integrated circuit's sequential control circuit includes: n VR, N-1 PNP type triodes and N-2 OR gates, wherein N is more than or equal to 3; wherein Vin of N VRs is respectively connected with a Vin power supply, Vout of N VRs is respectively connected with Pin of a target integrated circuit, PG of the ith VR is connected with EN of the (i + 1) th VR, collecting electrodes of N-1 PNP type triodes are all grounded, first input ends of N-2 OR gates are all connected with the Vin power supply, the second input end of the jth OR gate is connected with PG of the (j + 2) th VR, the output end of the jth OR gate is connected with the base electrode of the jth PNP type triode, the emitter electrode of the jth PNP type triode is connected with Vout of the (j + 1) th VR, the base electrode of the N-1 PNP type triode is connected with the Vin power supply, and the emitter electrode of the N-1 PNP type triode is connected with Vout of the N VR; i is more than or equal to 1 and less than or equal to N-1, and j is more than or equal to 1 and less than or equal to N-2. Obviously, the space volume occupied by the sequential control circuit can be obviously reduced by the arrangement mode.)

1. A timing control circuit for an integrated circuit, comprising: n VR, N-1 PNP type triodes and N-2 OR gates, wherein N is more than or equal to 3;

wherein Vin of N VRs is respectively connected with a Vin power supply, Vout of N VRs is respectively connected with Pin of a target integrated circuit, PG of the ith VR is connected with EN of the (i + 1) th VR, collectors of N-1 PNP type triodes are all grounded, first input ends of N-2 OR gates are all connected with the Vin power supply, a second input end of the jth OR gate is connected with PG of the (j + 2) th VR, an output end of the jth OR gate is connected with a base electrode of the jth PNP type triode, an emitter electrode of the jth PNP type triode is connected with Vout of the (j + 1) th VR, a base electrode of the N-1 PNP type triode is connected with the Vin power supply, and an emitter electrode of the N-1 PNP type triode is connected with Vout of the N VR; i is more than or equal to 1 and less than or equal to N-1, and j is more than or equal to 1 and less than or equal to N-2.

2. The timing control circuit of claim 1, wherein N is specifically 3.

3. The timing control circuit of claim 1, further comprising: a voltage dividing circuit;

the voltage division circuit is connected between the Vin power supply and the base electrode of the N-1 st PNP type triode.

4. The timing control circuit of claim 3, wherein the voltage divider circuit comprises: a first resistor and a second resistor;

the first end of the first resistor is connected with the Vin power supply, the second end of the first resistor is respectively connected with the first end of the second resistor and the base electrode of the (N-1) th PNP type triode, and the second end of the second resistor is connected with the collector electrode of the (N-1) th PNP type triode.

5. The timing control circuit of claim 1, wherein the OR gate comprises a first diode and a second diode;

the cathode of the first diode is connected with the cathode of the second diode;

correspondingly, the anode of the first diode is the first input end of the or gate, the anode of the second diode is the second input end of the or gate, and the cathode of the first diode and the cathode of the second diode jointly form the output end of the or gate.

6. The timing control circuit according to any one of claims 1 to 5, further comprising: the circuit comprises a delay circuit, an NPN type triode and a pull-up resistor;

the first end of the delay circuit is connected with the PG of the Nth VR, the second end of the delay circuit is connected with the base electrode of the NPN type triode, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is respectively connected with the pull-up resistor and the second input end of the N-2 th OR gate.

7. The timing control circuit of claim 6, wherein the delay circuit comprises: a third resistor and a capacitor;

the first end of the third resistor is connected with the PG of the Nth VR, the second end of the third resistor is respectively connected with the first end of the capacitor and the base electrode of the NPN type triode, and the second end of the capacitor is connected with the emitting electrode of the NPN type triode.

8. A server board card comprising the timing control circuit applied to an integrated circuit as claimed in any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of servers, in particular to a time sequence control circuit applied to an integrated circuit and a server board card.

Background

At present, people generally need to analyze and process mass data by using an integrated circuit such as a DSP (Digital Signal Processing) chip, an FPGA (Field Programmable Gate Array) chip and the like, which is specially used for Processing big data. However, the power-on and power-off timing of an integrated circuit is specified in a new generation of an integrated circuit instruction manual. Referring to fig. 1, fig. 1 is a schematic diagram illustrating power-up and power-down timing requirements of an integrated circuit.

In the prior art, in order to enable an integrated circuit to normally operate, a CP L D (complex programmable L analog Device) is generally used as a timing control circuit of the integrated circuit, that is, an EN of a VR (Voltage Regulator) is directly controlled by a CP L D to control an electrical timing of the integrated circuit, but since the CP L D has a large volume, a space occupied by the timing control circuit of the integrated circuit is large, and the integrated circuit cannot be integrated and designed on a server board with a small volume.

Therefore, it is obvious that a technical problem to be solved by those skilled in the art is how to reduce the space volume occupied by the timing control circuit so that the integrated circuit can be integrated and designed on a server board card with a small volume.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a timing control circuit applied to an integrated circuit and a server board, so as to reduce the space occupied by the timing control circuit and enable the integrated circuit to be integrated and designed on the server board with a smaller size. The specific scheme is as follows:

a timing control circuit for an integrated circuit, comprising: n VR, N-1 PNP type triodes and N-2 OR gates, wherein N is more than or equal to 3;

wherein Vin of N VRs is respectively connected with a Vin power supply, Vout of N VRs is respectively connected with Pin of a target integrated circuit, PG of the ith VR is connected with EN of the (i + 1) th VR, collectors of N-1 PNP type triodes are all grounded, first input ends of N-2 OR gates are all connected with the Vin power supply, a second input end of the jth OR gate is connected with PG of the (j + 2) th VR, an output end of the jth OR gate is connected with a base electrode of the jth PNP type triode, an emitter electrode of the jth PNP type triode is connected with Vout of the (j + 1) th VR, a base electrode of the N-1 PNP type triode is connected with the Vin power supply, and an emitter electrode of the N-1 PNP type triode is connected with Vout of the N VR; i is more than or equal to 1 and less than or equal to N-1, and j is more than or equal to 1 and less than or equal to N-2.

Preferably, N is specifically 3.

Preferably, the method further comprises the following steps: a voltage dividing circuit;

the voltage division circuit is connected between the Vin power supply and the base electrode of the N-1 st PNP type triode.

Preferably, the voltage dividing circuit includes: a first resistor and a second resistor;

the first end of the first resistor is connected with the Vin power supply, the second end of the first resistor is respectively connected with the first end of the second resistor and the base electrode of the (N-1) th PNP type triode, and the second end of the second resistor is connected with the collector electrode of the (N-1) th PNP type triode.

Preferably, the or gate includes a first diode and a second diode;

the cathode of the first diode is connected with the cathode of the second diode;

correspondingly, the anode of the first diode is the first input end of the or gate, the anode of the second diode is the second input end of the or gate, and the cathode of the first diode and the cathode of the second diode jointly form the output end of the or gate.

Preferably, the method further comprises the following steps: the circuit comprises a delay circuit, an NPN type triode and a pull-up resistor;

the first end of the delay circuit is connected with the PG of the Nth VR, the second end of the delay circuit is connected with the base electrode of the NPN type triode, the emitting electrode of the NPN type triode is grounded, and the collecting electrode of the NPN type triode is respectively connected with the pull-up resistor and the second input end of the N-2 th OR gate.

Preferably, the delay circuit includes: a third resistor and a capacitor;

the first end of the third resistor is connected with the PG of the Nth VR, the second end of the third resistor is respectively connected with the first end of the capacitor and the base electrode of the NPN type triode, and the second end of the capacitor is connected with the emitting electrode of the NPN type triode.

Correspondingly, the invention also discloses a server board card which comprises the time sequence control circuit applied to the integrated circuit.

Therefore, in the invention, when a Vin power supply is in an electrifying state, VR1 to VR N can sequentially use PG signals of VR of the previous stage to trigger EN signals of VR of the next stage, and thus the effect of sequentially electrifying VR1 to VR N can be achieved, when the Vin power supply is in a power-down state, the output voltage of the Vin power supply begins to drop, N-1 PNP type triode connected with VR N is in a conducting state, at the moment, the N-1 PNP type triode is equivalent to a conducting wire and enables VR N to be powered down, when the VR N is powered down, a low level signal output by PG of VR N and a low level signal output by the Vin power supply can be used as two input trigger signals connected with or gated by VR N-1, and the gate is triggered to control the transistor N-2 to conduct, so that the effect of powering down after VR N-1 is connected with or gated by VR N-1 can be achieved, and the effect of sequentially controlling the transistor can be achieved by using a time sequence integrated circuit board card, and the time sequence integrated circuit board can achieve the effect of sequentially reducing the CP of the CP control of the integrated circuit of the PNP integrated circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of power-up and power-down timing requirements for an integrated circuit;

FIG. 2 is a block diagram of a timing control circuit applied to an integrated circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram of another timing control circuit applied to an integrated circuit according to an embodiment of the present invention;

fig. 4 is a structural diagram of a timing control circuit diagram of an nth VR according to an embodiment of the present invention;

fig. 5 is a structural diagram of a timing control circuit diagram of the N-1 th VR according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, fig. 2 is a structural diagram of a timing control circuit applied to an integrated circuit according to an embodiment of the present invention, where the timing control circuit includes: n VR, N-1 PNP type triodes and N-2 OR gates, wherein N is more than or equal to 3;

wherein Vin of N VRs is respectively connected with a Vin power supply, Vout of N VRs is respectively connected with Pin of a target integrated circuit, PG of the ith VR is connected with EN of the (i + 1) th VR, collecting electrodes of N-1 PNP type triodes are all grounded, first input ends of N-2 OR gates are all connected with the Vin power supply, the second input end of the jth OR gate is connected with PG of the (j + 2) th VR, the output end of the jth OR gate is connected with the base electrode of the jth PNP type triode, the emitter electrode of the jth PNP type triode is connected with Vout of the (j + 1) th VR, the base electrode of the N-1 PNP type triode TVN-1 is connected with the Vin power supply, and the emitter electrode of the N-1 PNP type triode TVN-1 is connected with Vout of the N VR; i is more than or equal to 1 and less than or equal to N-1, and j is more than or equal to 1 and less than or equal to N-2.

In this embodiment, a timing control circuit applied to an integrated circuit is provided, through which the space volume occupied by the timing control circuit can be significantly reduced, and the integrated circuit can be integrated and designed on a server board card with a small volume. In this embodiment, the target integrated circuit may be an FPGA or an integrated circuit such as a DSP for processing mass data.

Specifically referring to fig. 2, when the Vin power source is in a power-on state, the PG signal of the 1 st VR triggers the EN port of the 2 nd VR, thereby achieving the effect that the 2 nd VR is powered on after the 1 st VR. It is contemplated that after the 2 nd VR is powered up, the PG signal of the 2 nd VR will trigger the EN port of the 3 rd VR and cause the 3 rd VR to be powered up after the 2 nd VR. By analogy, when the N-1 VR is in the power-up state, the PG signal of the N-1 VR triggers the EN port of the N VR, and thus the N VR is powered up later than the N-1 VR. Obviously, the timing control circuit provided in this embodiment can enable the EN port of the next stage VR by using the PG port of the previous stage VR, so that the effect of sequentially powering on the 1 st VR to the nth VR can be achieved.

When the Vin power supply is in a power-off state, the output voltage of the Vin power supply begins to drop, the N-1 st PNP type triode connected with the N VRs is in a conducting state, at the moment, the N-1 st PNP type triode is equivalent to a conducting wire, and the N VR is powered down firstly; when the power failure of the Nth VR is finished, at the moment, the PG port of the Nth VR outputs a low-level signal, the Vin power supply also outputs a low-level signal, and the two low-level signals trigger the logic unit or gate connected with the (N-1) th VR. It can be thought that when the two input ends of the or gate connected to the N-1 th VR are both low level signals, the output signal of the or gate triggers the N-1 th PNP triode to conduct, so that the effect of powering down the N-1 th VR compared with the N-1 th VR can be achieved. Similarly, when the power failure of the (N-1) th VR is finished, at the moment, the PG port of the (N-1) th VR outputs a low level signal, the Vin power supply also outputs a low level signal, and the two low level signals trigger the logic unit or gate connected with the (N-2) th VR. Obviously, when two input ends of an or gate connected with the N-2 VRs are low level signals, an output signal of the or gate triggers the N-2 PNP type triode to be conducted, and therefore the effect that the N-2 VRs are powered down compared with the N-1 VR can be achieved. By analogy, the effect that the power is turned off from the Nth VR to the 1 st VR in sequence can be realized.

Obviously, compared with the prior art that the up-down power sequence of the integrated circuit can be controlled by using the CP L D with a large volume, the time sequence control circuit provided by the invention can achieve the purpose of controlling the up-down power sequence of the integrated circuit only by using the PNP type triode with a small volume and the logic unit or gate, so that the space volume required by the time sequence control circuit of the integrated circuit can be significantly reduced by the arrangement mode.

It can be seen that, in this embodiment, when a Vin power supply is in a powered-up state, VR1 to VR N may sequentially use a PG signal of a VR of a previous stage to trigger an EN signal of a VR of a next stage, and thus, an effect of sequentially powering up VR1 to VR N may be achieved, when the Vin power supply is in a powered-down state, an output voltage of the Vin power supply starts to decrease, an N-1 PNP transistor connected to VR N is in a conducting state, at this time, the N-1 PNP transistor is equivalent to a conducting wire, and the VR N is powered down first, and when the VR N is powered down, a low level signal output by PG of VR N and a low level signal output by the Vin power supply may serve as two input trigger signals connected to or gated by VR N-1 VR, and thus trigger or gate to gate the N-2 PNP transistor to conduct, so that a power down effect of VR N-1 compared to VR N may be achieved by analogy, and a timing control circuit integrated circuit board may be designed to have a smaller up and down time sequence, and thus, a time sequence integrated circuit board may be able to achieve a more effective control a time sequence control that a CP is capable of reducing CP by using a CP, and a time sequence integrated circuit.

Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, N is specifically 3.

In practical applications, it is often seen that the integrated circuit needs three stages of power supply timing, so in this embodiment, a timing control circuit of the integrated circuit is provided, which can provide three stages of power supply timing. Referring to fig. 3, fig. 3 is a structural diagram of another timing control circuit applied to an integrated circuit according to an embodiment of the present invention, in the timing control circuit of the integrated circuit, 3 VRs, 2 PNP triodes, and 1 or gate are provided, that is, the timing control circuit can provide a three-stage power supply timing.

Specifically, when the Vin power supply is powered on, the PG port of VR1 triggers the EN port of VR2, and allows VR1 to be powered on before VR2, and when VR2 is powered on, the PG port of VR2 triggers the EN port of VR3, and allows VR2 to be powered on before VR 3.

When the Vin power supply is in a power-off state, the output voltage of the Vin power supply begins to drop, and when the output voltage of the Vin power supply drops to a certain value, the PNP type triode VT2 is in a conducting state, under the condition, the PNP type triode VT2 is equivalent to a conducting wire and can carry out short-circuit discharge, and therefore the VR3 can be powered off in advance. Then, the Or gate Or will use the power-down logic of VR3 and the power-down state of Vin power supply as two input trigger signals of the Or gate, when the two input trigger signals of the Or gate Or are both low level, the output signal of the Or gate will trigger the PNP transistor VT1 to conduct, so as to power down VR2, because the VR1 requires the final power-down, there is no need to add any discharge structure in VR 1.

Obviously, the technical scheme provided by the embodiment can not only realize the three-level power supply timing requirement of the integrated circuit, but also make the timing control circuit more universal in practical application.

Based on the foregoing embodiment, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the timing control circuit further includes: a voltage dividing circuit;

the voltage division circuit is connected between the Vin power supply and the base electrode of the N-1 PNP type triode.

Referring to fig. 4, fig. 4 is a structural diagram of a timing control circuit diagram of an nth VR according to an embodiment of the present invention. In this embodiment, in order to control the power-down time of the nth VR, a voltage divider circuit is further disposed between the Vin power source and the base of the N-1 st PNP transistor TVN-1. It is conceivable that when the voltage divider circuit is disposed between the Vin power supply and the base of the N-1 st PNP transistor, the voltage divider circuit can be used to control when the N-1 st PNP transistor TVN-1 is turned on.

Obviously, the technical scheme provided by the embodiment can further improve the flexibility of people when using the sequential control circuit.

As a preferred embodiment, the voltage dividing circuit includes: a first resistor R1 and a second resistor R2;

the first end of the first resistor R1 is connected with the Vin power supply, the second end of the first resistor R1 is respectively connected with the first end of the second resistor R2 and the base electrode of the N-1 th PNP type triode TVN-1, and the second end of the second resistor R2 is connected with the collector electrode of the N-1 th PNP type triode TVN-1.

Referring to fig. 4, in the present embodiment, the voltage divider circuit is configured as a first resistor R1 and a second resistor R2. It is conceivable that, when the voltage dividing circuit is provided in this form, not only the structure of the voltage dividing circuit can be made simpler, but also the cost required for the voltage dividing circuit can be reduced.

Certainly, in practical applications, the voltage divider circuit may be disposed at other positions of the timing control circuit according to needs of actual situations, so that a worker may control the power-down time of any VR, and since the operation is well known by those skilled in the art, detailed description is omitted here.

Based on the above embodiments, this embodiment further describes and optimizes the technical solution, as a preferred implementation, the or gate includes a first diode and a second diode;

the cathode of the first diode is connected with the cathode of the second diode;

correspondingly, the anode of the first diode is the first input end of the OR gate, the anode of the second diode is the second input end of the OR gate, and the cathode of the first diode and the cathode of the second diode jointly form the output end of the OR gate.

In this embodiment, a specific arrangement of the or gate is provided, that is, two diodes are used to form a logic unit or gate. Obviously, because the diode is not only common in daily life, but also relatively low in design cost, when the or gate is configured in such a structure, the complexity in building the or gate can be relatively reduced.

Referring to fig. 5, fig. 5 is a structural diagram of a timing control circuit diagram of the N-1 th VR according to an embodiment of the present invention, in the timing control circuit, an or gate connected to an N-2 th PNP transistor TVN-2 is set to a structural form of D1+ D2, that is, two diodes are used to form one or gate.

Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, please refer to fig. 5, and fig. 5 is a structural diagram of a timing control circuit diagram of the N-1 th VR provided in the embodiment of the present invention. As a preferred embodiment, the timing control circuit further includes: the circuit comprises a delay circuit, an NPN type triode and a pull-up resistor;

the first end of the delay circuit is connected with PG of the Nth VR, the second end of the delay circuit is connected with the base electrode of the NPN type triode TV, the emitting electrode of the NPN type triode TV is grounded, and the collecting electrode of the NPN type triode TV is respectively connected with the pull-up resistor and the second input end of the N-2 th OR gate.

In the embodiment, in order to further improve the user experience when people use the timing control circuit, a delay circuit for adjusting the N-1 th VR to delay power-down is further arranged in the timing control circuit. Referring to fig. 5, fig. 5 is a block diagram of a timing control circuit diagram of an N-1 th VR according to an embodiment of the present invention, in which a delay circuit is used to adjust a power-down delay time of the N-1 th VR. Of course, in practical applications, the delay circuit may be disposed at other positions of the timing control circuit, so that the worker can control the power-off delay time of any VR.

Obviously, through the technical scheme provided by the embodiment, the functions of the sequential control circuit can be more flexible and diversified.

As a preferred embodiment, the delay circuit includes: a third resistor R3 and a capacitor C;

a first end of the third resistor R3 is connected to PG of the nth VR, a second end of the third resistor R3 is connected to a first end of the capacitor C and a base of the NPN transistor TV, respectively, and a second end of the capacitor C is connected to an emitter of the NPN transistor TV.

Referring to fig. 5, in the present embodiment, the delay circuit is configured as a third resistor R3 plus a capacitor C, that is, the delay circuit is configured as an RC circuit. Obviously, because the RC circuit is not only common in real life, but also has the advantages of simple connection structure and easy implementation, when the delay circuit is configured as such, the usability of the delay circuit in the using process can be relatively improved.

Correspondingly, the embodiment of the invention also discloses a server board card which comprises the sequential control circuit applied to the integrated circuit.

The server board card provided by the embodiment of the invention has the beneficial effects of the time sequence control circuit applied to the integrated circuit disclosed in the specification.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The timing control circuit applied to the integrated circuit and the server board card provided by the invention are described in detail, a specific example is applied in the description to explain the principle and the implementation of the invention, and the description of the above embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.