阅读说明：本技术 集成电路布局以及具有双重图案的方法 (Integrated circuit layout and method with double patterns ) 是由 谢铭峰 刘如淦 谢弘璋 高蔡胜 辜耀进 于 2013-11-22 设计创作，主要内容包括：本发明提供了用于集成电路(IC)的方法的一个实施例。该方法包括通过第一光刻工艺在衬底上形成心轴图案；在心轴图案的侧壁上形成第一间隔件图案；去除心轴图案；在第一间隔件图案的侧壁上形成第二间隔件图案；去除第一间隔件图案；以及将第二间隔件图案用作蚀刻掩模来蚀刻衬底。本发明还公开了集成电路布局以及具有双重图案结构的方法。(One embodiment of a method for an Integrated Circuit (IC) is provided. The method includes forming a mandrel pattern on a substrate through a first photolithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask. The invention also discloses an integrated circuit layout and a method with a double-pattern structure.)

1. A method for an Integrated Circuit (IC), comprising:

forming a mandrel pattern on a substrate through a first photolithography process;

forming a first spacer pattern on sidewalls of the mandrel pattern;

removing the mandrel pattern;

forming a plurality of second spacer patterns on sidewalls of the first spacer patterns;

removing the first spacer pattern;

forming an irregular cut pattern on the second spacer patterns through a second photolithography process, the cut pattern having a plurality of openings, the cut pattern covering a first set of the second spacer patterns of the plurality of second spacer patterns, the plurality of openings exposing a portion of a second set of the second spacer patterns of the plurality of second spacer patterns;

removing the portion of the second set of second spacer patterns within the plurality of openings and leaving second spacer patterns of the second set of second spacer patterns and the first set of second spacer patterns having different pitches; and

etching the substrate using the remaining another portion of the second set of second spacer patterns and the first set of second spacer patterns as an etch mask to form a first set of island features and a second set of island features having different pitches.

2. The method of claim 1, wherein etching the substrate comprises: a trench pattern is formed in the substrate, and the trench pattern includes the first set of island features and the second set of island features.

3. The method of claim 2, wherein:

the mandrel pattern comprises a plurality of first features having a first width L and spaced apart at a first spacing S;

the first spacer pattern comprises a plurality of second features, each of the second features having a second width b;

the second spacer pattern includes a plurality of third features, each of the third features having a third width c; and

the pitch of the first and second sets of islands is jointly determined by the parameters L, S, b and c.

4. The method of claim 3, wherein the first set of islands has a first pitch P1, the second set of islands has a second pitch P2, the first pitch P1 and the second pitch P2 being different from each other.

5. The method of claim 4, wherein:

p1 is equal to the sum of b and c; and

p2 equals L-c.

6. The method of claim 5, wherein L and c are determined according to P2 ═ L-c, and

b is determined from P1 ═ b + c.

7. The method of claim 6, further comprising determining S from S-L-2 c.

8. The method of claim 6, wherein the island further comprises a third pitch P3, and the first spacing S is determined according to S-P3-c.

9. A method for an Integrated Circuit (IC), comprising:

receiving an integrated circuit layout having a plurality of components;

determining a variable and aperiodic pitch in the plurality of components;

determining mask parameters and process parameters related to a mandrel pattern and an irregular cut pattern based on the variable and aperiodic pitch in the component, wherein the irregular cut pattern has a plurality of openings of different widths; and

manufacturing a mask according to the mask parameters, wherein the manufacturing the mask comprises:

forming a mandrel pattern, forming a first spacer pattern on sidewalls of the mandrel pattern;

removing the mandrel pattern, and forming a plurality of second spacer patterns on sidewalls of the first spacer patterns;

forming the irregular cut pattern on the second spacer pattern, the cut pattern having a plurality of openings, the cut pattern covering a first set of second spacer patterns of the plurality of second spacer patterns, the openings exposing a portion of a second set of second spacer patterns of the plurality of second spacer patterns;

removing the portion of the second set of second spacer patterns within the plurality of openings of the cut pattern and leaving second spacer patterns of the second set of second spacer patterns and the first set of second spacer patterns having different pitches;

wherein determining a variable and aperiodic pitch in the plurality of components comprises: the substrate is etched using the mask to form a first set of islands and a second set of islands having different pitches.

10. A method for an Integrated Circuit (IC), comprising:

receiving an integrated circuit layout having a plurality of components, forming a mandrel pattern on the wafer according to the integrated circuit layout;

depositing a first layer of spacer material having a first thickness b;

performing a first anisotropic etch to form a first spacer pattern on sidewalls of the mandrel pattern;

removing the mandrel pattern;

depositing a second spacer material layer having a second thickness c;

performing a second anisotropic etch to form a second spacer pattern composed of a plurality of third features on sidewalls of the first spacer pattern;

removing the first spacer pattern;

forming an irregular cut pattern on the second spacer pattern, the cut pattern having a plurality of openings, the cut pattern covering a first set of second spacer patterns of the plurality of second spacer patterns, the plurality of openings exposing a portion of a second set of second spacer patterns of the plurality of second spacer patterns;

removing the portion of the second group of second spacer patterns within the plurality of openings, and remaining second spacer patterns of the second group of second spacer patterns and the first group of second spacer patterns having first and second pitches P1 and P2, respectively, which are different from each other and are non-periodic; and

etching the wafer using the remaining another portion of the second set of second spacer patterns and the first set of second spacer patterns as an etch mask to form a first set of island features and a second set of island features having the first pitch P1 and the second pitch P2;

wherein the plurality of components have a first pitch P1 and a second pitch P2 that are different from each other and aperiodic;

determining a first process parameter c from P2-L-c, wherein L is a first width of the part, and

the second process parameter b is determined from P1 ═ b + c.

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to integrated circuit layouts and methods having dual pattern structures.

Background

Semiconductor technology is continually evolving to smaller feature sizes, e.g., down to 28 nanometers, 20 nanometers, and lower feature sizes. Various Integrated Circuit (IC) components having small component sizes are formed on a semiconductor wafer by various techniques. For example, a double pattern is used to form a plurality of features with a small pitch. However, there is no effective method for fabricating irregular patterns by double patterning.

Therefore, there is a need for a method and photomask structure to provide efficient IC design and fabrication of advanced IC technologies that address the above-mentioned problems.

Disclosure of Invention

To solve the problems in the prior art, according to an aspect of the present invention, there is provided a method for an Integrated Circuit (IC), including:

forming a mandrel pattern on a substrate through a first photolithography process;

forming a first spacer pattern on sidewalls of the mandrel pattern;

removing the mandrel pattern;

forming a second spacer pattern on sidewalls of the first spacer pattern;

removing the first spacer pattern; and

etching the substrate using the second spacer pattern as an etch mask.

In an alternative embodiment, the method further comprises: forming a cutting pattern on the second spacer pattern through a second photolithography process; and removing a portion of the second spacer pattern within the opening of the cutting pattern before etching the substrate.

In an alternative embodiment, etching the substrate comprises: a trench pattern is formed in the substrate, and the trench pattern includes a plurality of island-like features having a variable pitch.

In an alternative embodiment, the mandrel pattern includes a plurality of first features having a first width L and spaced apart at a first spacing S, the first spacer pattern includes a plurality of second features each having a second width b, the second spacer pattern includes a plurality of third features each having a third width c, and the variable pitch is collectively determined by parameters L, S, b, and c.

In an alternative embodiment, the plurality of island features in the trench pattern include a first pitch P1 and a second pitch P2 that are different from each other.

In an alternative embodiment, P1 equals the sum of b and c, and P2 equals L-c.

In an alternative embodiment, the variable pitch collectively determined by parameters L, S, b, and c includes determining L and c from P2-L-c and b from P1-b + c.

In an alternative embodiment, the method further comprises determining S from S L-2 c.

In an alternative embodiment, the island further comprises a third pitch P3, and the first spacing S is determined according to S-P3-c.

In an alternative embodiment, the forming of the mandrel pattern includes depositing a layer of mandrel material on the substrate, and patterning the layer of mandrel material by a process further including coating a photoresist layer on the layer of mandrel material, performing an exposure process on the photoresist layer using a mask defining the mandrel pattern having the first pitch S and the first width L, developing the photoresist layer to form a photoresist pattern having openings, and etching the layer of mandrel material through the openings of the photoresist pattern to form the mandrel pattern.

In an alternative embodiment, forming the first spacer pattern on the sidewalls of the mandrel pattern comprises: depositing a first layer of spacer material having a first thickness equal to b over the substrate and the mandrel pattern; and performing a first anisotropic etch on the first spacer material layer, thereby forming the first spacer pattern.

In an alternative embodiment, forming the second spacer pattern on the sidewalls of the first spacer pattern includes: depositing a second spacer material layer having a second thickness equal to c on the substrate and the first spacer pattern; and performing a second anisotropic etch on the second spacer material layer, thereby forming the second spacer pattern.

In an alternative embodiment, the first features in the mandrel pattern comprise a first spacing S1 and a second spacing S2 that is greater than S1; and determining the second width b to be less than S2/2 and at least equal to S1/2, thereby causing adjacent two of the second components having the first pitch to merge together.

In an alternative embodiment, removing the portion of the second spacer pattern within the opening of the cutting pattern includes removing two adjacent second features.

There is also provided, in accordance with another embodiment of the present invention, a method for an Integrated Circuit (IC), including:

receiving an IC layout having a plurality of components;

determining a pitch in the plurality of components;

determining mask parameters and process parameters based on the pitch in the feature; and

a mask is fabricated according to the mask parameters.

In an alternative embodiment, the method further comprises: a wafer is manufactured according to the process parameters and using the mask.

In an alternative embodiment, the mask parameters include a width L and a spacing S defined in the feature, and the process parameters include a first thickness b of a first layer of spacer material to be deposited on the wafer and a second thickness c of a second layer of spacer material to be deposited on the wafer.

In an alternative embodiment, the fabrication of the wafer comprises: depositing the first layer of spacer material having the first thickness b; and performing a first anisotropic etch on the first spacer material layer to form a first spacer pattern.

In an alternative embodiment, the fabrication of the wafer comprises: depositing the second spacer material layer having the second thickness c; and performing a second anisotropic etch on the second spacer material layer to form a second spacer pattern.

According to yet another aspect of the present invention, there is also provided a method for an Integrated Circuit (IC), comprising:

receiving an IC layout having a plurality of components with first and second pitches P1, P2 that are different from one another;

determining a first process parameter c from P2-L-c, wherein L is a first width of the part, and

the second process parameter b is determined from P1 ═ b + c.

In an alternative embodiment, the method further comprises: fabricating a wafer, the fabricating of the wafer further comprising: forming a mandrel pattern on the wafer according to the IC layout; depositing a first layer of spacer material having a first thickness b; performing a first anisotropic etch to form a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; depositing a second spacer material layer having a second thickness c; performing a second anisotropic etch to form a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the wafer using the second spacer pattern as an etch mask.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, the various features of the drawings are not necessarily drawn to scale. In fact, the dimensions of the elements shown may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow diagram of an embodiment of a method of an Integrated Circuit (IC) constructed in accordance with aspects of the invention.

Fig. 2-10 are cross-sectional views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

Figure 11 is a cross-sectional view of a semiconductor structure constructed in accordance with aspects of the invention in one or more embodiments.

FIG. 12 is a flow diagram of an embodiment of an IC method constructed in accordance with aspects of the invention.

Figure 13 is a cross-sectional view of a semiconductor structure constructed in accordance with aspects of the invention in one or more other embodiments.

Fig. 14-17 are top views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

Fig. 18-22 are top views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

Fig. 23-29 are top views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

Fig. 30-36 are top views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

Figures 37-38 are top views of semiconductor structures constructed in accordance with aspects of the invention and at various stages of fabrication in one or more embodiments.

FIG. 39 is a flow diagram of another embodiment of an IC method constructed in accordance with aspects of the invention.

FIG. 40 is a flow diagram of another embodiment of an IC method constructed in accordance with aspects of the invention.

Fig. 41 is a top view of a cutting pattern constructed in accordance with aspects of the invention in one or more embodiments.

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. They are, of course, merely illustrative and are not intended to be limiting. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 1 is a flow diagram of a method 20 for fabricating an Integrated Circuit (IC) constructed in accordance with various aspects of the invention in one or more embodiments. Fig. 2-10 are cross-sectional views of semiconductor structure 100 at various stages of fabrication. Semiconductor structure 100 is one example of a semiconductor structure manufactured by method 20. The method 20 and the semiconductor structure 100 are collectively described with reference to fig. 1-10.

The method 20 begins at operation 22 by forming a hard mask pattern 104 on the substrate 102. The hard mask pattern 104 is a dummy pattern and will be removed at a subsequent manufacturing stage. The hard mask pattern 104 is also referred to as a mandrel pattern 104. The substrate 102 includes a semiconductor substrate such as a silicon wafer. Optionally, substrate 102 comprises germanium, silicon germanium, or other suitable semiconductor material. The substrate 102 may also include a plurality of doped regions such as n-type and p-type wells. In one embodiment, the substrate 102 includes an epitaxial (or epi) semiconductor layer. In another embodiment, the substrate 102 includes a buried dielectric material layer for isolation formed by a suitable technique, such as a technique known as separation by implantation of oxygen (SIMOX). In some embodiments, the substrate 102 may be a semiconductor-on-insulator such as a silicon-on-insulator (SOI).

In operation 22, the designer receives or provides an IC layout (or IC design pattern). In one example, the designer may be a design company or a design team separate from the semiconductor manufacturers assigned to manufacture the IC products according to the IC layout. In various embodiments, a semiconductor manufacturer is able to manufacture a photomask (mask), a semiconductor wafer, or both. The IC layout includes a plurality of geometric patterns designed for the IC product and based on specifications of the IC product. For example, an IC layout includes a pattern defining a fin active area structure, wherein a plurality of IC devices, such as fin field effect transistors (finfets), are formed on the fin active area structure. In one embodiment, the IC pattern is defined in a photomask (mask).

In the present embodiment, the mandrel pattern 104 defines a plurality of openings such that the substrate 102 is exposed within the openings. In one embodiment, the formation of the mandrel pattern 104 includes depositing a layer of mandrel material such as a dielectric material (e.g., silicon oxide, silicon nitride); forming a photoresist pattern; and etching the mandrel material layer using the photoresist layer as an etch mask to form a mandrel pattern 104. The photoresist pattern comprises a photoresist material that is sensitive to the radiation beam and is formed by a photolithography process. In one example, the photolithography process includes coating a photoresist layer on the mandrel material layer, performing a photolithography exposure process on the photoresist layer according to the IC layout, and developing the exposed photoresist layer to form a photoresist pattern. The lithographic exposure process uses a radiation beam, such as light (such as ultraviolet-UV, deep ultraviolet-DUV, or extreme ultraviolet-EUV), to chemically alter the exposed portions of the photoresist layer. In this embodiment, the photolithographic exposure process utilizes a mask having an IC layout defined thereon. The mask may be a binary mask, a Phase Shift Mask (PSM) or a reflective mask (such as a reflective mask for an EUV lithographic exposure process).

The mandrel pattern 104 includes a plurality of first features oriented in the Y direction and spaced apart in the X direction perpendicular to the Y direction, examples of the first features are also referred to as 104, or specifically as 104A, 104B, and 104C, respectively as shown in FIG. 2, the first features 104 have a first width L and a first spacing S. in particular, the first width L may be constant or alternatively variable from feature to feature.

The method 20 proceeds to operation 24, where a first spacer pattern 106 is formed on sidewalls of the mandrel pattern 104, as shown in fig. 3. In one embodiment, the formation of the first spacer pattern 106 includes depositing a first layer of spacer material on the substrate 102 and the mandrel pattern 104, and then performing a first anisotropic etch on the first layer of spacer material, thereby forming the first spacer pattern 106. The first layer of spacer material may comprise a dielectric material such as silicon oxide, silicon nitride, or silicon carbide but different from the layer of mandrel material to obtain etch selectivity during the first anisotropic etch. The deposition of the first spacer material layer comprises a suitable technique such as Chemical Vapor Deposition (CVD). The thickness of the first spacer material layer is referred to as a first process parameter "b". In one example, the first anisotropic etch can comprise a plasma etch. The first spacer pattern 106 includes a plurality of second features oriented in the Y-direction and spaced apart from each other in the X-direction.

The method 20 proceeds to operation 26 where the mandrel pattern 104 is removed, as shown in FIG. 4. The mandrel pattern 104 is removed by an etching process that selectively removes the layer of mandrel material but does not substantially etch the first layer of spacer material. As shown in fig. 4, the second features in the first spacer pattern 106 have a second width that is substantially equal to the deposited thickness "b" of the first spacer material layer.

The method 20 proceeds to operation 28 where a second spacer pattern 108 is formed on sidewalls of the first spacer pattern 106, as shown in fig. 5. In one embodiment, the forming of the second spacer pattern 108 includes depositing a second spacer material layer on the substrate 102 and the first spacer pattern 106, and then performing a second anisotropic etch on the second spacer material layer, thereby forming the second spacer pattern 108. The second spacer material layer may comprise a dielectric material such as silicon oxide, silicon nitride or silicon carbide but different from the first spacer material layer to obtain an etch selectivity during the second anisotropic etch. The deposition of the second spacer material layer comprises a suitable technique such as CVD. The thickness of the second spacer material layer is referred to as a second process parameter "c". In one example, the second anisotropic etch can comprise a plasma etch. The second spacer pattern 108 includes a plurality of third features oriented in the Y-direction and spaced apart from each other in the X-direction.

The method 20 proceeds to operation 30 where the first spacer pattern 106 is removed, as shown in fig. 6. The first spacer pattern 106 is removed by an etching process that selectively removes the first spacer material layer but does not substantially etch the second spacer material layer. As shown in fig. 6, the third features in the second spacer pattern 108 have a third width that is substantially equal to the deposition thickness "c" of the second spacer material layer.

The method 20 proceeds to operation 32 where the cutting pattern 110 having the openings 112 is formed such that a subset of the third features within the openings 112 are uncovered, as shown in fig. 7. The cutting pattern 110 is used as an etch mask during a subsequent etching process to remove a subset of the third features in the second spacer pattern 108. The cutting pattern 110 may include a photoresist layer patterned by a second photolithography process. The second lithographic process may utilize a suitable lithographic technique such as immersion lithography. Alternatively, the cutting pattern 110 includes a hard mask material (a dielectric material such as silicon oxide or silicon nitride) different from the second spacer material layer to obtain etching selectivity, and is patterned through processes including depositing the dielectric material layer, forming a photoresist pattern on the dielectric material layer, and etching the dielectric material layer using the photoresist pattern as an etching mask. The cutting pattern 110 and the plurality of openings 112 defined thereon are further illustrated in a top view in fig. 41.

The method 20 proceeds to operation 34 where a subset of the third features in the second spacer pattern 108 are removed, as shown in fig. 8. The subset of third features in the second spacer pattern 108 is removed by an etching process that selectively removes the second spacer material layer but does not substantially etch the cut pattern 110. As shown in fig. 9, thereafter, the cutting pattern 110 is removed by a suitable process. In one example in which the cutting pattern 110 is a photoresist pattern, the cutting pattern 110 is removed by wet stripping or plasma ashing. In another example where the cutting pattern 110 is a hard mask pattern of a dielectric material, the cutting pattern 110 may be removed by a wet etching process to selectively remove the hard mask material. The second spacer pattern is still labeled 108 but is reduced due to the removal of a subset of the third features.

The method 20 proceeds to operation 36 where the substrate 102 is etched using the second spacer pattern 108 as an etch mask to form a plurality of trenches 114 in the substrate 102, referring to fig. 10. The etch process applied to the substrate 102 is designed to selectively etch the substrate 102, such as selectively etching silicon. The etching process may include dry etching and/or wet etching and may include multiple etching steps to optimize the etching effect. For example, the etching process includes dry etching to substantially remove the majority and wet etching to further remove the remainder. In one embodiment, one or more hard mask layers are disposed on the substrate 102. In this case, the second spacer pattern 108 is used to pattern the hard mask layer. Thereafter, the substrate 102 is patterned to form trenches 114 through the patterned hard mask layer.

Alternatively, the second spacer pattern 108 serves as an ion implantation mask. An ion implantation process is applied to the substrate to form various doped features in the substrate 102 through the openings of the second spacer pattern 108. The third features in the second spacer pattern 108 prevent ion implantation from introducing dopants into the substrate in the regions protected by the third features.

Thereafter, the second spacer pattern 108 is removed by a suitable etching process such as wet etching. The method 20 may include other operations before, during, or after the operations 22-26. For example, method 20 includes an operation 38 of forming an IC pattern in substrate 102. In the present embodiment, the second spacer pattern 108 defines fin-shaped active regions for finfets. In this case, operation 38 forms fin-shaped active regions in substrate 102.

In one embodiment, operation 38 includes forming Shallow Trench Isolation (STI) features and notching the STI features to form fin-shaped active areas. The formation of STI features may implement a process that includes the steps of: depositing one or more dielectric materials to fill the trench; and performing a polishing process, such as Chemical Mechanical Polishing (CMP), to remove excess dielectric material on the substrate and planarize the top surface. The trenching of the STI features may include an etching process to selectively etch the STI features such that the STI features are trenched below the top surface of the substrate 102.

In another embodiment, operation 38 includes forming STI features and selectively epitaxially growing semiconductor material on the substrate 102 to form fin-shaped active regions. The semiconductor material selectively epitaxially grown on the substrate 102 may be the same as or alternatively different from the semiconductor material of the substrate. For example, the substrate 102 comprises silicon, and the semiconductor material selectively epitaxially grown thereon comprises germanium (Ge), silicon germanium (SiGe), or other semiconductor materials that differ in composition from silicon, such as III-V semiconductor materials. In another example, the substrate 102 comprises germanium or silicon germanium, and the semiconductor material selectively epitaxially grown thereon comprises silicon or other semiconductor material that differs in composition.

The disclosed method 20 forms a second spacer pattern 108 (shown in fig. 6 or 9) having a different structure, particularly, the second spacer pattern 108 may include an irregular pattern, e.g., the second spacer pattern has a non-periodic structure, particularly, in the irregular pattern, a third feature in the second spacer pattern 108 has a variable pitch that varies between the third features, hi the method 200, two sets of parameters are introduced and defined, the first set including L and S, referred to as mask parameters, and the second set including b and c, referred to as process parameters, associated with masks used in the lithographic process of the method 20, the mask parameters may also include other parameters associated with the cut pattern 110, the process parameters are associated with various process operations, such as deposition to form the first and second spacer material layers, respectively, the method 20 further includes the step of selecting various combinations of the mask parameters and the process parameters to form different IC patterns, particularly, the irregular IC patterns, as further described below in accordance with various embodiments.

Fig. 11 shows a cross-sectional view of semiconductor structure 100, but a number of features are present for better understanding purposes only, and the structure in fig. 11 is referred to as semiconductor structure 116, although in reality those features will not be present at the same stage of fabrication. It is understood that the structure 116 is for illustration purposes only. Fig. 13 illustrates a cross-sectional view of a semiconductor structure 134 according to another embodiment. Structure 134 is similar to structure 116 in that multiple components are present for better understanding purposes only, although in reality those components would not be present at the same stage of manufacture. The structure 134 also includes a cutting pattern having one or more cutting openings 112. The various parameters are labeled in fig. 11 and 13 for the following description. Fig. 12 is a flow diagram of a method 120 for fabricating IC patterns constructed in accordance with aspects of the invention, in various embodiments. The method 120 is used to determine a plurality of parameters and is combined with the method 20 to form IC patterns having various structures, particularly various irregular structures. For example, method 120 is performed to determine mask and process parameters; and method 20 is performed to form an IC pattern according to the parameters determined by method 120. The method 120 is described with reference to fig. 11-13 and with further reference to other figures.

The method 120 begins at operation 122 with receiving an IC layout having a plurality of third features, such as the second spacer pattern 108 of fig. 9 that may define a plurality of fin active regions in the substrate 102.

The method 120 may proceed to operation 124 where some pitch in the third feature (also referred to as 108) is determined. The third members are oriented in the Y direction and spaced apart from each other in the X direction. In one embodiment, the third members 108 are arranged in a periodic structure having a pitch P1 in the X direction. A pitch is defined as the dimension from an edge of one feature in the second spacer pattern to the same edge of an adjacent feature in the second spacer pattern. In another embodiment, the third components 108 are configured in the X direction with a non-periodic structure (irregular structure) having two pitches P1 and P2 or alternatively a plurality of pitches such as P1, P2, and P3. In the irregular configuration, a first subset of the third features has one pitch (such as P1) and a second subset of the third features has another pitch (such as P2), and so on.

The method 120 proceeds to operation 126 where a respective value for each pitch in the third component 108 is determined. Those values can be extracted directly from the IC layout. For example, P1 is 82nm and P2 is 94 nm.

The method 120 proceeds to operation 128 where the various mask parameters and process parameters are determined based on the IC layout, particularly based on the respective values of the pitches the mask parameters include L and S. process parameters defined in the mask to form the mandrel pattern 104 in the first lithographic process of method 20 include b and c. those parameters are labeled in fig. 11 for method 20 to deposit the first and second spacer material layers, respectively, then the method of determining those parameters is further described according to various examples in one example, where the first pitch P1 b + c, the second pitch P2 b 7-c, and the third pitch P3S-2 b-c, as shown in fig. 11, where the third feature of the second spacer pattern 108 within the gap between two adjacent first features of the mandrel pattern 104 is removed by etching through the openings 112 of the cut pattern 110, the third pitch P35 3S + c, based on those equations, the parameters may be determined based on P1, P2, P36S, b, P L, P364934 c.

In one case, there may be more freedom in determining the parameters. In this case, the parameters may be further adjusted based on other considerations such as mask inspection rules and manufacturing capabilities.

In other cases, there may not be enough freedom to select the appropriate parameters. For example, in the case of four or more pitches, the cutting pattern 110 is properly designed to obtain an irregular pattern during the second photolithography process in the method 20, thereby forming the cutting pattern 110. As shown in fig. 13, the cutting pattern includes one or more openings 112 defining a plurality of third features to be removed. For this purpose, the cutting patterns may be designed to have different widths, pitches, one or more pitches. Additionally or alternatively, the process parameters b and/or c may be designed to cause merging to obtain an irregular pattern with multiple pitches. The cutting pattern may be designed to remove the merged features.

In another example where the number of pitches is 2, the irregular pattern may be formed by requiring P1 ═ P2, P2 ═ P3, or P1 ═ P3. In yet another example where the number of pitches is 1, the irregular pattern may be formed by requiring P1-P2-P3.

In another example, the second elements in the first spacer pattern 106 are merged by adjusting L and S such that S < ═ 2b and | L-S | ═ 2c, and a periodic (regular) pattern with pitch P1 ═ L + S)/2 is obtained, hi one particular example, b ═ 24, c ═ 12, S ═ 48, and L ═ 72, so P1 ═ 60.

In another example, by adjusting L and S so that S < ═ 2b +2c and setting "D" to the dummy features to be removed during operations 32 and 34 of method 20 (as shown in fig. 13), an aperiodic (irregular) pattern is obtained with one pitch L-c and another pitch S + c, hi one particular example, c ═ 12, S ═ 72, and L ═ 80, so one pitch is 58 and another pitch is 84.

The method 120 proceeds to operation 130 where a mask is fabricated according to the IC pattern and the determined mask parameters. Operation 130 may include generating a mandrel pattern according to the determined mask parameters and fabricating a mask defining the mandrel pattern. Operation 130 may also include generating a cut pattern based on the determined mask parameters and fabricating a mask defining the cut pattern. The mask may be a binary mask, a phase shift mask, a reflective mask, or other suitable mask.

The method 120 proceeds to operation 132 where a wafer is fabricated during a corresponding photolithography process based on the determined process parameters and using a mask, in the present embodiment, operation 132 includes method 20. for example, operation 132 includes forming the mandrel pattern 104 by a first photolithography process using a mask designed according to mask parameters L and S, forming the first spacer pattern 106 by a process including depositing a first layer of spacer material having a first thickness according to the determined process parameter b, and forming the second spacer pattern 108 by a process including depositing a second layer of spacer material having a second thickness according to the determined process parameter c.

Operation 132 may also include forming the cut pattern 110 by a second photolithography process using a mask designed according to mask parameters associated with the cut pattern, such as the respective widths and spacings of the cut features in the cut pattern.

Other embodiments of methods 20 and 120 are described below in accordance with various embodiments. Fig. 14-17 are top views of a semiconductor structure 136 at various stages of fabrication, constructed in accordance with one embodiment. The various mask parameters and process parameters are determined from the received IC layout by method 120 and fabrication of semiconductor structure 136 is achieved by method 20.

Referring to FIG. 14, a mandrel pattern 104 is formed on a substrate 102 for simplicity, the substrate 102 is not shown in the following figures, the mandrel pattern 104 includes a plurality of first features having a first width L and a first pitch S in a periodic structure, in the present embodiment, the ratio L/S is equal to 3/2 or 1.5. in one example for illustration, the width L is about 72nm and the pitch S is about 48nm the mandrel pattern 104 is formed by a process such as operation 22 of method 20.

Referring to fig. 15, a first spacer pattern 106 is formed on the sidewalls of the mandrel pattern 104 by a suitable process, such as operation 24 of method 20. In particular, the second components of the first spacer pattern 106 merge together within the gaps between the first components of the mandrel pattern 104. In this case, the first spacer material layer is deposited with a thickness b equal to half the first spacing S, expressed by the formula b-S/2. In the above example, the deposition thickness b is about 24 nm.

Referring to fig. 16, the mandrel pattern 104 is removed by a process, such as operation 26 of method 20, and a second spacer pattern 108 is formed on the sidewalls of the first spacer pattern 106 by a suitable process, such as operation 28 of method 20. In particular, the deposition thickness c of the second spacer material layer is equal to half the first thickness b, expressed by the formula c-b/2. In the above example, the deposition thickness c is about 12 nm.

Referring to fig. 17, the first spacer pattern 106 is removed through a process such as operation 30 of the method 20, thereby forming a second spacer pattern 108 having a periodic structure (regular structure) with a pitch P of S + c or P of (L + S)/2, in the above example, the pitch of the second spacer pattern 108 is about 60 nm.

More generally, for structure 136, those parameters are adjusted so that S < ═ 2b and | L-S | ═ 2c, the periodic structure of second spacer pattern 108 has a pitch P of (L + S)/2.

Fig. 18-22 are top views of a semiconductor structure 138 at various stages of fabrication constructed in accordance with another embodiment. Various mask parameters and process parameters are determined from the received IC layout by method 120 and fabrication of semiconductor structure 138 is achieved by method 20.

Referring to FIG. 18, a mandrel pattern 104 is formed on a substrate 102. for simplicity, the substrate 102 is not shown. the mandrel pattern 104 includes a plurality of first features in a periodic structure having a first width L and a first pitch S. in this embodiment, the ratio L/S is equal to 1/2 or 0.5. in one example for illustration, the width L is about 48nm and the pitch S is about 96 nm. the mandrel pattern 104 is formed by a process such as operation 22 of method 20.

Referring to fig. 19, a first spacer pattern 106 is formed on the sidewalls of the mandrel pattern 104 by a suitable process, such as operation 24 of the method 20. in particular, the first spacer material layer has a deposition thickness b equal to one-half of the first width L, expressed by the formula b L/2.

Referring to FIG. 20, the mandrel pattern 104 is removed by a process such as operation 26 of method 20.

Referring to fig. 21, a second spacer pattern 108 is formed on sidewalls of the first spacer pattern 106 by a suitable process, such as operation 28 of method 20. In particular, the deposition thickness c of the second spacer material layer is equal to half the first thickness b, expressed by the formula c-b/2. In the above example, the deposition thickness c is about 12 nm.

Referring to fig. 22, the first spacer pattern 106 is removed by a process such as operation 30 of the method 20, thereby forming a second spacer pattern 108 having a periodic structure (regular structure) with a pitch P of b + c or P of (L + S)/4, in the above example, the pitch of the second spacer pattern 108 is about 36nm.

Fig. 23-29 are top views of a semiconductor structure 140 at various stages of fabrication constructed in accordance with another embodiment. Various mask parameters and process parameters are determined from the received IC layout by method 120 and fabrication of semiconductor structure 140 is achieved by method 20.

Referring to FIG. 23, a mandrel pattern 104 is formed on a substrate 102. for simplicity, the substrate 102 is not shown. the mandrel pattern 104 includes a plurality of first features having a first pitch S in a non-periodic configuration, however, as shown in FIG. 23, the first features include a first subset having one width L1 and a second subset having another width L2. L1 is greater than L2. in this embodiment, the ratio (L1-L2)/(L2-S) is equal to 1/2 or 0.5. in one example for illustration, the width L1 is about 106nm, the L2 is about 94nm and the pitch S is about 70 nm. the mandrel pattern 104 is formed by a process such as operation 22 of method 20.

Referring to fig. 24, a first spacer pattern 106 is formed on the sidewalls of the mandrel pattern 104 by a suitable process, such as operation 24 of method 20. in this example, the deposited thickness b of the first spacer material layer is equal to L2-s. in the above example, the deposited thickness b is about 24 nm.

Referring to FIG. 25, mandrel pattern 104 is removed by a process such as operation 26 of method 20.

Referring to fig. 26, the second spacer pattern 108 is formed on the sidewalls of the first spacer pattern 106 by a suitable process such as operation 28 of the method 20, in particular, the deposition thickness c of the second spacer material layer is equal to half the first thickness b, expressed by the formula c-b/2, in which case, as shown in fig. 26, some of the third components in the second spacer pattern 108 are merged together, in the above example, the deposition thickness c is about 12nm the second spacer pattern 108 has a plurality of pitches, such as the pitches P1, P2, P3, and P4934, respectively shown in fig. 26, specifically, P1S + c, P2L-c, P3-L-c, and P4-b + c, since the merged third components will be removed in the subsequent operation, and thus the merged third components are not considered in the above example, P636-c, P5812-b + c, P6312-94 nm, and P3682-12 nm.

Referring to fig. 27, the first spacer pattern 106 is removed through a process such as operation 30 of method 20.

Referring to fig. 28, a cutting pattern 110 is formed on the substrate 102 and the second spacer pattern 108 through a process such as operation 32 of the method 20. The cutting pattern 110 includes a plurality of openings 112 defining portions of the second spacer pattern 108 to be removed. In this embodiment, the opening 112 is aligned with the incorporated third component.

Referring to fig. 29, the portion of the second spacer pattern 108 within the opening 112 of the cut pattern 110 is removed by a process such as operation 34 of method 20, thereby forming a final structure of the second spacer pattern 108 having an irregular structure of a plurality of pitches.

Fig. 30-36 are top views of semiconductor structure 142 at various stages of fabrication constructed in accordance with another embodiment. The various mask parameters and process parameters are determined from the received IC layout by method 120 and fabrication of semiconductor structure 142 is achieved by method 20.

Referring to FIG. 30, a mandrel pattern 104 is formed on a substrate 102. the mandrel pattern 104 includes a plurality of first features having a width L and a spacing S in a periodic structure.

Referring to fig. 31, a first spacer pattern 106 is formed on the sidewalls of the mandrel pattern 104 by a suitable process, such as operation 24 of method 20.

Referring to FIG. 32, mandrel pattern 104 is removed by a process such as operation 26 of method 20.

Referring to fig. 33, a second spacer pattern 108 is formed on sidewalls of the first spacer pattern 106 by a suitable process, such as operation 28 of the method 20.

Referring to fig. 34, the first spacer pattern 106 is removed by a process such as operation 30 of method 20.

Referring to fig. 35, a cutting pattern 110 is formed on the substrate 102 and the second spacer pattern 108 through a process such as operation 32 of the method 20. The cutting pattern 110 includes a plurality of openings 112 defining portions of the second spacer pattern 108 to be removed. In the present embodiment, the cutting pattern 110 has an irregular structure with a plurality of openings of corresponding widths and intervals. As shown in fig. 35, the opening 112A has a first width such that only one feature of the second spacer pattern 108 is exposed therein. The openings 112B have a second width such that two features of the second spacer pattern 108 are exposed therein. The opening 112C has a third width such that three features of the second spacer pattern 108 are exposed therein. The cutting pattern 110 may have other openings of different sizes. Further, the distance between adjacent openings may vary at different locations. For example, the spacing between the second opening 112B and the third opening 112C is different from the spacing between the third opening 112C and the fourth opening 112D.

Referring to fig. 36, the portion of the second spacer pattern 108 within the opening 112 of the cut pattern 110 is removed by a process such as operation 34 of method 20, thereby forming a final structure of the second spacer pattern 108 having an irregular structure of a plurality of pitches.

Figures 37-38 are top views of semiconductor structure 114 at various stages of fabrication constructed in accordance with another embodiment. Various mask parameters and process parameters are determined from the received IC layout by method 120 and fabrication of semiconductor structure 144 is achieved by method 20.

The process of forming the semiconductor structure 144 is similar to the process of forming the semiconductor structure 142 in that the irregular cut pattern 110 is used to obtain a final structure having a plurality of pitches and configurations of the second spacer pattern 108. in addition, as shown in FIG. 37, the mandrel pattern 104 in the semiconductor structure 144 is further defined as another irregular structure. for example, the mandrel pattern 104 in FIG. 37 includes a plurality of widths such as L1, L2, and L3 that are different from one another.

The mandrel pattern 104 is defined by a mandrel mask and is formed by a first photolithography process. The cutting pattern 110 is defined by a cutting mask and is formed by a second photolithography process. As shown in fig. 38, a more complex structure of the second spacer pattern 108 is formed on the substrate 102 by combining the first irregular pattern in the mandrel mask and the second irregular pattern in the cutting mask. Thus, the method provides a greater degree of freedom to adjust the final structure of the second spacer pattern 108.

Fig. 39 is a flow chart of a method 150 for fabricating an IC pattern. In addition, the method 150 is used to determine various parameters and is combined with the method 20 to form an IC pattern having various structures (particularly, various irregular structures). For example, method 150 is performed to determine mask and process parameters; and method 20 is performed to form the IC pattern according to the parameters determined by method 150. Method 150 may be one example of method 120. The method 150 is described with reference to fig. 39, 11, and other figures.

The method 150 begins at operation 152 by receiving an IC layout having a plurality of third features, such as the second spacer pattern 108 of fig. 9 that may define a plurality of fin active regions in the substrate 102. In this embodiment, the IC layout has two pitches P1 and P2.

The method 150 may proceed to operation 154 where a corresponding value for the pitch in the third component 108 is determined. Those values may be extracted directly from the IC layout. In the present example, pitches P1 and P2 are determined.

The method 150 proceeds to operation 156 where mask parameters L and process parameters c are determined based on the IC layout, particularly based on the respective pitches P1 and P2. in this example, as shown in fig. 11, the first pitch P1 ═ b + c and the second pitch P2 ═ L-c, parameters L and c are determined based on the formula P2 ═ L-c.

The method 150 moves to operation 158 where a process parameter b is determined based on the IC layout, and in particular, based on the corresponding pitch P1. In the present example, the parameter b is determined based on the first pitch P1 ═ b + c.

The method 150 proceeds to operation 160 and determines mask parameters S based on the IC layout, in particular based on the spatial relationship S L-2 c (meaning that the third pitch P3 — P2 is required). as shown in fig. 11, since P2 — L-c and P3 — S + c, P2 — P3 give the condition of S L-2 c, the parameters S are determined based on the formula S L-2 c.

The method 150 proceeds to operation 162 where a mask is fabricated based on the IC pattern and the determined mask parameters including L and S. operation 162 may include generating a mandrel pattern based on the determined mask parameters and fabricating a mask defining the mandrel pattern.

The method 150 may proceed to operation 164 to fabricate a wafer using a mask based on the determined process parameters and during a corresponding photolithography process in the present embodiment, operation 164 includes method 20. for example, operation 164 includes forming the mandrel pattern 104 by a first photolithography process using a mask designed according to mask parameters L and S, forming the first spacer pattern 106 by a process including depositing a first layer of spacer material having a first thickness according to the determined process parameter b, and forming the second spacer pattern 108 by a process including depositing a second layer of spacer material having a second thickness according to the determined process parameter c.

Operation 164 may also include forming the cut pattern 110 by a second photolithography process using a mask designed according to mask parameters associated with the cut pattern, such as the respective widths and spacings of the cut features in the cut pattern.

Fig. 40 is a flow chart of a method 170 for fabricating an IC pattern. In addition, the method 170 is used to determine various parameters and is combined with the method 20 to form an IC pattern having various structures (particularly, various irregular structures). For example, method 170 is performed to determine mask and process parameters; and method 20 is performed to form the IC pattern according to the parameters determined by method 170. Method 170 may be one example of method 120. The method 170 is described with reference to fig. 40, 11, and other figures.

The method 170 begins at operation 172 by receiving an IC layout having a plurality of third features, such as the second spacer pattern 108 of fig. 9 that may define a plurality of fin active regions in the substrate 102. In the present embodiment, the IC layout has pitches P1, P2, and P3.

The method 170 may proceed to operation 174 to determine a corresponding value for the pitch in the third component 108. Those values may be extracted directly from the IC layout. In this example, pitches P1, P2, and P3 are determined.

The method 170 proceeds to operation 176 and determines mask parameters L and process parameters c based on the IC layout, in particular based on the respective pitches P1 and P2. in this example, the first pitch P1 is b + c, the second pitch P2 is L-c, and the third pitch P3 is S + c (assuming that the third component of the second spacer pattern 108 in the gap between two adjacent first components of the mandrel pattern 104 is removed by etching through the opening 112 of the cut pattern 110.) otherwise, as shown in fig. 11, P3 is S-2b-c, parameters L and c are determined based on the formula P2L-c.

The method 170 proceeds to operation 178 where a process parameter b is determined based on the IC layout, and in particular, based on the corresponding pitch P1. In the present example, the parameter b is determined based on the first pitch P1 ═ b + c.

The method 170 proceeds to operation 180 where mask parameters S are determined based on the IC layout, and in particular, based on the corresponding pitch P3. In this example, the parameter S is determined based on the third pitch P3 ═ S + c. Otherwise, if the cutting pattern 110 is not applied to remove the third features in the gaps between adjacent third features of the mandrel pattern 104, the parameter S is determined based on the formula P3 — S-2 b-c.

The method 170 proceeds to operation 182 where a mask is fabricated based on the IC pattern and the determined mask parameters including L and S. operation 182 may include generating a mandrel pattern based on the determined mask parameters and fabricating a mask defining the mandrel pattern.

The method 170 proceeds to operation 184 where a wafer is fabricated based on the determined process parameters and using a mask during a corresponding photolithography process, in the present embodiment, operation 184 includes method 20. for example, operation 184 includes forming a mandrel pattern 104 by a first photolithography process using a mask designed according to mask parameters L and S, forming a first spacer pattern 106 by a process including depositing a first layer of spacer material having a first thickness according to the determined process parameter b, and forming a second spacer pattern 108 by a process including depositing a second layer of spacer material having a second thickness according to the determined process parameter c.

Operation 184 may also include forming the cut pattern 110 by a second photolithography process using a mask designed according to mask parameters associated with the cut pattern, such as the respective widths and spacings of the cut features in the cut pattern.

By using the disclosed method, complex IC patterns are formed by method 20 by adjusting various mask and process parameters that are further obtained by method 120. In particular, the disclosed method is capable of forming a pattern of non-periodic (irregular) structures having a plurality of pitches. Other advantages may occur in different embodiments. For example, by implementing the disclosed methods, complex structures may be formed with fewer fabrication steps and/or lower resolution lithography systems, thus reducing fabrication costs. Other embodiments and variations may be implemented without departing from the spirit of the invention. In one embodiment, rather than forming fin-shaped active regions, other IC components such as multiple gate electrodes for field effect transistors or metal lines for interconnect structures are formed by the disclosed method.

Accordingly, the present invention provides an Integrated Circuit (IC) design method. The method includes forming a mandrel pattern on a substrate by a first photolithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.

The present invention also provides another embodiment of a method for an Integrated Circuit (IC). The method includes receiving an IC layout having a plurality of components; determining a pitch in the plurality of components; determining mask parameters and process parameters based on the pitch in the feature; and manufacturing the mask according to the mask parameters.

The present invention also provides another embodiment of a method for an Integrated Circuit (IC), the method including receiving an IC layout having a plurality of components with mutually different first and second pitches P1 and P2, determining a first process parameter c based on P2-L-c, wherein L is a first width of the components, and determining a second process parameter b based on P1-b + c.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.