阅读说明：本技术 一种具有像元失配校正功能的读出电路 (Reading circuit with pixel mismatch correction function ) 是由 韦良忠 陈黎明 李磊 于 2020-04-23 设计创作，主要内容包括：本发明涉及一种具有像元失配校正功能的读出电路,构建偏置电路模块101、减法电路模块102、第一电流镜DAC模块103、第二电流镜DAC模块104、积分放大电路模块105,通过各电路模块之间的连接关系,构建最终非制冷光电焦平面阵列读出电路,能够减弱像元失配影响,具有低电路噪声、适应性强的优点,能够实现像元失配校正功能,提高光电检测的精度。(The invention relates to a readout circuit with a pixel mismatch correction function, which is characterized in that a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104 and an integral amplification circuit module 105 are constructed, and a final uncooled photoelectric focal plane array readout circuit is constructed through the connection relationship among the circuit modules, so that the pixel mismatch influence can be weakened, the readout circuit has the advantages of low circuit noise and strong adaptability, the pixel mismatch correction function can be realized, and the photoelectric detection precision is improved.)

1. A kind of readout circuit with mismatch correction function of the picture element, is used for realizing the infrared radiation signal reading of the picture element, characterized by: the circuit comprises a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104 and an integral amplification circuit module 105;

the bias circuit module 101 comprises a dummy pixel branch circuit, a detection pixel and blind pixel branch circuit and is used for biasing the detection pixel and the blind pixel;

the subtraction circuit module 102 is respectively connected to the output end of the dummy pixel branch circuit, the output end of the detection pixel and the output end of the blind pixel branch circuit, and is used for performing subtraction operation on the outputs of the two branch circuits;

the first current mirror DAC module 103 is connected to the output end of the subtraction circuit module 102, and scales the output current of the subtraction circuit module 102 according to a preset proportion;

the second current mirror DAC module 104 is connected to the output end of the first current mirror DAC module 103 and the output end of the dummy pixel branch circuit in the bias circuit module 101, and scales the connected current according to a preset proportion;

the integral amplification circuit module 105 is connected to the output end of the second current mirror DAC module 104 and the output ends of the detection pixel and blind pixel branch circuit in the bias circuit module 101, and performs integral amplification on the connected current and outputs the amplified current, thereby reading the infrared radiation signal of the pixel.

2. A readout circuit having a pixel mismatch correction function according to claim 1, wherein: the detection pixel and the blind pixel branch circuit in the bias circuit module 101 comprise a detection pixel R_sAnd a blind pixel element R_bWherein the detection pixel R_sOne end of the blind pixel R_bOne end of the detection pixel is respectively connected with a power supply and a detection pixel R_sThe other end of the first MOS transistor MP1 is butted with a source end of a first MOS transistor MP1, a gate end of the first MOS transistor MP1 is butted with a gate end of a second MOS transistor MP2, a gate end of a third MOS transistor MP3 and a gate end of a fourth MOS transistor MP4 respectively, a drain end of the first MOS transistor MP1 forms a second output end of the detection pixel and blind pixel branch circuit, meanwhile, a drain end of the first MOS transistor MP1 is butted with a source end of the second MOS transistor MP2, and a drain end of the second MOS transistor MP2 is grounded; blind pixel element R_bThe other end of the third MOS transistor MP3 is connected to the source terminal of the third MOS transistor MP3, the drain terminal of the third MOS transistor MP3 forms the first output terminal of the detection pixel and blind pixel branch circuit, the drain terminal of the third MOS transistor MP3 is connected to the source terminal of the fourth MOS transistor MP4, and the drain terminal of the fourth MOS transistor MP4 is grounded.

3. A readout circuit having a pixel mismatch correction function according to claim 2, wherein: the dummy pixel branch circuit in the bias circuit module 101 includes a first reference pixel R_b1And a second reference pixel element R_b2Wherein the first reference pixel element R_b1One end of the first reference pixel and the second reference pixel R_b2One end of the first reference pixel is respectively connected with a power supply and a first reference pixel_b1The other end of the first transistor is butted with a source end of a fifth MOS transistor MP5, a gate end of the fifth MOS transistor MP5 is butted with a gate end of a sixth MOS transistor MP6, a gate end of a seventh MOS transistor MP7 and a gate end of an eighth MOS transistor MP8 respectively, a drain end of the fifth MOS transistor MP5 forms a first output end of the dummy pixel branch circuit, meanwhile, a drain end of the fifth MOS transistor MP5 is butted with a source end of the sixth MOS transistor MP6, and a drain end of the sixth MOS transistor MP6 is grounded; second reference pixel element R_b2The other end pair ofThe source end of the seventh MOS transistor MP7 is connected, the drain end of the seventh MOS transistor MP7 forms the second output end of the dummy pixel branch circuit, the drain end of the seventh MOS transistor MP7 is connected to the source end of the eighth MOS transistor MP8, and the drain end of the eighth MOS transistor MP8 is grounded.

4. A readout circuit having a pixel mismatch correction function according to claim 3, wherein: the subtraction circuit module 102 comprises an operational amplifier A1, wherein the positive input terminals of the operational amplifier A1 are respectively connected to the third semiconductor resistors R₃One end of the resistor R, a fifth semiconductor resistor R₅One end of (1), a fifth semiconductor resistor R₅Is grounded, and a third semiconductor resistor R₃The other end of the first half-bridge is respectively butted with a first output end of the detection pixel and the blind pixel branch circuit and a first semiconductor resistor R₁One end of (1), the first semiconductor resistor R₁The other end of the first and second electrodes is grounded; the negative pole input ends of the operational amplifiers A1 are respectively connected with the fourth semiconductor resistors R₄One end of the resistor R, and a sixth semiconductor resistor R₆Of the fourth semiconductor resistor R₄The other end of the dummy pixel branch circuit is respectively butted with a first output end of the dummy pixel branch circuit and a second semiconductor resistor R₂One end of (1), a second semiconductor resistor R₂The other end of the first and second electrodes is grounded; the output terminal of the operational amplifier A1 forms the output terminal of the subtracting circuit block 102, and the output terminals of the operational amplifier A1 are connected to the sixth semiconductor resistors R₆Another terminal of (1), a seventh semiconductor resistor R₇Of one end of (1), a seventh semiconductor resistor R₇And the other end of the same is grounded.

5. A readout circuit having a pixel mismatch correction function according to claim 3 or 4, wherein: the second current mirror DAC module 104 comprises an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain terminal of the eleventh MOS transistor MP11 is connected with the gate terminal thereof and forms the input terminal of the second current mirror DAC module 104, and the input terminal is butted with the second output terminal of the dummy pixel branch circuit and the first output terminalThe output end of the current mirror DAC module 103 is connected to the gate of the eleventh MOS transistor MP11, the gate of the eleventh MOS transistor MP12 is connected to the gate of the twelfth MOS transistor MP 3578, and the source of the eleventh MOS transistor MP11 is connected in series with the eighth semiconductor resistor R₈Then, connecting to ground; the source end of the twelfth MOS transistor MP12 is connected in series with the ninth semiconductor resistor R₉Then, in parallel, the drain terminal of the twelfth MOS transistor MP12 constitutes the output terminal of the second current mirror DAC module 104.

6. A readout circuit having a pixel mismatch correction function according to claim 5, wherein: the integrating and amplifying circuit module 105 comprises an operational amplifier A2, wherein a positive input terminal of the operational amplifier A2 is connected with a preset correction voltage V_refThe negative pole input end of the operational amplifier A2 is connected in series with a tenth semiconductor resistor R₁₀Then, an input end of the integral amplifying circuit module 105 is formed, the input end is connected with a second output end of the detection pixel and blind pixel branch circuit and an output end of the second current mirror DAC module 104, and meanwhile, a negative input end of the operational amplifier A2 is respectively connected with a capacitor C_intOne end of the switch S, the control switch S_rstOne end of (1), capacitor C_intThe other end of (1), a control switch S_rstThe other end of the operational amplifier a2, and the output end of the operational amplifier a2, and forms the output end of the integrating and amplifying circuit module 105.

7. A readout circuit having a pixel mismatch correction function according to claim 1, wherein: the first current mirror DAC module 103 includes a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein a source terminal of the ninth MOS transistor MP9 and a source terminal of the tenth MOS transistor MP10 are respectively connected to a power supply, a drain terminal of the ninth MOS transistor MP9 is connected to a gate terminal thereof and forms an input terminal of the first current mirror DAC module 103, a gate terminal of the ninth MOS transistor MP9 is connected to a gate terminal of the tenth MOS transistor MP10, and a drain terminal of the tenth MOS transistor MP10 forms an output terminal of the first current mirror DAC module 103.

Technical Field

The invention relates to a readout circuit with a pixel mismatch correction function, and belongs to the field of uncooled infrared focal plane array readout circuits.

Background

Infrared detection refers to a technique of detecting an infrared radiation signal of an object by means of a photoelectric technique or the like and converting the infrared radiation signal into an electric signal. The microbolometer type uncooled infrared focal plane detector utilizes a thermosensitive material to manufacture a microbolometer pixel, and under the condition that temperature rise is changed due to infrared radiation, the equivalent resistance of the microbolometer pixel is changed, so that infrared detection is responded. The microbolometer pixel is prepared by adopting an MEMS (micro electro mechanical systems) process, however, due to undesirable and inevitable factors, the resistance of the microbolometer pixel may have great difference, the pixel mismatch influence is generated, the problems of circuit noise and non-uniformity are further caused, the accuracy of a detected signal in the actual work of the infrared detector is directly influenced, and the non-uniformity can cause the failure of a reading circuit under the worst condition. Therefore, the detection precision of the microbolometer type uncooled infrared focal plane detector in the prior art needs to be further improved.

Disclosure of Invention

The invention aims to solve the technical problem of providing a reading circuit with a pixel mismatch correction function, which can weaken the influence of pixel mismatch, has the advantages of low circuit noise and strong adaptability, can realize the pixel mismatch correction function and improve the accuracy of photoelectric detection.

The invention adopts the following technical scheme for solving the technical problems: the invention designs a readout circuit with a pixel mismatch correction function, which is used for reading infrared radiation signals of pixels and comprises a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104 and an integral amplification circuit module 105;

the bias circuit module 101 comprises a dummy pixel branch circuit, a detection pixel and blind pixel branch circuit and is used for biasing the detection pixel and the blind pixel;

the subtraction circuit module 102 is respectively connected to the output end of the dummy pixel branch circuit, the output end of the detection pixel and the output end of the blind pixel branch circuit, and is used for performing subtraction operation on the outputs of the two branch circuits;

the first current mirror DAC module 103 is connected to the output end of the subtraction circuit module 102, and scales the output current of the subtraction circuit module 102 according to a preset proportion;

the second current mirror DAC module 104 is connected to the output end of the first current mirror DAC module 103 and the output end of the dummy pixel branch circuit in the bias circuit module 101, and scales the connected current according to a preset proportion;

the integral amplification circuit module 105 is connected to the output end of the second current mirror DAC module 104 and the output ends of the detection pixel and blind pixel branch circuit in the bias circuit module 101, and performs integral amplification on the connected current and outputs the amplified current, thereby reading the infrared radiation signal of the pixel.

As a preferred technical scheme of the invention: the detection pixel and the blind pixel branch circuit in the bias circuit module 101 comprise a detection pixel R_sAnd a blind pixel element R_bWherein the detection pixel R_sOne end of the blind pixel R_bOne end of the detection pixel is respectively connected with a power supply and a detection pixel R_sThe other end of the first MOS transistor MP1 is butted with a source end of a first MOS transistor MP1, a gate end of the first MOS transistor MP1 is butted with a gate end of a second MOS transistor MP2, a gate end of a third MOS transistor MP3 and a gate end of a fourth MOS transistor MP4 respectively, a drain end of the first MOS transistor MP1 forms a second output end of the detection pixel and blind pixel branch circuit, meanwhile, a drain end of the first MOS transistor MP1 is butted with a source end of the second MOS transistor MP2, and a drain end of the second MOS transistor MP2 is grounded; blind pixel element R_bThe other end of the third MOS transistor MP3 is connected to the source terminal of the third MOS transistor MP3, the drain terminal of the third MOS transistor MP3 forms the first output terminal of the detection pixel and blind pixel branch circuit, the drain terminal of the third MOS transistor MP3 is connected to the source terminal of the fourth MOS transistor MP4, and the drain terminal of the fourth MOS transistor MP4 is grounded.

As a preferred technical scheme of the invention: the dummy pixel branch circuit in the bias circuit module 101 includes a first reference pixel R_b1And a second reference pixel element R_b2Wherein the first reference pixel element R_b1One end of the first reference pixel and the second reference pixel R_b2One end of the first reference pixel is respectively connected with a power supply and a first reference pixel_b1The other end of the first transistor is butted with a source end of a fifth MOS transistor MP5, a gate end of the fifth MOS transistor MP5 is butted with a gate end of a sixth MOS transistor MP6, a gate end of a seventh MOS transistor MP7 and a gate end of an eighth MOS transistor MP8 respectively, a drain end of the fifth MOS transistor MP5 forms a first output end of the dummy pixel branch circuit, meanwhile, a drain end of the fifth MOS transistor MP5 is butted with a source end of the sixth MOS transistor MP6, and a drain end of the sixth MOS transistor MP6 is grounded; second reference pixel element R_b2The other end of the first end is butted with the second endThe source end of the seventh MOS transistor MP7, the drain end of the seventh MOS transistor MP7 form the second output end of the dummy pixel branch circuit, meanwhile, the drain end of the seventh MOS transistor MP7 is butted to the source end of the eighth MOS transistor MP8, and the drain end of the eighth MOS transistor MP8 is grounded.

As a preferred technical scheme of the invention: the subtraction circuit module 102 comprises an operational amplifier A1, wherein the positive input terminals of the operational amplifier A1 are respectively connected to the third semiconductor resistors R₃One end of the resistor R, a fifth semiconductor resistor R₅One end of (1), a fifth semiconductor resistor R₅Is grounded, and a third semiconductor resistor R₃The other end of the first half-bridge is respectively butted with a first output end of the detection pixel and the blind pixel branch circuit and a first semiconductor resistor R₁One end of (1), the first semiconductor resistor R₁The other end of the first and second electrodes is grounded; the negative pole input ends of the operational amplifiers A1 are respectively connected with the fourth semiconductor resistors R₄One end of the resistor R, and a sixth semiconductor resistor R₆Of the fourth semiconductor resistor R₄The other end of the dummy pixel branch circuit is respectively butted with a first output end of the dummy pixel branch circuit and a second semiconductor resistor R₂One end of (1), a second semiconductor resistor R₂The other end of the first and second electrodes is grounded; the output terminal of the operational amplifier A1 forms the output terminal of the subtracting circuit block 102, and the output terminals of the operational amplifier A1 are connected to the sixth semiconductor resistors R₆Another terminal of (1), a seventh semiconductor resistor R₇Of one end of (1), a seventh semiconductor resistor R₇And the other end of the same is grounded.

As a preferred technical scheme of the invention: the second current mirror DAC module 104 comprises an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain terminal of the eleventh MOS transistor MP11 is connected with the gate terminal thereof and forms the input terminal of the second current mirror DAC module 104, the input terminal is butted with the second output terminal of the dummy pixel branch circuit and the output terminal of the first current mirror DAC module 103, meanwhile, the gate terminal of the eleventh MOS transistor MP11 is butted with the gate terminal of the twelfth MOS transistor MP12, the source terminal of the eleventh MOS transistor MP11 is connected with an eighth semiconductor resistor R in series₈Then, connecting to ground; tenth itemThe source ends of the two MOS transistors MP12 are connected in series with a ninth semiconductor resistor R₉Then, in parallel, the drain terminal of the twelfth MOS transistor MP12 constitutes the output terminal of the second current mirror DAC module 104.

As a preferred technical scheme of the invention: the integrating and amplifying circuit module 105 comprises an operational amplifier A2, wherein a positive input terminal of the operational amplifier A2 is connected with a preset correction voltage V_refThe negative pole input end of the operational amplifier A2 is connected in series with a tenth semiconductor resistor R₁₀Then, an input end of the integral amplifying circuit module 105 is formed, the input end is connected with a second output end of the detection pixel and blind pixel branch circuit and an output end of the second current mirror DAC module 104, and meanwhile, a negative input end of the operational amplifier A2 is respectively connected with a capacitor C_intOne end of the switch S, the control switch S_rstOne end of (1), capacitor C_intThe other end of (1), a control switch S_rstThe other end of the operational amplifier a2, and the output end of the operational amplifier a2, and forms the output end of the integrating and amplifying circuit module 105.

As a preferred technical scheme of the invention: the first current mirror DAC module 103 includes a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein a source terminal of the ninth MOS transistor MP9 and a source terminal of the tenth MOS transistor MP10 are respectively connected to a power supply, a drain terminal of the ninth MOS transistor MP9 is connected to a gate terminal thereof and forms an input terminal of the first current mirror DAC module 103, a gate terminal of the ninth MOS transistor MP9 is connected to a gate terminal of the tenth MOS transistor MP10, and a drain terminal of the tenth MOS transistor MP10 forms an output terminal of the first current mirror DAC module 103.

Compared with the prior art, the reading circuit with the pixel mismatch correction function has the following technical effects by adopting the technical scheme:

the readout circuit with the pixel mismatch correction function is designed, the bias circuit module 101, the subtraction circuit module 102, the first current mirror DAC module 103, the second current mirror DAC module 104 and the integral amplification circuit module 105 are constructed, and the final uncooled photoelectric focal plane array readout circuit is constructed through the connection relationship among the circuit modules, so that the pixel mismatch influence can be weakened, the advantages of low circuit noise and strong adaptability are achieved, the pixel mismatch correction function can be realized, and the photoelectric detection precision is improved.

Drawings

Fig. 1 is a schematic diagram of a readout circuit with pixel mismatch correction designed by the present invention.

Detailed Description

The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.

The invention designs a readout circuit with a pixel mismatch correction function, which is used for reading infrared radiation signals of pixels, and specifically comprises a bias circuit module 101, a subtraction circuit module 102, a first current mirror DAC module 103, a second current mirror DAC module 104 and an integral amplification circuit module 105, as shown in FIG. 1.

The bias circuit module 101 comprises a dummy pixel branch circuit, a detection pixel and blind pixel branch circuit and is used for biasing the detection pixel and the blind pixel;

the subtraction circuit module 102 is respectively connected to the output end of the dummy pixel branch circuit, the output end of the detection pixel and the output end of the blind pixel branch circuit, and is used for performing subtraction operation on the outputs of the two branch circuits;

the first current mirror DAC module 103 is connected to the output end of the subtraction circuit module 102, and scales the output current of the subtraction circuit module 102 according to a preset proportion;

the second current mirror DAC module 104 is connected to the output end of the first current mirror DAC module 103 and the output end of the dummy pixel branch circuit in the bias circuit module 101, and scales the connected current according to a preset proportion;

the integral amplification circuit module 105 is connected to the output end of the second current mirror DAC module 104 and the output ends of the detection pixel and blind pixel branch circuit in the bias circuit module 101, and performs integral amplification on the connected current and outputs the amplified current, thereby reading the infrared radiation signal of the pixel.

Based on the above design of the bias circuit module 101, the subtraction circuit module 102, the first current mirror DAC module 103, and the second current mirror DAC moduleThe connection between the DAC module 104 and the integrating and amplifying circuit module 105 further specifically designs the detailed circuit structure of each circuit module, wherein the detection pixel in the bias circuit module 101 and the blind pixel branch circuit include the detection pixel R_sAnd a blind pixel element R_bWherein the detection pixel R_sOne end of the blind pixel R_bOne end of the detection pixel is respectively connected with a power supply and a detection pixel R_sThe other end of the first MOS transistor MP1 is butted with a source end of a first MOS transistor MP1, a gate end of the first MOS transistor MP1 is butted with a gate end of a second MOS transistor MP2, a gate end of a third MOS transistor MP3 and a gate end of a fourth MOS transistor MP4 respectively, a drain end of the first MOS transistor MP1 forms a second output end of the detection pixel and blind pixel branch circuit, meanwhile, a drain end of the first MOS transistor MP1 is butted with a source end of the second MOS transistor MP2, and a drain end of the second MOS transistor MP2 is grounded; blind pixel element R_bThe other end of the third MOS transistor MP3 is connected to the source terminal of the third MOS transistor MP3, the drain terminal of the third MOS transistor MP3 forms the first output terminal of the detection pixel and blind pixel branch circuit, the drain terminal of the third MOS transistor MP3 is connected to the source terminal of the fourth MOS transistor MP4, and the drain terminal of the fourth MOS transistor MP4 is grounded.

The dummy pixel branch circuit in the bias circuit module 101 includes a first reference pixel R_b1And a second reference pixel element R_b2Wherein the first reference pixel element R_b1One end of the first reference pixel and the second reference pixel R_b2One end of the first reference pixel is respectively connected with a power supply and a first reference pixel_b1The other end of the first transistor is butted with a source end of a fifth MOS transistor MP5, a gate end of the fifth MOS transistor MP5 is butted with a gate end of a sixth MOS transistor MP6, a gate end of a seventh MOS transistor MP7 and a gate end of an eighth MOS transistor MP8 respectively, a drain end of the fifth MOS transistor MP5 forms a first output end of the dummy pixel branch circuit, meanwhile, a drain end of the fifth MOS transistor MP5 is butted with a source end of the sixth MOS transistor MP6, and a drain end of the sixth MOS transistor MP6 is grounded; second reference pixel element R_b2The other end of the first MOS transistor MP7 is connected with the source end of a seventh MOS transistor MP7, the drain end of the seventh MOS transistor MP7 forms the second output end of the dummy pixel branch circuit, and the drain end of the seventh MOS transistor MP7 is connected with the source end of an eighth MOS transistor MP8, and an eighth MOS crystalThe drain of transistor MP8 is connected to ground.

The subtracting circuit module 102 includes an operational amplifier A1, wherein the positive input terminals of the operational amplifier A1 are respectively connected to the third semiconductor resistors R₃One end of the resistor R, a fifth semiconductor resistor R₅One end of (1), a fifth semiconductor resistor R₅Is grounded, and a third semiconductor resistor R₃The other end of the first half-bridge is respectively butted with a first output end of the detection pixel and the blind pixel branch circuit and a first semiconductor resistor R₁One end of (1), the first semiconductor resistor R₁The other end of the first and second electrodes is grounded; the negative pole input ends of the operational amplifiers A1 are respectively connected with the fourth semiconductor resistors R₄One end of the resistor R, and a sixth semiconductor resistor R₆Of the fourth semiconductor resistor R₄The other end of the dummy pixel branch circuit is respectively butted with a first output end of the dummy pixel branch circuit and a second semiconductor resistor R₂One end of (1), a second semiconductor resistor R₂The other end of the first and second electrodes is grounded; the output terminal of the operational amplifier A1 forms the output terminal of the subtracting circuit block 102, and the output terminals of the operational amplifier A1 are connected to the sixth semiconductor resistors R₆Another terminal of (1), a seventh semiconductor resistor R₇Of one end of (1), a seventh semiconductor resistor R₇And the other end of the same is grounded.

The first current mirror DAC module 103 includes a ninth MOS transistor MP9 and a tenth MOS transistor MP10, wherein a source terminal of the ninth MOS transistor MP9 and a source terminal of the tenth MOS transistor MP10 are respectively connected to a power supply, a drain terminal of the ninth MOS transistor MP9 is connected to a gate terminal thereof and forms an input terminal of the first current mirror DAC module 103, a gate terminal of the ninth MOS transistor MP9 is connected to a gate terminal of the tenth MOS transistor MP10, and a drain terminal of the tenth MOS transistor MP10 forms an output terminal of the first current mirror DAC module 103.

The second current mirror DAC module 104 comprises an eleventh MOS transistor MP11 and a twelfth MOS transistor MP12, wherein the drain terminal of the eleventh MOS transistor MP11 is connected with the gate terminal thereof and forms the input terminal of the second current mirror DAC module 104, the input terminal is in butt joint with the second output terminal of the dummy pixel branch circuit and the output terminal of the first current mirror DAC module 103, and meanwhile, the drain terminal of the eleventh MOS transistor MP11 is connected with the gate terminal thereof, and the input terminal of the second current mirror DAC module 104 is in butt joint with the second output terminal ofThe gate terminal of the eleventh MOS transistor MP11 is butted against the gate terminal of the twelfth MOS transistor MP12, and the source terminal of the eleventh MOS transistor MP11 is connected in series with the eighth semiconductor resistor R₈Then, connecting to ground; the source end of the twelfth MOS transistor MP12 is connected in series with the ninth semiconductor resistor R₉Then, in parallel, the drain terminal of the twelfth MOS transistor MP12 constitutes the output terminal of the second current mirror DAC module 104.

The integrating and amplifying circuit module 105 comprises an operational amplifier A2, wherein the positive input terminal of the operational amplifier A2 is connected to a preset correction voltage V_refThe negative pole input end of the operational amplifier A2 is connected in series with a tenth semiconductor resistor R₁₀Then, an input end of the integral amplifying circuit module 105 is formed, the input end is connected with a second output end of the detection pixel and blind pixel branch circuit and an output end of the second current mirror DAC module 104, and meanwhile, a negative input end of the operational amplifier A2 is respectively connected with a capacitor C_intOne end of the switch S, the control switch S_rstOne end of (1), capacitor C_intThe other end of (1), a control switch S_rstThe other end of the operational amplifier a2, and the output end of the operational amplifier a2, and forms the output end of the integrating and amplifying circuit module 105.

The reading circuit with the pixel mismatch correction function designed by the invention is applied to the reality, as shown in figure 1, when the pixel R is detected due to MEMS process error at the initial temperature_sResistance R 'of'_sAnd a blind pixel element R_bResistance R 'of'_bThe ratio of the components is as follows:

namely obtaining the detection pixel R_sResistance R 'of'_sAnd a blind pixel element R_bResistance R 'of'_bThe ratio of (1+ k) to (1). In practical application, the DC bias current I_DCCurrent change Δ I due to self-heating effect_SHCurrent change Δ I due to infrared radiation heat_IR：

Wherein, V_biasIs a pixel bias voltage, R₀Is an initial resistance value of the pixel, α is a temperature coefficient of resistance, C_th、R_thIs the thermal constant, P, of the pixel bridge leg_IRFor detecting the infrared radiation energy absorbed by the picture element.

I.e., as shown in FIG. 1, so that it passes through the blind pixel R_bCurrent of (I)_b＝I_DC+ΔI_SH(ii) a By detecting the pixel R_sCurrent of

The subtraction circuit block 102 then first subtracts the current I_DCAnd I_bRespectively at the semiconductor resistor R₂A semiconductor resistor R₁Converting the voltage into a voltage, obtaining a difference voltage through a subtraction circuit, and finally passing the difference voltage through a semiconductor resistor R₇Conversion to a current Δ I_SHAnd is transmitted to the first current mirror DAC module 103, for a current Δ I by the first current mirror DAC module 103_SHScaling according to 1 (1+ k) to obtain a mirror current delta I_SHV (1+ k) and continues into the second current mirror DAC module 104.

In the second current mirror DAC module 104, the current I is first implemented_DCAnd a mirror current Δ I_SH/(1+ k) and then the resulting total current I_DC+ΔI_SHV (1+ k), scaling according to 1 (1+ k) to obtain image current I_DC/(1+k)+ΔI_SH/(1+k)²And continues to the integrating and amplifying circuit module 105.

In the integrating and amplifying circuit module 105, for the current I_sAnd a mirror current I_DC/(1+k)+ΔI_SH/(1+k)²Performing difference making, realizing integral amplification of the current with small difference value, and finally obtaining the output voltage V subjected to pixel mismatch correction_out。

According to the technical scheme, the readout circuit with the pixel mismatch correction function is designed, the bias circuit module 101, the subtraction circuit module 102, the first current mirror DAC module 103, the second current mirror DAC module 104 and the integral amplification circuit module 105 are constructed, and the final uncooled photoelectric focal plane array readout circuit is constructed through the connection relation among the circuit modules, so that the pixel mismatch influence can be weakened, the advantages of low circuit noise and strong adaptability are achieved, the pixel mismatch correction function can be achieved, and the photoelectric detection precision is improved.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.