阅读说明：本技术 使用自下而上氧化途径的具有削减沟道结构的栅极全环绕式集成电路结构 (Gate all-around integrated circuit structure with reduced channel structure using bottom-up oxidation approach ) 是由 W.拉赫马迪 G.杜威 J.T.卡瓦列罗斯 A.利拉克 P.莫罗 A.范 黄政颖 E. 于 2019-12-04 设计创作，主要内容包括：描述了具有去填充沟道结构的栅极全环绕式集成电路结构,以及使用自下而上氧化途径制备具有去填充沟道结构的栅极全环绕式集成电路结构的方法。例如,集成电路结构包括衬底上方的纳米线竖直布置。纳米线竖直布置具有在一个或多个氧化纳米线上方的一个或多个有源纳米线。栅极堆叠在纳米线竖直布置之上,并环绕一个或多个氧化纳米线。(A gate all-around integrated circuit structure having a depopulated channel structure and a method of fabricating a gate all-around integrated circuit structure having a depopulated channel structure using a bottom-up oxidation approach are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The nanowire vertical arrangement has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and surrounds one or more oxidized nanowires.)

1. An integrated circuit structure, comprising:

a vertical arrangement of nanowires above a substrate, the vertical arrangement of nanowires having one or more active nanowires above one or more oxidized nanowires;

a gate stack over the nanowire vertical arrangement and surrounding the one or more oxidized nanowires.

2. The integrated circuit structure of claim 1, wherein the one or more oxidized nanowires have an oxidation catalyst layer thereon.

3. The integrated circuit structure of claim 2, wherein the oxidation catalyst layer comprises alumina.

4. The integrated circuit structure of claim 1, 2 or 3, further comprising:

an epitaxial source or drain structure at a vertically disposed end of the nanowire.

5. The integrated circuit structure of claim 4, wherein the epitaxial source or drain structure is a discrete epitaxial source or drain structure.

6. The integrated circuit structure of claim 4, wherein the epitaxial source or drain structure is a non-discrete epitaxial source or drain structure.

7. The integrated circuit structure of claim 4, wherein the gate stack has dielectric sidewall spacers and the epitaxial source or drain structure is an embedded epitaxial source or drain structure extending under the dielectric sidewall spacers of the gate stack.

8. The integrated circuit structure of claim 4, further comprising:

a pair of conductive contact structures coupled to the epitaxial source or drain structures.

9. The integrated circuit structure of claim 8, wherein the pair of conductive contact structures is an asymmetric pair of conductive contact structures.

10. The integrated circuit structure of claim 1, 2 or 3, wherein the nanowire is vertically disposed above a fin.

11. The integrated circuit structure of claim 1, 2 or 3, wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

12. An integrated circuit structure, comprising:

a first vertical arrangement of nanowires above a substrate having a greater number of active nanowires than the second vertical arrangement of nanowires, the first and second vertical arrangements of nanowires having an uppermost nanowire and a lowermost nanowire that are co-planar, and the second vertical arrangement of nanowires having a lowermost nanowire that is oxidized;

a first gate stack over the first vertical arrangement of nanowires; and

a second gate stack over the nanowire second vertical arrangement and surrounding the oxidized bottommost nanowire.

13. The integrated circuit structure of claim 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is the same as a horizontal width of the nanowire of the second vertical arrangement of nanowires.

14. The integrated circuit structure of claim 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is greater than a horizontal width of the nanowire of the second vertical arrangement of nanowires.

15. The integrated circuit structure of claim 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is less than a horizontal width of the nanowire of the second vertical arrangement of nanowires.

16. The integrated circuit structure of claim 12, 13, 14 or 15, further comprising:

a first epitaxial source or drain structure at a first vertically disposed end of the nanowire; and

a second epitaxial source or drain structure at a second vertically disposed end of the nanowire.

17. The integrated circuit structure of claim 16 wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

18. The integrated circuit structure of claim 16, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

19. The integrated circuit structure of claim 16, wherein the first gate stack has a dielectric sidewall spacer and the first epitaxial source or drain structure is a first embedded epitaxial source or drain structure extending under the dielectric sidewall spacer of the first gate stack, and wherein the second gate stack has a dielectric sidewall spacer and the second epitaxial source or drain structure is a second embedded epitaxial source or drain structure extending under the dielectric sidewall spacer of the second gate stack.

20. The integrated circuit structure of claim 16, further comprising:

a first pair of conductive contact structures coupled to the first epitaxial source or drain structure; and

a second pair of conductive contact structures coupled to the second epitaxial source or drain structure.

21. The integrated circuit structure of claim 12, 13, 14 or 15, wherein the nanowire is first vertically disposed over a first fin and the nanowire is second vertically disposed over a second fin.

22. The integrated circuit structure of claim 12, 13, 14 or 15, further comprising:

a gate end cap isolation structure between and in contact with the first and second gate stacks.

23. The integrated circuit structure of claim 12, 13, 14 or 15, wherein the first and second gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode.

24. A method of fabricating an integrated circuit structure, the method comprising:

forming a vertical arrangement of active nanowires over a substrate;

oxidizing one or more bottommost nanowires of the vertical arrangement of active nanowires, but not oxidizing one or more uppermost nanowires of the vertical arrangement of active nanowires; and

forming a gate stack around the oxidized one or more bottommost nanowires and around the one or more uppermost nanowires.

25. The method of claim 24, wherein oxidizing the one or more bottommost nanowires of the active nanowire vertical arrangement comprises first forming an oxidation catalyst layer on the one or more bottommost nanowires.

Technical Field

Embodiments of the present disclosure are in the field of integrated circuit structures and processes, and in particular, gate all-around integrated circuit structures with a trimmed (dummy) channel structure, and methods of making gate all-around integrated circuit structures with a trimmed channel structure.

Background

Scaling of features in integrated circuits has been a driving force behind the growing semiconductor industry over the past decades. Scaling to smaller and smaller features enables increased density of functional units on the limited real estate (realate) of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated onto a chip, resulting in the production of products with increased capacity. However, it is not without problems for larger and larger capacity drives. The necessity to optimize the performance of each device becomes more and more significant.

In the fabrication of integrated circuit devices, multi-gate transistors (such as tri-gate transistors) have become more common as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred because of their lower cost and because they enable less complex tri-gate fabrication processes. On the other hand, as microelectronic device dimensions shrink below 10 nanometer (nm) nodes, maintaining mobility improvements and short channel control provides challenges in device fabrication. Nanowires used to fabricate devices provide improved short channel control.

However, scaling down multiple gate and nanowire transistors is not without consequence. As the size of these basic building blocks of microelectronic circuitry has decreased, and as the absolute number of basic building blocks fabricated in a given area has increased, the constraints on the photolithographic process used to pattern these building blocks have become overwhelming. In particular, there may be a tradeoff between the minimum size of features patterned in a semiconductor stack (critical dimension) and the spacing between such features.

Drawings

Fig. 1 illustrates a cross-sectional view of a gate all-around integrated circuit structure having a trimmed channel structure.

Figure 2 illustrates a cross-sectional view showing another gate all-around integrated circuit structure with a trimmed channel structure.

Figure 3 illustrates cross-sectional views representing various operations in a method of fabricating a gate all-around integrated circuit structure with a trimmed channel structure, according to an embodiment of the disclosure.

Fig. 4A-4J illustrate cross-sectional views of various operations in a method of fabricating a gate all-around integrated circuit structure, according to an embodiment of the present disclosure.

Fig. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure.

Fig. 6 illustrates a cross-sectional view taken through a nanowire and a fin for a non-end cap architecture (left-hand (a)) versus a self-aligned gate-extreme cap (SAGE) architecture (right-hand (b)), according to an embodiment of the present disclosure.

Figure 7 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate terminal cap (SAGE) structure with a gate all-around device, according to an embodiment of the disclosure.

Figure 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.

Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of figure 8A, as taken along the a-a' axis, in accordance with an embodiment of the present disclosure.

Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of figure 8A, as taken along the b-b' axis, in accordance with an embodiment of the present disclosure.

Fig. 9A-9E illustrate three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin/nanowire structure, in accordance with an embodiment of the present disclosure.

FIG. 10 illustrates a computing device according to one implementation of an embodiment of the disclosure.

Fig. 11 illustrates an interposer (interposer) including one or more embodiments of the present disclosure.

Detailed Description

A gate all-around integrated circuit structure having a trimmed channel structure and a method of fabricating a gate all-around integrated circuit structure having a trimmed channel structure are described. In the following description, numerous specific details are set forth, such as specific integration and material systems (material regions), in order to provide a thorough understanding of embodiments of the present disclosure. ‎ it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring embodiments of the disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus is not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and/or position of portions of the component within a consistent but arbitrary frame of reference which is set forth by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may relate to front-end (FEO L) semiconductor processing and structures FEO L is the first part of Integrated Circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer FEO L generally covers every process thing up to (but not including) the deposition of a metal interconnect layer the result, following the final FEO L operation, is typically a wafer with isolated transistors (e.g., without any leads).

Embodiments described herein may relate to back end of line (BEO L) semiconductor processing and structures BEO L is the second part of IC fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected by wiring (e.g., one or more metallization layers) on the wafer BEO L includes contact points, insulating layers (dielectrics), metal levels, and bond sites for chip-to-package connections in the BEO L portion of the fabrication stage, contact points (pads), interconnect wires, vias, and dielectric structures are formed.

The embodiments described below may be applicable to FEO L processing and structures, BEO L processing and structures, or both FEO L and BEO L processing and structures.

One or more embodiments described herein relate to self-aligned bottom-up oxidation for nanowire transistor channel clipping and nanoribbon transistor channel clipping.

To provide context, the integration of nanowire and/or nanoribbon Complementary Metal Oxide Semiconductor (CMOS) transistors faces the challenge of producing devices with different strengths. In current FinFET technology, device robustness granularity is achieved by varying the number of fins in the device channel. Unfortunately, this option is not easily used for nanowire and nanoribbon architectures because the channels are vertically stacked. This requirement is more pertinent for nanowire and/or nanoribbon (NW/NR) structures in self-aligned stacked CMOS structures where the NMOS and PMOS channels are patterned with the same width (punishing). Previous attempts to solve the above problems have included: (1) integration of NW/NR devices with different channel widths (only an option available for nanoribbons requiring complex patterning); or (2) subtractive removal of leads/strips from source/drain or channel regions (challenging options for stacked CMOS architectures).

To provide additional context, transistors with different drive currents may be required for different circuit types. Embodiments disclosed herein relate to achieving different drive currents by cutting down the number of nanowire transistor channels (de-pop) in a device structure. One or more embodiments provide a way to eliminate a discrete number of leads from a transistor structure. The approach may be suitable for both ribbon and wire (RAW). Furthermore, for proper circuit function, transistor leakage current through the sub-fins must be controlled. Embodiments disclosed herein provide a method for sub-fin isolation for nanowire transistors. For the reduction, the technique using finfets can reduce the number of fins in each device to achieve different drive current strengths. For sub-fin isolation, a sub-fin implant is used to dope the sub-fins to reduce leakage. However, since the nanowires are stacked and self-aligned, the nanowires cannot be trimmed in the same manner as fins (de-capped). In addition, the sub-fin dopants must be targeted and capable of back-diffusing into the channel, degrading carrier transport.

In accordance with embodiments of the present disclosure, a process flow for achieving self-aligned bottom-up oxidation nanowire transistor channel clipping and/or sub-fin isolation is described herein. Embodiments may include channel clipping of nanowire transistors to provide modulation of drive current in different devices as may be required for different circuits. Embodiments may be implemented as a self-aligned approach that allows depth scaling for future nanowire technologies.

In accordance with embodiments of the present disclosure, nanowire processing of alternating Si/SiGe stacks includes patterning the stack into the fin₂O₃) Deposited on the NW/NR channel. In a particular embodiment, a masking film, such as a Carbon Hard Mask (CHM), is then deposited to fill the gate trench, which is followed by a recess etch to convert the CHM overlying the strips to oxide. A selective wet etchant (such as a dilute hydrogen fluoride or ammonium hydroxide-peroxide solution) is then used to remove the oxidation catalyst layer from the exposed strip. The hard mask is then subsequently removed by exposing the hard mask to an oxygen plasma to oxidize the catalyst layer (e.g., Al)₂O₃) Only the bottom most one or more NW/NR channels are encapsulated. The bottom-most one or more NW/NR channels are then selectively converted to oxide (e.g., silicon oxide oxidized from the silicon NW/NR channels) by subjecting them to a wet oxidation anneal. Due to oxidation of the catalyst layer (e.g. Al)₂O₃) Promotes oxygen diffusion into silicon (Si), so that the bottom-most NW/NR channel or channels are rapidly converted to oxide (e.g., SiO)₂). The oxidation conditions selected may be so mild that little oxidation occurs on the upper zone not encapsulated by the oxidation catalyst layer. In this way, the Si nanowires are oxidized from bottom to top. Although some embodiments describe the use of Si (wire or strip) and SiGe (sacrificial) layers, other pairs of semiconductor materials (e.g., InAs and InGaAs, or Si) that can be alloyed and epitaxially grownGe and Ge) can be implemented to implement the various embodiments herein. Embodiments described herein enable the fabrication of self-aligned stacked transistors with a variable number of active nanowires or nanoribbons in the channel and methods of implementing such structures.

As a comparison of channel clipping involving source or drain structure adjustment (tune), fig. 1 illustrates cross-sectional views (gate-on-fin profile and fin-on-gate profile) representing a gate all-around integrated circuit structure with a clipped channel structure.

Referring to fig. 1, a CMOS integrated circuit structure 100 is formed over a substrate 102 and includes a lower PMOS region and an upper NMOS region. The lower PMOS region includes stacked nanoribbons 104A, 104B, 104C, and 104D. A P-type source or drain structure 106 is adjacent to the stacked nanoribbons and over the insulating structure 108. The lower gate structure includes a gate dielectric layer 110 having a P-type gate electrode 112 thereon. The upper NMOS region includes stacked nanoribbons 114A, 114B, 114C, and 114D. An N-type source or drain structure 116 is adjacent to the stacked nanoribbons and over the insulating structure 118. The upper gate structure includes a gate dielectric layer 120 having an N-type gate electrode 122 thereon. The spacers 124 may be adjacent to the uppermost portion of the upper gate structure.

Referring again to fig. 1, all (e.g., 4 in this case) of the upper stacked nanoribbons 114A, 114B, 114C and 114D are coupled to an N-type source or drain structure 116. However, only the upper two stacked nanoribbons 104C and 104D are coupled to the P-type source or drain structure 106, while the lower two stacked nanoribbons 104A and 104B are not coupled to the P-type source or drain structure 106. The resulting structure effectively clips two of the four channel regions of the P-type portion of the CMOS integrated circuit structure 100. However, source or drain 106 depth design is required to fabricate the CMOS integrated circuit structure 100. It is to be appreciated that while illustrative examples of four upper leads and two lower leads and effectively two clipped nanowires are depicted and described above, it is to be appreciated that all such lead counts can vary.

As a comparison of channel clipping involving channel count adjustment, fig. 2 graphically illustrates a cross-sectional view (gate-on-fin profile and fin-on-gate profile) of another gate all-around integrated circuit structure having a clipped channel structure.

Referring to fig. 2, a CMOS integrated circuit structure 200 is formed over a substrate 202 and includes a lower PMOS region and an upper NMOS region. The lower PMOS region includes stacked nanoribbons 204A and 204B over a raised substrate portion 208. A P-type source or drain structure 206 is adjacent to the stacked nanoribbons. The lower gate structure includes a gate dielectric layer 210 having a P-type gate electrode 212 thereon. The upper NMOS region includes stacked nanoribbons 214A, 214B, 214C, and 214D. An N-type source or drain structure 216 is adjacent to the stacked nanoribbons and over the insulating structure 218. The upper gate structure includes a gate dielectric layer 220 having an N-type gate electrode 222 thereon. The spacer 224 may be adjacent to an uppermost portion of the upper gate structure.

Referring again to fig. 2, all of the upper stacked nanoribbons 214A, 214B, 214C and 214D (e.g., 4 in this case) are coupled to an N-type source or drain structure 216. Likewise, both nanoribbons 204A and 204B are coupled to a P-type source or drain structure 206. However, the lower structure includes only two stacked nanoribbons 104A and 104B. The resulting structure effectively clips two of the four channel regions of the P-type portion of the CMOS integrated circuit structure 200. However, a channel count design is required to fabricate the CMOS integrated circuit structure 200. It is to be appreciated that while illustrative examples of four upper leads and two lower leads and effectively two clipped nanowires are depicted and described above, it is to be appreciated that all such lead counts can vary.

As an example of bottom-up oxidation for channel clipping, fig. 3 illustrates cross-sectional views representing various operations in a method of fabricating a gate all-around integrated circuit structure with a clipped channel structure, in accordance with an embodiment of the present disclosure.

Referring to part (a) of fig. 3, a method of fabricating an integrated circuit structure includes forming a vertical arrangement 300 of active nanowires or nanoribbons over a substrate. For example, the lower set of nanowires 304A, 304B, 304C, and 304D and the upper set of nanowires 314A, 314B, 314C, and 314D are provided as vertical stacks. As explained in more detail in other embodiments described below, the channel regions of the lower set of nanowires 304A, 304B, 304C, and 304D and the upper set of nanowires 314A, 314B, 314C, and 314D may be exposed during a replacement gate process during which an open trench 303, such as an open trench formed in a dielectric layer or within a dielectric spacer (either scenario represented as 302).

Referring to part (B) of fig. 3, an oxidation catalyst layer 330 is formed on the lower set of nanowires 304A, 304B, 304C, and 304D and the upper set of nanowires 314A, 314B, 314C, and 314D. In one embodiment, as depicted, oxidation catalyst layer 330 is further formed along the surface of trench 302. In one embodiment, oxidation catalyst layer 330 is or includes alumina. In another embodiment, oxidation catalyst layer 330 is or includes lanthanum oxide.

Referring to part (c) of fig. 3, the oxidation catalyst layer 330 is patterned to constrain the oxidation catalyst layer 330 to only those nanowires selected for channel clipping. In an embodiment, a hard mask layer 332 (such as a carbon-based hard mask layer) is formed in the trench 303 on the oxidation catalyst layer 330. The hardmask layer 332 is then recessed to a level slightly above the uppermost nanowire selected for oxidation. Then, portions of the oxidation catalyst layer 330 not covered by the recessed hard mask layer 332 are removed to form oxidation catalyst portions 334.

Referring to part (d) of fig. 3, the hard mask layer 332 is removed. Then, an oxidation process is performed. In an embodiment, the oxidation process is a process that is capable of oxidizing silicon but oxidizes silicon at a rate that is substantially increased by the presence of the oxidation catalyst portion 334. In one such embodiment, the oxidation process is enhanced to rapidly oxidize nanowires 304A and 304B to form oxidized nanowires 350A and 350B, respectively, without oxidizing (or only minimally oxidizing) nanowires 304C, 304D, 314A, 314B, 314C, and 314D. In an embodiment, the oxidation process involves a wet oxidation anneal (e.g., heating the structure in the presence of water or water vapor). This approach can effectively enable oxidation of one or more bottommost nanowires of the vertical arrangement of active nanowires without oxidizing one or more uppermost nanowires of the vertical arrangement of active nanowires.

It is to be appreciated that while on portion (d) of fig. 3, six upper nanowires are selected to remain active and two lower nanowires are selected for oxidation, any suitable number of upper active nanowires can be retained while one or more lower nanowires are oxidized to form oxidized nanowires.

It is also to be appreciated that subsequent to the processing described in association with part (d) of fig. 3, a permanent gate structure may be prepared in the trench 303. In one exemplary embodiment, the permanent gate structure includes a lower gate dielectric and a lower P-type gate electrode thereon, and an upper gate dielectric and an upper N-type gate electrode thereon. In another exemplary embodiment, the permanent gate structure includes a lower N-type gate electrode on a lower gate dielectric, and an upper P-type gate electrode on an upper gate dielectric. In an embodiment, a permanent gate structure is formed around all NW/NR channels (including oxidized NW/NR channels). In certain such embodiments, the oxidation catalyst layer is not removed, and the remaining portions are included in the final structure. In other embodiments, however, the oxidation catalyst layer is removed prior to the preparation of the permanent gate structure.

Referring again to section (D) of fig. 3 and the subsequent description, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a vertical arrangement of nanowires (e.g., 350A, 350B, 304C, 304D, 314A, 314B, 314C, and 314D) above a substrate. The nanowire vertical arrangement has one or more active nanowires (e.g., 304C, 304D, 314A, 314B, 314C, and 314D) above one or more oxidized nanowires (e.g., 350A and 350B). The gate stack is over the nanowire vertical arrangement and surrounds one or more oxidized nanowires (e.g., 350A and 350B).

In an embodiment, one or more oxidized nanowires (e.g., 350A and 350B) have thereon an oxidation catalyst layer 334 remaining from a bottom-up channel-clipping process as, for example, a residual layer or an artifact layer (artifact layer). In one embodiment, oxidation catalyst layer 334 comprises alumina. In another embodiment, oxidation catalyst layer 334 comprises lanthanum oxide.

In an embodiment, the integrated circuit structure comprises an epitaxial source or drain structure at an end of the vertical arrangement of nanowires. In one such embodiment, the epitaxial source or drain structure is a discrete epitaxial source or drain structure, examples of which are described below. In another such embodiment, the epitaxial source or drain structure is a non-discrete epitaxial source or drain structure, examples of which are described below. In an embodiment, the gate stack has dielectric sidewall spacers, and the epitaxial source or drain structure is an embedded epitaxial source or drain structure extending under the dielectric sidewall spacers of the gate stack, examples of which are described below.

In an embodiment, the integrated circuit structure further comprises a pair of conductive contact structures coupled to the epitaxial source or drain structures. In one such embodiment, the pair of conductive contact structures is an asymmetric pair of conductive contact structures, examples of which are described below.

In an embodiment, the nanowire is vertically arranged above the fin, an example of which is described below. In an embodiment, the gate stack includes a high-k gate dielectric layer and a metal gate electrode.

It is to be appreciated that the embodiments described herein can be implemented to prepare nanowire and/or nanoribbon structures with different numbers of active lead/ribbon channels. It is to be appreciated that embodiments described herein may relate to selective oxidation pathways that enable such structures. The embodiments described herein may be implemented to enable fabrication of nanowire/nanoribbon based CMOS architectures.

In an embodiment, to design different devices with different drive current strengths, a self-aligned clip (de-pop) flow can be patterned with photolithography so that the ribbons and leads (RAW) are only clipped from a particular device. In an embodiment, the entire wafer may be trimmed uniformly, so all devices have the same number of RAWs. It is to be appreciated that when de-pop is performed through the gate trench, some of the epitaxial (epi) source or drain (S/D) material may be oxidized from the proximate gate electrode, as opposed to performing de-pop through the S/D location.

As mentioned above, the nanowire release process may be performed by replacing the gate trench. Examples of such release processes are described below. In addition, Back End (BE) interconnect scaling, on the other hand, can lead to lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein may be implemented to enable front and back side interconnect integration for nanowire transistors. Embodiments described herein may provide a way to achieve relatively wide interconnect pitches. The result can be improved product performance and lower patterning costs. Embodiments may be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

One or more embodiments described herein relate to dual Epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric Trench Contact (TCN) depths. In an embodiment, an integrated circuit structure is prepared by forming source-drain openings of nanowire/nanoribbon transistors partially filled with SD epitaxy. The remaining portion of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to the backside interconnect level.

In an exemplary process flow, fig. 4A-4J illustrate cross-sectional views of various operations in a method of fabricating a gate all-around integrated circuit structure, according to an embodiment of the present disclosure.

Referring to fig. 4A, a method of fabricating an integrated circuit structure includes forming a starting stack 400, the starting stack 400 including alternating layers 404 of silicon germanium and 406 of silicon over a fin 402 (such as a silicon fin). The silicon layer 406 may be referred to as a silicon nanowire vertical arrangement. As depicted, protective caps 408 may be formed over alternating layers of silicon germanium 404 and silicon 406.

Referring to fig. 4B, a gate stack 410 is formed over the nanowire vertical arrangement 406. Portions of the nanowire vertical arrangement 406 are then released by removing portions of the silicon germanium layer 404 to provide a recessed silicon germanium layer 404' and a cavity 412, as depicted in fig. 4C.

It is to be appreciated that the structure of fig. 4C can be prepared to completion without first performing the deep etch and asymmetric contact point processing described below in association with fig. 4D. In either case (e.g., with or without asymmetric contact processing), in an embodiment, the fabrication process involves the use of a process scheme that provides a gate all-around integrated circuit structure with a trimmed-channel structure, an example of which is described above in association with fig. 3.

Referring to fig. 4D, upper gate spacers 414 are formed at sidewalls of the gate structure 410. A cavity spacer 416 is formed in the cavity 412 under the upper gate spacer 414. A deep trench contact etch is then performed to form trench 418 and form recessed nanowire 406'. As depicted in fig. 4E, a sacrificial material 420 is then formed in trench 418.

Referring to fig. 4F, a first epitaxial source or drain structure (e.g., left-hand feature 422) is formed at a first end of the nanowire vertical arrangement 406 ', a second epitaxial source or drain structure (e.g., right-hand feature 422) is formed at a second end of the nanowire vertical arrangement 406', an interlayer dielectric (I L D) material 424 is then formed at the side of the gate electrode 410 and adjacent to the source or drain structure 422, as depicted in fig. 4G.

Referring to fig. 4H, a replacement gate process is used to form permanent gate dielectric 428 and permanent gate electrode 426. In an embodiment, following removal of gate structure 410 and formation of permanent gate dielectric 428 and permanent gate electrode 426, recessed silicon germanium layer 404 'is removed to leave upper active nanowires or nanoribbons 406'. In an embodiment, the recessed silicon germanium layer 404' is selectively removed by a wet etch that selectively removes silicon germanium while not etching the silicon layer. The silicon germanium may be selectively etched using etching chemistries such as, for example, carboxylic acid/nitric acid/HF chemistries and citric acid/nitric acid/HF. Halide-based dry etching or plasma enhanced vapor etching may also be used to implement embodiments herein.

Referring again to fig. 4H, one or more of the bottommost nanowires or ribbons 406' are then oxidized, such as by the approach described in association with fig. 3, to form one or more oxidized nanowires or ribbons 499. Permanent gate dielectric 428 and permanent gate electrode 426 are then formed to surround nanowire or nanoribbon 406' and one or more oxidized nanowires or nanoribbons 499.

Referring to fig. 4I, I L D material 424 is then removed sacrificial material 420 is then removed from one of the source-drain locations (e.g., the right-hand side) to form trench 432, but is not removed from the other of the source-drain locations to form trench 430.

Referring to fig. 4J, a first conductive contact structure 434 is formed coupled to a first epitaxial source or drain structure (e.g., left-hand feature 422). A second conductive contact structure 436 is formed coupled to a second epitaxial source or drain structure (e.g., right-hand feature 422). Second conductive contact structure 436 is formed deeper along fin 402 than first conductive contact structure 434. In an embodiment, although not depicted in fig. 4J, the method further includes forming an exposed surface of the second conductive contact structure 436 at the bottom of the fin 402.

In an embodiment, as depicted, second conductive contact structure 436 is deeper along fin 402 than first conductive contact structure 434. In one such embodiment, as depicted, first conductive contact structure 434 is not along fin 402. In another such embodiment (not depicted), the first conductive contact structure 434 is partially along the fin 402.

In an embodiment, second conductive contact structure 436 is along the entirety of fin 402. In an embodiment (although not depicted), where the bottom of the fin 402 is exposed by a backside substrate removal process, the second conductive contact structure 436 has an exposed surface at the bottom of the fin 402.

In another aspect, to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein may be fabricated using a backside reveal fabrication approach to a front-side structure. In some exemplary embodiments, the exposure of the backside of a transistor or other device structure requires wafer-level backside processing. In contrast to conventional through-silicon via TSV-type techniques, the reveal of the backside of the transistor as described herein can be performed at the density of the device cells and even within sub-regions of the device. Furthermore, such reveal of the backside of the transistor may be performed to remove substantially all of the donor substrate (during front-side device processing, the device layers are disposed on the donor substrate). Thus, with the thickness of the semiconductor in the device cell after the exposure of the backside of the transistor potentially being only tens or hundreds of nanometers, micron-scale deep TSVs become unnecessary.

The reveal techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where "center" is any layer employed in front-side fabrication, revealed from the back-side, and again employed in back-side fabrication. Processing of both the frontside of the device structure and the exposed backside may address many of the challenges associated with fabricating 3D ICs when relying primarily on frontside processing.

Approaches to reveal the backside of the transistor may be employed, for example, to remove at least a portion of the carrier layer and intervening layers of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the charge carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and/or wet/dry etching process known to be suitable for the composition of the carrier layer may be employed. For example, where the carrier layer is a group IV semiconductor (e.g., silicon), known CMP slurries suitable for thinning the semiconductor may be employed. Likewise, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors may also be employed.

For example, where the carrier layer is 400-900 μm in thickness, 100-700 μm may be severed by practicing any blanket implant (blanket implant) known to promote wafer level fracture.

Subsequently, exposure of the intervening layer is detected. A time is detected for identifying that the backside surface of the donor substrate has advanced to almost the device layer. Any end-point detection technique known to be suitable for detecting transitions between materials employed for the charge carrier layer and the intervening layers may be practiced. In some embodiments, the one or more endpoint criteria are based on detecting a change in light absorption or emission of the backside surface of the donor substrate during the performed polishing or etching. In some other embodiments, the endpoint criterion is associated with a change in light absorption or emission by-products during polishing or etching of the donor substrate backside surface. For example, the absorption or emission wavelengths associated with the carrier layer etch byproducts may vary depending on the different compositions of the carrier layer and intervening layers. In other embodiments, the endpoint criterion is associated with a change in the quality of a substance in a byproduct of polishing or etching the backside surface of the donor substrate. For example, the byproducts of the process may be sampled by a quadrupole mass analyzer (quadrupole mass analyzer), and the change in mass of the species may be related to the different compositions of the charge carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criterion is associated with a change in friction between the backside surface of the donor substrate and a polished surface in contact with the backside surface of the donor substrate.

In the case where the removal process is selective to the carrier layer relative to the intervening layer, detection of the intervening layer may be enhanced because non-uniformities in the carrier removal process may be mitigated by the etch rate between the carrier layer and the intervening layer. Detection may even be skipped if the grinding, polishing, and/or etching operations remove the intervening layer at a rate that is sufficiently lower than the rate at which the carrier layer is removed. If endpoint criteria are not employed, a predetermined fixed duration grinding, polishing, and/or etching operation may be stopped on the intervening layer material if the intervening layer is thick enough to satisfy the etch selectivity. In some examples, the carrier etch rate: the intervening layer etch rate is 3:1 to 10:1 or greater.

Upon exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layers may be removed. For example, a thickness of the intervening layer may be uniformly removed by polishing. Alternatively, a masking or blanket etch process may be utilized to remove a thickness of the intervening layer. The process may employ the same polishing or etching process as employed to thin the carriers, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that facilitates removal of the intervening layer as compared to removal of the device layer. Where intervening layer thicknesses of less than a few hundred nanometers are to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than the removal process employed for removal of the charge carrier layer. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between the semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) that surrounds the device layer and is embedded within the intervening layer, e.g., as an electrical spacer between adjacent device regions.

For embodiments in which the device layer is revealed by complete removal of the intervening layer, backside processing may begin on the exposed backside of the device layer or specific device regions therein. In some embodiments, backside device layer processing includes additional polishing or wet/dry etching through a thickness of the device layer disposed between the intervening layer and a device region (such as a source or drain region) previously fabricated in the device layer.

In some embodiments in which wet and/or plasma etching is utilized to recess the carrier layer, intervening layer, or device layer backside, such etching may be a patterned etch that imparts significant non-planarity or topography (topographies) into the device layer backside surface or an etch that is selective in material. As described further below, the patterning may be performed within the device cell (i.e., "intra-cell" patterning) or may be performed across the device cell (i.e., "inter-cell" patterning). In some patterned etch embodiments, the at least partially thick intervening layer serves as a hard mask for backside device layer patterning. Thus, the masked etch process may serve as the beginning of the etch of the device layer corresponding to the mask.

The processing schemes described above may result in a donor-host substrate assembly that includes an IC device that exposes a backside of an intervening layer, a backside of a device layer, and/or a backside, and/or front-side metallization of one or more semiconductor regions within the device layer. Additional backside processing of any of these revealed regions may then be performed during downstream processing.

It is to be appreciated that the structures resulting from the above exemplary processing schemes may be used in the same or similar fashion for subsequent processing operations to complete device fabrication (such as CMOS, PMOS, and/or NMOS device fabrication). As an example of a completed device, fig. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along gate lines, in accordance with an embodiment of the present disclosure.

Referring to fig. 5, a semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In an embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (such as nanowires 504A and 504B) above sub-fin region 505, as represented by the dashed lines. In either case, to facilitate the description of the nonplanar integrated circuit structure 500, the nonplanar active regions 504 are referred to hereinafter as protruding fin portions. In an embodiment, the fabrication process involves the use of a process scheme that provides the active region 504 as a trimmed channel structure, an example of which is described above in association with fig. 3. For example, in one embodiment, the lower nanowire 504B is an oxidized nanowire and the upper nanowire 504A is an active nanowire. In one embodiment, the lower oxidized nanowire 504B includes an oxidation catalyst layer thereon.

Gate line 508 is disposed over protruding portion 504 of the nonplanar active area (including surrounding nanowires 504A and 504B, if applicable) and over a portion of trench isolation region 506. As shown, gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate line 508 may also include a dielectric cap layer 554. Also seen from this perspective are gate contact 514 and overlying gate contact via 516, along with overlying metal interconnect 560, all disposed in an interlayer dielectric stack or layer 570. As also seen from the perspective view of fig. 5, in one embodiment, gate contact 514 is disposed over trench isolation region 506 rather than over the nonplanar active region.

In an embodiment, the semiconductor structure or device 500 is a non-planar device (such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device). In such embodiments, the corresponding semiconductor-type channel region is comprised of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate line 508 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

As also depicted in fig. 5, in an embodiment, an interface 580 is present between the protruding fin portion 504 and the sub-fin region 505. The interface 580 can be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is about 10 nanometers wide or less, and the sub-fin dopants are supplied from the solid-state doped layer adjacent at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

Although not depicted in fig. 5, it is to be appreciated that the source or drain regions of the protruding fin portions 504 or adjacent to the protruding fin portions 504 are on either side of the gate line 508 (i.e., into and out of the page). In one embodiment, the source or drain regions are doped portions of the original material of the protruding fin portion 504. In another embodiment, the material of the protruding fin portions 504 is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form discrete epitaxial bumps (nub) or non-discrete epitaxial structures. In either embodiment, the source or drain region may extend below the height of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to embodiments of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below the interface 580) inhibits source-to-drain leakage through that portion of the bulk semiconductor fin. In an embodiment, the source and drain structures are N-type epitaxial source and drain structures, both of which include phosphorus dopant impurity atoms. In accordance with one or more embodiments of the present disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as described above in association with fig. 4J.

Referring again to fig. 5, in an embodiment, fin 504/505 (and possibly nanowires 504A and 504B) is comprised of a crystalline silicon, silicon/germanium, or germanium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, fin 504/505 is composed of a group III-V material (such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof). The trench isolation region 506 may be comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

The gate line 508 may be composed of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In an embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Further, a portion of the gate dielectric layer may include a native oxide layer formed from the top few layers of the protruding fin portion 504. In an embodiment, the gate dielectric layer is comprised of a top high-k portion and a lower portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure that includes a bottom portion that is substantially parallel to a surface of the substrate and two sidewall portions that are substantially perpendicular to a top surface of the substrate.

In one embodiment, the gate electrode is composed of a metal layer (such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide). In a specific embodiment, the gate electrode is comprised of a non-workfunction setting fill material formed above the metal workfunction setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal depending on whether the transistor is to be a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be comprised of a stack of two or more metal layers, where one or more of the metal layers is a work function metal layer and at least one of the metal layers is a conductive fill layer. For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). An N-type metal layer would enable the formation of an NMOS gate electrode with a workfunction between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode can be comprised of a "U" shaped structure that includes a bottom portion that is substantially parallel to a surface of the substrate and two sidewall portions that are substantially perpendicular to a top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may be simply a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

The spacers associated with the gate electrode stack may be comprised of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact 514 and overlying gate contact via 516 can be comprised of a conductive material. In an embodiment, one or more of the contact points or vias are comprised of a metallic substance. The metal species may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 508, while precluding the use of a lithography step with an extremely tight registration budget. In an embodiment, the contact point pattern is a vertically asymmetric contact point pattern such as described in association with fig. 4J. In other embodiments, all contact points are front-side connected and not asymmetrical. In one such embodiment, the self-aligned approach enables the use of an inherently highly selective wet etch (e.g., as opposed to conventionally implemented dry or plasma etches) to generate the contact point openings. In an embodiment, the contact pattern is formed by using an existing gate pattern in conjunction with a contact plug (contact plug) photolithography operation. In one such embodiment, the approach can eliminate the need for otherwise critical lithographic operations to generate contact patterns as used in conventional approaches. In an embodiment, the trench contact grid (grid) is not patterned separately, but instead is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cutting.

In an embodiment, providing the structure 500 involves preparing the gate stack structure 508 by a replacement gate process. In such schemes, the dummy gate material (such as polysilicon or silicon nitride pillar material) may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to proceeding from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or a wet etch process. In one embodiment, the dummy gate is comprised of polysilicon or amorphous silicon, and utilizing includes using SF₆Is removed by a dry etching process. In another embodiment, the dummy gate is comprised of polysilicon or amorphous silicon, and the utilizing includes using NH₄A wet etching process of OH aqueous solution or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch comprising an aqueous solution of phosphoric acid.

Referring again to fig. 5, the arrangement of the semiconductor structure or device 500 places the gate contact over the isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed over the active area (e.g., over the sub-fin 505) and in the same layer as the trench contact via.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of the embodiments of the present disclosure. Also, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or the like. For example, in an embodiment, the semiconductor device is a Metal Oxide Semiconductor (MOS) transistor for logic or memory or a bipolar transistor. Also, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate all-around (GAA) device, a tri-gate device, an independently-accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10 nm) technology nodes.

In an embodiment, as used throughout this description, an interlayer dielectric (I L D) material is composed of or includes a layer of dielectric material or insulating material₂) Silicon doped oxide, silicon fluorinated oxide, silicon carbon doped oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or by other deposition methods.

In embodiments, as also used throughout this description, metal lines or interconnect line materials (and via materials) are composed of one or more metals or other conductive structures a common example is a structure that uses copper lines and a barrier (barrier) layer that may or may not include copper and the surrounding I L D material as used herein, the term metal includes alloys, stacks, and other combinations of metals.

In an embodiment, as also used throughout this description, the hard mask material, the capping layer, or the plug is comprised of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials may be used in different regions in order to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap or plug layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer or both or a combination thereof. Other suitable materials may include carbon-based materials. Other hard mask, capping, or plug layers known in the art may be used depending on the particular implementation. The hard mask, cap or plug layer may be formed by CVD, PVD or by other deposition methods.

In an embodiment, as also used throughout this description, the lithographic operation is performed using 193nm immersion lithography (i 193), EUV and/or EBDW lithography, or the like. Either positive or negative resists may be used. In one embodiment, the photolithographic mask is a tri-layer mask consisting of a profile masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a Carbon Hard Mask (CHM) layer and the antireflective coating layer is a silicon ARC layer.

In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate terminal cap (SAGE) structure. Particular embodiments may relate to the integration of multiple width (multiple Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, nanowires/nanoribbons are integrated by multiple Wsi in the SAGE architecture portion of the previous process flow. Such process flows may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next generation transistors with low power and high performance. As described in more detail below in association with fig. 9A-9E, the associated epitaxial source or drain regions may be embedded (e.g., portions of the nanowires are removed and source or drain (S/D) growth is then performed) or formed by vertical fusion (e.g., forming the epitaxial regions around existing leads).

To provide additional context, advantages of self-aligned gate-extreme cap (SAGE) architectures may include the ability to achieve higher layout densities and scaling of diffusion to diffusion spacings in particular. To provide an illustrative comparison, fig. 6 illustrates a cross-sectional view taken through the nanowire and fin for a non-end-cap architecture (left-hand (a)) versus a self-aligned gate-terminal cap (SAGE) architecture (right-hand (b)), according to an embodiment of the disclosure.

Referring to the left-hand side (a) of fig. 6, an integrated circuit structure 600 includes a substrate 602, the substrate 602 having a sub-fin 604 protruding therefrom, the sub-fin 604 being within an isolation structure 608 that laterally surrounds the sub-fin 604. Corresponding nanowires 649 and 605 are above the sub-fin 604. In one embodiment, the lower nanowire 649 is an oxide nanowire and the upper nanowire 605 is an active nanowire. In one embodiment, the lower oxidation nanowire 649 includes an oxidation catalyst layer thereon. A gate structure may be formed over the integrated circuit structure 600 to fabricate a device. However, the break in such gate structures can be adjusted by increasing the spacing between the sub-fin 604/nanowire 649/605 pairings (pairing).

In contrast, referring to the right-hand side (b) of fig. 6, integrated circuit structure 650 includes a substrate 652, the substrate 652 having a sub-fin 654 protruding therefrom, the sub-fin 654 being within an isolation structure 658 laterally surrounding the sub-fin 654. Corresponding nanowires 699 and 655 are on the sub-fin 654. In one embodiment, the lower nanowire 699 is an oxidized nanowire and the upper nanowire 655 is an active nanowire. In one embodiment, the lower oxidation nanowire 699 includes an oxidation catalyst layer thereon. An isolated SAGE wall 660 is included within isolation structure 658 and between adjacent sub-fin 654/nanowire 699/655 pairs. The distance between the isolated SAGE wall 660 and the nearest sub-fin 654/nanowire 699/655 pair defines a gate end cap spacer 662. A gate structure may be formed over the integrated circuit structure 650, between the isolated SAGE walls, to fabricate a device. The break in such gate structures is imposed by the isolated SAGE walls. Since the isolated SAGE walls 660 are self-aligned, the constraints from the conventional approach can be minimized to enable more aggressive diffusion to the diffusion gap. Further, since the gate structure includes breaks at all locations, the respective gate structure portions may be layers connected by local interconnects formed over the isolated SAGE wall 660. In the embodiment as depicted, SAGE walls 660 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion (as depicted).

In accordance with an embodiment of the present disclosure, the fabrication process for the structure associated with fig. 6 involves the use of a process scheme that provides a gate all-around integrated circuit structure with a trimmed-channel structure, an example of which is described above in association with fig. 3.

Self-aligned gate extreme cap (SAGE) processing schemes involve forming gate/trench contact end caps that are self-aligned to the fins without requiring additional length to account for mask misregistration. Thus, the embodiment can be implemented to enable the shrinkage of the transistor layout area. Embodiments described herein may relate to the preparation of gate end cap isolation structures, which may also be referred to as gate walls, isolated gate walls, or self-aligned gate end cap (SAGE) walls.

In an exemplary processing scheme for a structure with SAGE walls separating adjacent devices, FIG. 7 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate terminal cap (SAGE) structure with a gate all-around device, according to an embodiment of the present disclosure.

Referring to part (a) of fig. 7, the starting structure includes a nanowire patterned stack 704 over a substrate 702. A lithographically patterned stack 706 is formed over the nanowire patterned stack 704. Nanowire patterned stack 704 includes alternating layers 710 and 712 of silicon germanium and silicon. A protective mask 714 is between the nanowire patterned stack 704 and the lithographically patterned stack 706. In one embodiment, the lithographically patterned stack 706 is a tri-layer mask consisting of the profile masking portion 720, the anti-reflective coating (ARC) layer 722, and the photoresist layer 724. In a particular such embodiment, the profile masking portion 720 is a Carbon Hard Mask (CHM) layer and the anti-reflective coating layer 722 is a silicon ARC layer.

Referring to part (b) of fig. 7, the stack of part (a) is lithographically patterned and then etched to provide an etched structure comprising the patterned substrate 702 and the trench 730.

Referring to part (c) of fig. 7, the structure of part (b) has an isolation layer 740 and a SAGE material 742 formed in the trench 730. The structure is then planarized to leave the patterned topography masking layer 720' as an exposed upper layer.

Referring to part (d) of fig. 7, the isolation layer 740 is recessed below the upper surface of the patterned substrate 702, e.g., to define protruding fin portions and to provide a trench isolation structure 741 under the SAGE walls 742.

Referring to part (e) of fig. 7, the silicon germanium layer 710 is removed at least in the channel region to release the silicon nanowires 712A and 712B.

In accordance with an embodiment of the present disclosure, the fabrication process for the structure associated with fig. 7 involves the use of a process scheme that provides a gate all-around integrated circuit structure with a trimmed-channel structure, an example of which is described above in association with fig. 3. For example, referring to part (e) of fig. 7, in an embodiment, the nanowire 712B and the nanoribbon 712A are an active nanowire and nanoribbon, respectively. In one such embodiment, as depicted, nanowires 799B are oxidized nanowires and nanoribbons 799A are oxidized nanoribbons. In another such embodiment, the nanowires 799B are oxidized nanowires and the nanoribbons 799A are active nanoribbons. In another such embodiment, the nanowires 799B are active nanowires and the nanoribbons 799A are oxidized nanoribbons. In any case, in embodiments, the oxidation nanowires or oxidation nanoribbons each include an oxidation catalyst layer thereon.

Following formation of the structure of part (e) of fig. 7, one or more gate stacks may be formed around the active and oxide nanowires and/or nanoribbons, over the protruding fins of substrate 702, and between SAGE walls 742. In one embodiment, the remaining portions of the protective mask 714 are removed prior to forming the gate stack. In another embodiment, artifacts of the remaining portions of the protective mask 714, such as the processing scheme, are retained as insulating fin caps.

Referring again to section (e) of fig. 7, it is appreciated that a channel view is depicted in which the source or drain regions are positioned in and out of the page. In an embodiment, the channel region comprising nanowire 712B has a smaller width than the channel region comprising nanowire 712A. Thus, in an embodiment, an integrated circuit structure includes a multiple width (multiple Wsi) nanowire. While the structures of 712B and 712A may be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to herein as nanowires. It is also to be appreciated that reference or depiction of a fin/nanowire pair throughout may refer to a structure that includes a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown in fig. 7), wherein one or more bottom leads are oxidized for trimming.

Referring again to part (e) of fig. 7 and the ensuing description, in accordance with an embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of active nanowires than the second vertical arrangement of nanowires. The first and second vertical arrangements of nanowires have an uppermost nanowire that is coplanar and a lowermost nanowire that is coplanar. The nanowire second vertical arrangement has an oxidized bottommost nanowire. A first gate stack is over the nanowire first vertical arrangement. A second gate stack is over the second vertical arrangement of nanowires and surrounds the oxidized bottommost nanowire.

In an embodiment, the nanowire of the first vertical arrangement of nanowires has a horizontal width that is the same as the horizontal width of the nanowire of the second vertical arrangement of nanowires. In another embodiment, the nanowires of the first vertical arrangement of nanowires have a horizontal width that is greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires. In another embodiment, the nanowire of the first vertical arrangement of nanowires has a horizontal width that is less than the horizontal width of the nanowire of the second vertical arrangement of nanowires.

To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, fig. 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, according to an embodiment of the present disclosure. Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of figure 8A, as taken along the a-a' axis. Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of figure 8A, as taken along the b-b' axis.

Referring to fig. 8A, an integrated circuit structure 800 includes one or more vertically stacked nanowires (804 sets) over a substrate 802. For illustrative purposes, optional fins between the bottommost nanowire and the substrate 802 are not depicted for emphasis of the nanowire portions. Embodiments herein target both single-lead and multi-lead devices. As an example, three nanowire-based devices having nanowires 804A, 804B, and 804C are shown for illustrative purposes. For ease of description, nanowires 804A serve as an example, with the description focusing on one of the nanowires. It is to be appreciated that where properties of one nanowire are described, multiple nanowire-based embodiments can have the same or substantially the same properties for each of the nanowires.

Each of the nanowires 804 includes a channel region 806 in the nanowire, the channel region 806 having a length (L), see fig. 8C, the channel region also having a perimeter (Pc) orthogonal to the length (L), see both fig. 8A and 8C, the gate electrode stack 808 surrounding the entire perimeter (Pc) of each of the channel regions 806, the gate electrode stack 808 including the gate electrode along with a gate dielectric layer between the channel region 806 and the gate electrode (not shown).

In accordance with an embodiment of the present disclosure, the fabrication process for the structure associated with fig. 8A-8C involves the use of a process scheme that provides a gate all-around integrated circuit structure with a trimmed channel structure 806, an example of which is described above in association with fig. 3. For example, in one embodiment, nanowires 804A are oxidized nanowires. In another embodiment, both nanowires 804A and 804B are oxide nanowires. In one embodiment, the oxidized nanowire includes an oxidation catalyst layer thereon.

Referring to both fig. 8A and 8B, the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810/812. A pair of non-discrete source or drain regions 810/812 are on either side of the channel region 806 of the plurality of vertically stacked nanowires 804. Further, the pair of non-discrete source or drain regions 810/812 abut the channel regions 806 of the plurality of vertically stacked nanowires 804. In one such embodiment, not depicted, the pair of non-discrete source or drain regions 810/812 is directly vertically contiguous with the channel region 806 because the epitaxial growth is on and between portions of the nanowire extending beyond the channel region 806, with the ends of the nanowire shown within the source or drain structure. In another embodiment, as depicted in fig. 8A, the pair of non-discrete source or drain regions 810/812 is indirectly vertically contiguous with the channel region 806 because the channel region 806 is formed at the ends of the nanowires, rather than between the nanowires.

In an embodiment, as depicted, the source or drain regions 810/812 are non-discrete because there is no separate and discrete source or drain region for each channel region 806 of the nanowire 804. Thus, in embodiments having a plurality of nanowires 804, the nanowire's source or drain region 810/812 is a global or uniform source or drain region, rather than discrete for each nanowire. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel region 806, as depicted in fig. 8B, each of the pair of non-discrete source or drain regions 810/812 is generally rectangular in shape with a bottom tapered portion and a top apex portion. However, in other embodiments, the source or drain regions 810/812 of the nanowires are relatively large, yet discrete, non-vertically merged epitaxial structures (such as the bumps described in association with fig. 4F-4J).

In accordance with an embodiment of the present disclosure, and as depicted in fig. 8A and 8B, the integrated circuit structure 800 further includes a pair of contact points 814, each contact point 814 being on one of a pair of non-discrete source or drain regions 810/812. In one such embodiment, each contact 814 completely surrounds a respective non-discrete source or drain region 810/812 in a vertical sense. On the other hand, as depicted in fig. 8B, the entire perimeter of the non-discrete source or drain region 810/812 may not be available for contact with the contact point 814, and thus, the contact point 814 only partially surrounds the non-discrete source or drain region 810/812. In a control embodiment not depicted, the entire perimeter of the non-discrete source or drain region 810/812, as taken along the a-a' axis, is surrounded by contact points 814. According to an embodiment of the present disclosure (although not depicted), the pair of contact points 814 is an asymmetric pair of contact points, as described in association with fig. 4J.

Referring to fig. 8B and 8C, the non-discrete source or drain region 810/812 is global in the sense that a single unified feature serves as a source or drain region for multiple (in this case, 3) nanowires 804 and, more particularly, for more than one discrete channel region 806. In an embodiment, the pair of non-discrete source or drain regions 810/812 is composed of a different semiconductor material than the semiconductor material of the discrete channel regions 806, e.g., the pair of non-discrete source or drain regions 810/812 is composed of silicon germanium and the discrete channel regions 806 is composed of silicon. In another embodiment, the pair of non-discrete source or drain regions 810/812 are composed of the same or substantially the same semiconductor material as the discrete channel region 806, e.g., both the pair of non-discrete source or drain regions 810/812 and the discrete channel region 806 are composed of silicon.

Referring again to fig. 8A, in an embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As depicted, the outer portions of the pair of spacers 816 can overlap portions of the non-discrete source or drain region 810/812, providing an "embedded" portion of the non-discrete source or drain region 810/812 beneath the pair of spacers 816. As also depicted, the embedded portion of the non-discrete source or drain regions 810/812 may not extend under the entirety of the pair of spacers 816.

The substrate 802 may be comprised of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 802 comprises a lower bulk substrate composed of a single crystal of material that may include, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. An upper insulator layer composed of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride on the lower bulk substrate. Thus, the structure 800 may be prepared from a starting semiconductor-on-insulator substrate. Alternatively, structure 800 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion in place of the upper insulator layer described above. In another alternative embodiment, the structure 800 is formed directly from a bulk substrate and doping is used to form electrically isolated active regions (such as nanowires) thereon. In one such embodiment, the first nanowire (i.e., proximate the substrate) is in the form of an omega-FET type structure.

In embodiments, the nanowires 804 can be sized as leads or ribbons, and can have square or rounded corners, as described below. In an embodiment, the nanowires 804 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowire is a single crystal. For example, for silicon nanowires 804, single crystal nanowires can be based on a (100) global orientation (e.g., employing a <100> plane in the z-direction). Other orientations are also contemplated, as described below. In an embodiment, the dimensions of the nanowire 804 are in the nanometer scale from a cross-sectional perspective. For example, in a particular embodiment, the smallest dimension of the nanowire 804 is less than about 20 nanometers. In an embodiment, the nanowire 804 is composed of a strained material, particularly in the channel region 806.

Referring to fig. 8C, in an embodiment, each of the channel regions 806 has a width (Wc) and a height (Hc), the width (Wc) and the height (Hc) being about the same. That is, in both cases, the channel region 806 is square or rounded in cross-sectional profile (if the corners are rounded). In another aspect, the width and height of the channel region need not be the same, such as for the case of nanoribbons as described throughout.

In another aspect, a method of fabricating a nanowire portion of a fin/nanowire integrated circuit structure is provided. For example, fig. 9A-9E illustrate three-dimensional cross-sectional views representing various operations in a method of fabricating a nanowire portion of a fin/nanowire structure, in accordance with an embodiment of the present disclosure.

A method of making a nanowire integrated circuit structure can include forming a nanowire over a substrate. In a specific example illustrating the formation of two silicon nanowires, fig. 9A illustrates a substrate 902 (e.g., consisting of a bulk substrate silicon substrate 902A with an insulating silicon dioxide layer 902B thereon), the substrate 902 having a silicon layer 904/silicon germanium layer 906/silicon layer 908 stack thereon. It is to be understood that in another embodiment, a silicon germanium layer/silicon germanium layer stack may be used to ultimately form two silicon germanium nanowires.

Referring to fig. 9B, a portion of the silicon layer 904/silicon germanium layer 906/silicon layer 908 stack and a top portion of silicon dioxide layer 902B are patterned into a fin structure 910, for example, using a mask and plasma etch process. It is to be appreciated that the etch for fig. 9B is shown as forming two silicon nanowire precursor portions for illustrative purposes. While the etch is shown as terminating within the bottom isolation layer for ease of illustration, more complex stacks are contemplated within the context of embodiments of the present disclosure. For example, as described in association with fig. 7, the process may be applied to a nanowire/fin stack.

The method can also include forming a channel region in the nanowire, the channel region having a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over two silicon nanowires, fig. 9C illustrates a fin structure 910 with three sacrificial gates 912A, 912B, and 912C thereon. In one such embodiment, the three sacrificial gates 912A, 912B and 912C are composed of a sacrificial gate oxide layer 914 and a sacrificial polysilicon gate layer 916, the sacrificial gate oxide layer 914 and the sacrificial polysilicon gate layer 916 being blanket deposited and patterned with a plasma etch process.

Following patterning to form the three sacrificial gates 912A, 912B, and 912C, spacers may be formed on sidewalls of the three sacrificial gates 912A, 912B, and 912C, doping (e.g., tip and/or source and drain type doping) may be performed, and an interlayer dielectric layer may be formed to cover the three sacrificial gates 912A, 912B, and 912C. The interlayer dielectric layer may be polished to expose the three sacrificial gates 912A, 912B and 912C for gate replacement or gate last processing.

Referring to fig. 9D, three sacrificial gates 912A, 912B, and 912C are removed such that a portion of spacer 918 and interlayer dielectric layer 920 remains. In addition, portions of silicon germanium layer 906 and portions of insulating silicon dioxide layer 902B of fin structure 910 are removed in the areas previously covered by three sacrificial gates 912A, 912B and 912C. As depicted in fig. 9D, discrete portions of silicon layers 904 and 908 thus remain.

In one embodiment, the discrete portions of silicon layers 904 and 908 shown in fig. 9D will eventually become channel regions in the nanowire-based device. Thus, at the stage of the process depicted in fig. 9D, channel design or tuning may be performed. For example, in one embodiment, the discrete portions of silicon layers 904 and 908 shown in fig. 9D are thinned using an oxidation and etching process. Such an etching process may be performed while the wires are separated by etching silicon germanium layer 906. Thus, the initial leads formed from silicon layers 904 and 908 are initially thicker and thinned to a size suitable for the channel region in the nanowire device, regardless of the size setting of the source and drain regions of the device. Thus, in an embodiment, forming the channel region includes removing a portion of the nanowire, and the resulting source and drain region perimeters (described below) are greater than the resulting channel region perimeters.

In accordance with an embodiment of the present disclosure, following the removal of three sacrificial gates 912A, 912B and 912C from the area originally covered by three sacrificial gates 912A, 912B and 912C and the removal of portions of silicon germanium layer 906 and portions of insulating silicon dioxide layer 902B of fin structure 910, a fabrication process is performed that provides a gate all-around integrated circuit structure with a trimmed channel structure, an example of which is described above in association with fig. 3. For example, in one embodiment, nanowires 904 are oxidized nanowires in the channel region. In one embodiment, the oxidized nanowire includes an oxidation catalyst layer thereon.

The method may further include forming a gate electrode stack around an entire perimeter of the channel region. In a specific example showing the formation of three gate structures over two silicon nanowires, fig. 9E illustrates the structure after subsequent deposition of a gate dielectric layer 922 (such as a high-k gate dielectric layer) and a gate electrode layer 924 (such as a metal gate electrode layer) in between spacers 918 and subsequent polishing. That is, the gate structure is formed in the trench 921 of fig. 9D. In addition, fig. 9E depicts the result of subsequent removal of the interlayer dielectric layer 920 after forming the permanent gate stack. Portions of silicon germanium layer 906 and portions of insulating silicon dioxide layer 902B of fin structure 910 are also removed in areas previously covered by portions of interlayer dielectric layer 920 depicted in fig. 9D. As depicted in fig. 9E, discrete portions of silicon layers 904 and 908 thus remain.

The method may further include forming a pair of source and drain regions in the nanowire on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to a length of the channel region. Specifically, in one embodiment, the discrete portions of silicon layers 904 and 908 shown in fig. 9E will eventually become at least part of the source and drain regions in the nanowire-based device. In one such embodiment, an epitaxial source or drain structure is formed by fusing epitaxial material around existing nanowires 904 and 908. In another embodiment, the epitaxial source or drain structures are embedded, e.g., portions of nanowires 904 and 908 are removed, and then source or drain (S/D) growth is performed. In the latter case, such epitaxial source or drain structures may be non-discrete as illustrated in association with fig. 8A and 8B, or may be discrete as illustrated in association with fig. 4J, in accordance with embodiments of the present disclosure. In either case, in one embodiment, the source or drain structure is an N-type epitaxial source or drain structure, both of which include phosphorus dopant impurity atoms.

The method may then include forming a pair of contacts, a first one of the pair of contacts completely or almost completely surrounding a perimeter of the source region and a second one of the pair of contacts completely or almost completely surrounding a perimeter of the drain region in embodiments such as described in association with FIG. 4J, the pair of contacts are an asymmetric pair of source and drain contact structures in other embodiments the pair of contacts are a symmetric pair of source and drain contact structures in particular, following epitaxial growth, the contacts are formed in trenches 925 of FIG. 9E.

In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device (such as, but not limited to, a finFET or a tri-gate device) with a corresponding one or more overlying nanowire structures. In such embodiments, the corresponding semiconductor-type channel region is comprised of or formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In one such embodiment, the gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

In embodiments, as described throughout, the substrate may be composed of a semiconductor material that is capable of withstanding the fabrication process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate comprised of a crystalline silicon, silicon/germanium or germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron or combinations thereof) to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a distinct crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron doped silicon single crystal substrate). The bulk substrate may alternatively be composed of a III-V material. In an embodiment, the bulk substrate is composed of a III-V material (such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof). In one embodiment, the bulk substrate is composed of a III-V material and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

In an embodiment, as described throughout, the trench isolation layer may be comprised of a material suitable to ultimately electrically isolate or facilitate isolation of portions of the permanent gate structure from the underlying bulk substrate or to isolate active regions formed within the underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the trench isolation layer is comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

In embodiments, as described throughout, the self-aligned gate terminal cap isolation structure may be comprised of one or more materials suitable to ultimately electrically isolate or facilitate isolation of portions of the permanent gate structure from each other. Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multi-layer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material, such as hafnium oxide.

Embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories may be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in a computer system (e.g., desktop computer, laptop computer, server), cellular telephone, personal electronic device, and so forth. The integrated circuit may be coupled to a bus or other component in the system. For example, the processor may be coupled to the memory, chipset, and so on by one or more buses. Each of the processors, memories, and chipsets can potentially be manufactured using the approaches disclosed herein.

FIG. 10 illustrates a computing device 1000 according to one implementation of an embodiment of the disclosure. The computing device 1000 houses a board 1002. The board 1002 may include a plurality of components including, but not limited to, a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations, at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In further implementations, the communication chip 1006 is part of the processor 1004.

Depending on its application, computing device 1000 may include other components that may or may not be physically and electrically coupled to board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a Compact Disc (CD), a Digital Versatile Disc (DVD), and so forth).

The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long term evolution (L TE), Ev-DO, HSPA +, HSDPA +, UPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and higher.

The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures (such as a gate all-around integrated circuit structure with a trimmed channel structure constructed in accordance with implementations of embodiments of the disclosure). The term "processor" may refer to any device or any portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. The integrated circuit die of the communication chip 1006 may include one or more structures (such as a gate all-around integrated circuit structure with a trimmed channel structure constructed in accordance with implementations of embodiments of the disclosure).

In further implementations, another component housed within the computing device 1000 may contain an integrated circuit die that includes one or more structures, such as a gate all-around integrated circuit structure with a trimmed channel structure constructed in accordance with implementations of embodiments of the present disclosure.

In various implementations, the computing device 1000 may be a laptop computer, a netbook, a notebook computer, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1000 may be any other electronic device that processes data.

Fig. 11 illustrates an interposer (interposer) 1100 including one or more embodiments of the present disclosure. Interposer 1100 is an intervening substrate used to bridge first substrate 1102 to second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. Second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer 1100 is to spread connections to a wider pitch or to reroute connections to different connections. For example, interposer 1100 may enable an integrated circuit die to be coupled to a Ball Grid Array (BGA) 1106, which in turn can be coupled to a second substrate 1104. In some embodiments, first and second substrates 1102/1104 are attached to opposite sides of interposer 1100. In other embodiments, first and second substrates 1102/1104 are attached to the same side of interposer 1100. Also, in further embodiments, three or more substrates are interconnected via interposer 1100.

Interposer 1100 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or polymeric material, such as polyimide. In further implementations, the interposer may be formed of alternative rigid or flexible materials that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 1108 and vias 1110, the vias 1110 including, but not limited to, Through Silicon Vias (TSVs) 1112. Interposer 1100 may further include embedded device 1114, embedded device 1114 including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 1100. In accordance with embodiments of the present disclosure, the devices or processes disclosed herein may be used in the preparation of interposer 1100 or in the preparation of components included in interposer 1100.

Thus, embodiments of the present disclosure include a gate all-around integrated circuit structure having a trimmed channel structure and a method of fabricating a gate all-around integrated circuit structure having a trimmed channel structure.

The foregoing description of illustrated implementations of embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1: an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The nanowire vertical arrangement has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and surrounds the one or more oxidized nanowires.

Example embodiment 2: the integrated circuit structure of example embodiment 1, wherein the one or more oxidized nanowires have an oxidation catalyst layer thereon.

Example embodiment 3: the integrated circuit structure of example embodiment 2, wherein the oxidation catalyst layer comprises alumina.

Example embodiment 4: the integrated circuit structure of example embodiments 1, 2, or 3, further comprising an epitaxial source or drain structure at a vertically disposed end of the nanowire.

Example embodiment 5: the integrated circuit structure of example embodiment 4, wherein the epitaxial source or drain structures are discrete epitaxial source or drain structures.

Example embodiment 6: the integrated circuit structure of example embodiment 4, wherein the epitaxial source or drain structure is a non-discrete epitaxial source or drain structure.

Example embodiment 7: the integrated circuit structure of example embodiments 4, 5, or 6, wherein the gate stack has a dielectric sidewall spacer, and the epitaxial source or drain structure is an embedded epitaxial source or drain structure extending under the dielectric sidewall spacer of the gate stack.

Example embodiment 8: the integrated circuit structure of example embodiments 4, 5, 6, or 7, further comprising: a pair of conductive contact structures coupled to the epitaxial source or drain structures.

Example embodiment 9: the integrated circuit structure of example embodiment 8, wherein the pair of conductive contact structures is an asymmetric pair of conductive contact structures.

Example embodiment 10: the integrated circuit structure of example embodiments 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein the nanowire is vertically disposed above the fin.

Example embodiment 11: the integrated circuit structure of example embodiments 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10, wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

Example embodiment 12: an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires over a substrate. The first vertical arrangement of nanowires has a greater number of active nanowires than the second vertical arrangement of nanowires. The nanowire first and second vertical arrangements have a coplanar uppermost nanowire and a coplanar bottommost nanowire. The nanowire second vertical arrangement has an oxidized bottommost nanowire. A first gate stack is over the nanowire first vertical arrangement. A second gate stack is over the second vertical arrangement of nanowires and surrounds the oxidized bottommost nanowire.

Example embodiment 13: the integrated circuit structure of example embodiment 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is the same as a horizontal width of the nanowire of the second vertical arrangement of nanowires.

Example embodiment 14: the integrated circuit structure of example embodiment 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is greater than a horizontal width of the nanowire of the second vertical arrangement of nanowires.

Example embodiment 15: the integrated circuit structure of example embodiment 12, wherein the nanowire of the first vertical arrangement of nanowires has a horizontal width that is less than a horizontal width of the nanowire of the second vertical arrangement of nanowires.

Example embodiment 16: the integrated circuit structure of example embodiments 12, 13, 14, or 15, further comprising: a first epitaxial source or drain structure at a first vertically disposed end of the nanowire; and a second epitaxial source or drain structure at a second vertically disposed end of the nanowire.

Example embodiment 17: the integrated circuit structure of example embodiment 16, wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

Example embodiment 18: the integrated circuit structure of example embodiment 16, wherein said first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

Example embodiment 19: the integrated circuit structure of example embodiments 16, 17, or 18, wherein the first gate stack has a dielectric sidewall spacer and the first epitaxial source or drain structure is a first embedded epitaxial source or drain structure extending under the dielectric sidewall spacer of the first gate stack, and wherein the second gate stack has a dielectric sidewall spacer and the second epitaxial source or drain structure is a second embedded epitaxial source or drain structure extending under the dielectric sidewall spacer of the second gate stack.

Example embodiment 20: the integrated circuit structure of example embodiments 16, 17, 18, or 19, further comprising: a first pair of conductive contact structures coupled to the first epitaxial source or drain structure; and a second pair of conductive contact structures coupled to the second epitaxial source or drain structure.

Example embodiment 21: the integrated circuit structure of example embodiments 12, 13, 14, 15, 16, 17, 18, 19, or 20, wherein the nanowire first is vertically disposed above the first fin and the nanowire second is vertically disposed above the second fin.

Example embodiment 22: the integrated circuit structure of example embodiments 12, 13, 14, 15, 16, 17, 18, 19, 20, or 21, further comprising: a gate end cap isolation structure between and in contact with the first and second gate stacks.

Example embodiment 23: the integrated circuit structure of example embodiments 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, or 22, wherein the first and second gate stacks each comprise a high-k gate dielectric layer and a metal gate electrode.

Example embodiment 24: a method of fabricating an integrated circuit structure comprising: forming a vertical arrangement of active nanowires over a substrate; oxidizing one or more bottommost nanowires of the vertical arrangement of active nanowires, but not oxidizing one or more uppermost nanowires of the vertical arrangement of active nanowires; and forming a gate stack around the oxidized one or more bottommost nanowires and around the one or more uppermost nanowires.

Example embodiment 25: the method of embodiment 24, wherein oxidizing the one or more bottommost nanowires of the active nanowire vertical arrangement comprises first forming an oxidation catalyst layer on the one or more bottommost nanowires.