阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 张星旭 曹荣大 金奇奂 郑秀珍 于 2020-01-07 设计创作，主要内容包括：半导体器件包括：有源区,其在衬底上在第一方向上延伸；沟道层,其位于有源区上并竖直地间隔开；栅极结构,其与有源区和沟道层交叉,栅极结构在第二方向上延伸并围绕沟道层；以及源/漏区,其位于栅极结构的一侧的有源区上,源/漏区接触沟道层,源/漏区包括第一外延层和第二外延层,第一外延层具有第一成分并包括第一层和第二层,所述第一层位于沟道层的侧表面上,所述第二层位于源/漏区的下端的有源区上,第二外延层具有与第一成分不同的第二成分,第二外延层在第一方向上位于第一外延层之间,并在第三方向上竖直地位于第一外延层之间。(The semiconductor device includes: an active region extending in a first direction on a substrate; a channel layer on the active region and vertically spaced apart; a gate structure crossing the active region and the channel layer, the gate structure extending in the second direction and surrounding the channel layer; and a source/drain region on the active region at one side of the gate structure, the source/drain region contacting the channel layer, the source/drain region including a first epitaxial layer having a first composition and including a first layer and a second layer, the first layer being on a side surface of the channel layer, the second layer being on the active region at a lower end of the source/drain region, the second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and vertically between the first epitaxial layers in the third direction.)

1. A semiconductor device, comprising:

an active region extending in a first direction on a substrate;

a plurality of channel layers on the active region and vertically spaced apart from each other;

a gate structure intersecting the active region and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; and

a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, the source/drain region comprising:

each first epitaxial layer having a first composition and including a first layer on a side surface of the plurality of channel layers taken in the first direction and a second layer on the active region at a lower end of the source/drain region; and

a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer interposed between the first epitaxial layers in the first direction and interposed between the first epitaxial layers in a third direction, wherein the third direction is a vertical direction perpendicular to the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein the first layer is separated from each other and from the second layer between the plurality of channel layers provided upward and downward in the third direction.

3. The semiconductor device of claim 1, wherein at least a portion of the first epitaxial layer overlaps the second epitaxial layer in plan view.

4. The semiconductor device of claim 1, further comprising:

an inner spacer layer disposed on a lower surface of each of the plurality of channel layers on an opposite side of the gate structure taken in the first direction and having an outer side surface substantially coplanar with the side surfaces of the plurality of channel layers.

5. The semiconductor device of claim 4, wherein the first layer protrudes toward the second epitaxial layer from a side surface formed by the interior spacer layer and the plurality of channel layers.

6. The semiconductor device of claim 4, wherein a side surface of the first layer taken in the first direction is surrounded by the second epitaxial layer, the plurality of channel layers, and the interior spacer layer.

7. The semiconductor device of claim 1, wherein the first epitaxial layer comprises a first impurity and the second epitaxial layer comprises a second impurity different from the first impurity.

8. The semiconductor device of claim 7, wherein each of the first epitaxial layers includes the first impurity at a first concentration, and the second epitaxial layers include the second impurity at a second concentration higher than the first concentration.

9. The semiconductor device of claim 8, wherein the second concentration is in a range of 10 to 20 times the first concentration.

10. The semiconductor device as set forth in claim 1,

wherein the first epitaxial layer and the second epitaxial layer include a first impurity, and

wherein each of the first epitaxial layers includes the first impurity at a first concentration, and the second epitaxial layers includes the first impurity at a second concentration higher than the first concentration.

11. The semiconductor device according to claim 10, wherein the first impurity comprises at least one of arsenic and phosphorus.

12. The semiconductor device of claim 1, wherein each of the first and second epitaxial layers is one of SiAs, SiP, SiPC, SiC, SiPAs, and SiGeP.

13. The semiconductor device of claim 1, wherein the source/drain region further comprises a third epitaxial layer disposed between the first layer and the plurality of channel layers and between the second layer and the active region.

14. The semiconductor device according to claim 13, wherein the third epitaxial layer includes an impurity at a concentration lower than a concentration of an impurity included in the first epitaxial layer.

15. The semiconductor device as set forth in claim 1,

wherein the first layer has a first maximum thickness at the side surfaces of the plurality of channel layers, and

wherein the second layer has a second maximum thickness greater than the first maximum thickness at an upper surface of the active region.

16. The semiconductor device of claim 1, wherein at least a portion of the first epitaxial layer overlaps the gate structure in plan view.

17. A semiconductor device, comprising:

an active region;

a plurality of channel layers on the active region and vertically spaced apart from each other;

a gate structure surrounding upper and lower surfaces of the plurality of channel layers and side surfaces taken in a first direction; and

a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, the source/drain region comprising:

at least one first epitaxial layer having a first composition and covering side surfaces of the plurality of channel layers taken in a second direction and covering at least a portion of an upper surface of the active region at a lower end of the source/drain region; and

a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being stacked on the first epitaxial layer and extending further upward than uppermost surfaces of the plurality of channel layers.

18. The semiconductor device of claim 17, wherein the first epitaxial layer has flexures corresponding to the plurality of channel layers.

19. The semiconductor device of claim 17, further comprising:

an inner spacer layer disposed at a lower portion of each of the plurality of channel layers on an opposite side of the gate structure taken in the second direction,

wherein the first epitaxial layer has a first maximum thickness on a side surface of the plurality of channel layers taken in the second direction, and has a second maximum thickness smaller than the first maximum thickness on a side surface of the inner spacer layer.

20. The semiconductor device of claim 17, wherein the first epitaxial layer comprises a first layer and a second layer, the first layer being respectively located on side surfaces of the plurality of channel layers taken in the second direction, the second layer being located on the active region at a lower end of the source/drain region.

21. A semiconductor device, comprising:

an active region extending in a first direction on a substrate;

a plurality of channel layers on the active region and vertically spaced apart from each other;

a gate structure intersecting the active region and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers;

an inter-spacer layer located on opposite sides of the gate structure taken in the first direction, the inter-spacer layer disposed in a lower portion of each of the plurality of channel layers; and

a source/drain region on the active region on at least one side of the gate structure, the source/drain region being in contact with the plurality of channel layers and including a plurality of epitaxial layers and having a concentration gradient of an impurity corresponding to a vertical arrangement of the inner spacer layer and the plurality of channel layers in a third direction, wherein the third direction is perpendicular to the first direction and the second direction.

22. The semiconductor device of claim 21, wherein in the source/drain regions, the impurity has a first maximum concentration in an outer region of the plurality of channel regions and a second maximum concentration higher than the first maximum concentration in an outer region of the inner spacer layer.

23. The semiconductor device of claim 22, wherein the second maximum concentration is in a range of 10 to 20 times the first maximum concentration.

24. The semiconductor device of claim 22, wherein in the source/drain region, the impurity has the first maximum concentration in a region adjacent to the active region.

25. The semiconductor device of claim 21, wherein the source/drain region has a substantially uniform impurity concentration in a central region taken from the first direction and the third direction.

Technical Field

Example embodiments relate to a semiconductor device.

Background

With the increase in demand for high performance, high speed, multifunction, and the like of semiconductor devices, the integration density of semiconductor devices has been increased. In order to meet the demand for high integration density of semiconductor devices, semiconductor devices having fine patterns have been developed, and it has become important to implement patterns having fine widths or fine pitches therebetween. In addition, in order to overcome the limitation on the operational performance of the planar metal oxide semiconductor fet (mosfet) of the reduced size, development of a semiconductor device including a fin fet (finfet) having a three-dimensional channel has been made.

Disclosure of Invention

Drawings

Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the attached drawings, wherein:

fig. 1 shows a plan view of a semiconductor device according to an example embodiment;

fig. 2 shows a cross-sectional view of a semiconductor device according to an example embodiment;

FIG. 3 illustrates an enlarged view of a portion of a semiconductor device according to an example embodiment;

fig. 4A to 5B illustrate graphs showing a distribution of a concentration of an impurity included in a source/drain region in a semiconductor device according to an example embodiment;

FIG. 6 illustrates an enlarged view of a portion of a semiconductor device according to an example embodiment;

fig. 7 shows a cross-sectional view of a semiconductor device according to an example embodiment;

FIG. 8 illustrates an enlarged view of a portion of a semiconductor device according to an example embodiment;

fig. 9 shows an enlarged view of a portion of a semiconductor device according to an example embodiment;

fig. 10A to 10C illustrate cross-sectional views of a semiconductor device according to example embodiments;

fig. 11A to 11K are diagrams illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment in order;

fig. 12 shows a block diagram of an electronic apparatus including a semiconductor device according to an example embodiment; and

fig. 13 shows a diagram of a system including a semiconductor device according to an example embodiment.

An embodiment relates to a semiconductor device, including: an active region extending in a first direction on a substrate; a plurality of channel layers on the active region and vertically spaced apart from each other; a gate structure crossing the active region and the plurality of channel layers, the gate structure extending in a second direction on the substrate and surrounding the plurality of channel layers; and a source/drain region on the active region of at least one side of the gate structure, the source/drain region being in contact with the plurality of channel layers, the source/drain region including: each first epitaxial layer having a first composition and including a first layer on a side surface of the plurality of channel layers taken in the first direction and a second layer on the active region at a lower end of the source/drain region; and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer interposed between the first epitaxial layers in a first direction and vertically interposed between the first epitaxial layers in a third direction, wherein the third direction is perpendicular to the first direction and the second direction.