阅读说明：本技术 一种低功耗采样mosfet功率管电流的电路 (Circuit for sampling current of MOSFET power tube with low power consumption ) 是由 李征 于 2021-08-10 设计创作，主要内容包括：本发明公开一种低功耗采样MOSFET功率管电流的电路,包括：放大器1、采样管M-(1)、功率管M-(0)和MOS管M-(2),MOS管M-(3)、分压电阻R-(5)、分压电阻R-(6),分压电阻R-(5)与分压电阻R-(6)串联在功率管M-(0)的源极和漏极之间,分压电阻R-(5)与分压电阻R-(6)共接点连接放大器1的正向输入端；MOS管M-(3)与MOS管M-(2)共栅极和共源极,构成电流镜,使得采样管M-(1)的原始采样电流得以重新分配,采样电流的大部分可以返回输出,成为输出电流,小部分经由采样电阻流入地,这部分电流导致的功耗,可以通过调整分压电阻的比例以及MOS管M-(3)与MOS管M-(2)的电流镜的比例,达到降低采样功耗的目的；当功率管与采样管的面积比例比较小的情况下,例如：采用分离器件工艺设计MOSFET功率管,最适合采用上述结构。(The invention discloses a circuit for sampling MOSFET power tube current with low power consumption, which comprises: amplifier 1 and sampling tube M 1 Power tube M 0 And MOS transistor M 2 MOS transistor M 3 A voltage dividing resistor R 5 A voltage dividing resistor R 6 Divider resistor R 5 And a voltage dividing resistor R 6 Is connected in series to the power tube M 0 Between the source and the drain, a voltage dividing resistor R 5 And a voltage dividing resistor R 6 The common contact is connected with the positive input end of the amplifier 1; MOS transistor M 3 And MOS transistor M 2 A common gate and a common source to form a current mirror, so that the sampling tube M 1 The original sampling current is redistributed, most of the sampling current can return to output and become output current, a small part of the sampling current flows into the ground through the sampling resistor, and the power consumption caused by the part of the current can be adjusted by adjusting the proportion of the voltage dividing resistor and the MOS transistor M 3 And MOS transistor M 2 The proportion of the current mirror is used for achieving the purpose of reducing the sampling power consumption; when the area ratio of the power tube to the sampling tube is small, for example: by usingThe MOSFET power tube is designed by a separated device process, and the structure is most suitable for being adopted.)

1. A circuit for sampling MOSFET power tube current with low power consumption comprises: amplifier 1 and sampling tube M₁Power tube M₀And MOS transistor M₂Sampling tube M₁And a power tube M₀Common grid, sampling tube M₁And a power tube M₀Common drain for inputting V_INVoltage, sampling tube M₁Source and MOS transistor M₂Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M₂Grid of (3), MOS transistor M₂The output end is connected with a sampling resistor R₄(ii) a Power tube M₀Source for outputting V_OUTA voltage; the method is characterized in that: further comprising: MOS transistor M₃A voltage dividing resistor R₅A voltage dividing resistor R₆Divider resistor R₅And a voltage dividing resistor R₆Is connected in series to the power tube M₀Between the source and the drain, a voltage dividing resistor R₅And a voltage dividing resistor R₆The common contact is connected with the positive input end of the amplifier 1; MOS transistor M₃Drain electrode of the power transistor M is connected with the power transistor M₀Source, MOS transistor M₃And MOS transistor M₂Common gate and common source, MOS transistor M₃And MOS transistor M₂Constituting a current mirror.

2. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: the power tube M adopts two independent bare chips as the substrate of the device₀And a sampling tube M₁On the die 1; amplifier 1 and MOS tube M₃MOS transistor M₂Sampling resistor R₄A voltage dividing resistor R₅And a voltage dividing resistor R₆Distributed on the bare chip 2, and the voltage-dividing resistor R₅Non-parallel voltage-dividing resistor R₆One end of the connection is connected with V_INA voltage.

3. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: power tube M₀And a sampling tube M₁The MOS tubes of the same type are selected from N-type MOS tubes.

4. The circuit for sampling MOSFET power tube current with low power consumption of claim 1, wherein: the MOS tube M₂And MOS transistor M₃The types are the same, and all adopt P type MOS tube, MOS tube M₂The source electrode is connected with the sampling electrode, the drain electrode is connected with the sampling resistor R₄。

5. The circuit for sampling MOSFET power tube current with low power consumption of claim 4, wherein: the MOS tube M₃And MOS transistor M₂A control loop is connected between the MOS tube M and the MOS tube M for ensuring the MOS tube M₃And MOS transistor M₂The drain voltages are the same, the control loop comprising: amplifier 2, P type MOS tube M₄MOS transistor M₂Drain electrode of (1) and MOS transistor M₃The drain electrode of the amplifier 2 is respectively connected with the reverse input end and the forward input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M₄Grid, MOS transistor M₄Source electrode connected MOS transistor M₂The drain electrode is connected with the sampling resistor R₄。

6. The circuit for sampling MOSFET power tube current with low power consumption of claim 5, wherein: the MOS tube M₄N-type MOS transistor M can also be selected₂Drain electrode of (1) and MOS transistor M₃The drain electrodes of the two transistors are respectively connected to the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M₄Grid, MOS transistor M₄Drain electrode connected with MOS transistor M₂The drain electrode and the source electrode are connected with a sampling resistor R₄。

Technical Field

The invention relates to an electronic component, a semiconductor and an integrated circuit, in particular to a circuit for sampling MOSFET power tube current with low power consumption.

Background

In the design of a DC/DC converter, sampling the current of a MOSFET power tube is essential regardless of which control method is used, for example: under the valley bottom current mode and the peak current mode, the current of the lower power tube and the current of the upper power tube are respectively collected in each period, corresponding ramp wave compensation is combined to form a current ramp wave, and the current ramp wave is intersected with the output of the transconductance amplifierThe PWM signal is generated to control the switching of the power transistor, and the slope of the current ramp needs to be precisely controlled within a set range, so that the stability of the control loop can be ensured, for example: in peak current mode, the ramp-compensated rising slope (M) and the sampled inductor current falling slope (M)₂) The following relationship needs to be satisfied:

the control loop can be stabilized, where D represents the duty cycle.

If the current sampling deviates from the designed value too high, which is equivalent to insufficient slope compensation, subharmonic oscillation occurs; on the contrary, if the current sampling deviates from the design value and is too low, the slope of the synthesized current ramp wave mainly consists of slope compensation, the control mode is changed into a voltage mode, and the zero pole in the loop cannot be correctly compensated by the frequency compensation designed according to the current mode, so that unstable oscillation is caused, and therefore, accurate current sampling is the basis for keeping the stability of the DC/DC converter.

FIG. 1 is a block diagram of a current sample using an exemplary top power transistor, including a power transistor M₀Sampling tube M₁Amplifier 1, resistor R₄And P type MOS tube M₂Power tube M₀The power tube sampling device can be an upper power tube or a lower power tube, and selects a proper power tube for sampling according to different control modes.

When the inductive current flows through the power tube M₀The current of which needs to be sampled, a sampling tube M₁And power tube M₀Is of the same type except that the size area ratio power tube M₀Small, sampling tube M₁And power tube M₀One of the common gate, source or drain is also connected together, and the other, unconnected, is held at the same potential by the action of the amplifier 1; for example: sampling the N-type upper power tube in figure 1, sampling tube M₁And power M₁Transistor common grid and drain, power transistor M₀Is connected to the positive input end of the amplifier 1, and the output of the amplifier 1 is connected with a P-type MOS tube M₂Grid of (2), sampling tube M₁Source electrode and MOS tube M₂Are connected together to the inverting input of an amplifier 1, the amplifier 1 and a MOS transistor M₂Forming a complete negative feedback control loop, under the action of which the sampling tube M₁And power tube M₀The source electrode of the power tube M is kept at the same voltage₀And a sampling tube M₁When the transistor is turned on, the electrical characteristic between the drain and the source is equivalent to a resistance, the voltage difference between the drain and the source divided by the resistance is equal to the current flowing between the two poles, and since the voltage difference between the drain and the source of the two transistors is equal, the current flowing through each transistor is in an inverse relationship with the equivalent resistance, for example: power tube M₀And a sampling tube M₁The equivalent resistance ratio of (a) is 1: N,

R₁＝N*R₀，

R₀representative power tube M₀Equivalent resistance of R₁Sampling tube M₁Then the power tube M₀And a sampling tube M₁The current ratio of (a) to (b) is N:1, i.e.:

I_SMPL＝I_OUT/N

power tube M₀And a sampling tube M₁The equivalent resistance of (a) is not a fixed value and is affected by external factors, such as: the resistance value decreases with the increase of the voltage difference between the gate and the source and increases with the increase of the ambient temperature, but the percentage of the effect of these changes on the resistance value is the same, so the ratio of the resistance values of the two transistors can be kept constant, and the ratio of the currents is also kept constant, the ratio is determined by the respective areas, the larger the area is, the smaller the resistance value is, and finally, the power transistor M and the transistor M are connected₀The sampling current with the current kept in a fixed proportion can be converted into sampling voltage through a resistor for processing by a downstream circuit.

Power tube M₀The self-consumed power during working is as follows:

P_M0＝(V_IN-V_OUT)*I_OUT

the power consumed to sample this current is:

P_SAMPLE＝V_IN*I_OUT/N

sampling current from V_INPassing through a sampling tube M₁MOS transistor M₂And a sampling resistor R₄Up to ground, the power consumption required for sampling is not just the sampling tube M₁But the consumption of the sample current over the entire path if the power transistor M₀By means of integrated circuit process design, sampling tube M₁The sampling current has great flexibility, and is usually easy to realize from tens of ohms to thousands of ohms, so that a great sampling proportion can be freely selected according to the requirement of power consumption, a very small sampling current is obtained, and the sampling power consumption is reduced, for example: power tube M₀When the on-resistance of (2) is 100M Ω and N is 10000, M is₁Has an on-resistance of 1000 omega at V_IN＝5V，I_OUTWhen 1A is satisfied, M₀The power consumed is 100mW and the additional power consumption caused by sampling is 0.5mW, i.e. 0.5%, however, the power transistor M is designed using integrated circuit technology₀The structure is complicated, for example: the 20V withstand voltage power LDMOS (Lateraly Double-Diffused MOSFET) under the current 0.18um process needs 18 layers of light masks to be manufactured, and the power tube M is used for better performance and more competitive cost at present₀Process designs for separating semiconductor devices are often used, for example: power tube M with 20V withstand voltage₀Only 5 layers of light masks are needed under the process of separating devices, the cost advantage is obvious, and the sampling tube M₁Needs and power tube M₀The same process is used to ensure matching of the various electrical properties, and therefore, the sampling tube M₁And a power tube M₀On the same Wafer (Wafer), the control circuit must be designed by using integrated circuit technology, another Wafer is needed, and when packaging, the dies (Die) from the two wafers are inevitably packaged together, as shown in fig. 2, the power tube M₀And a sampling tube M₁The source electrodes of (a) are connected to the control circuit by bonding wires, which require bonding pads (Bond Pad) with a size proportional to the wire diameter of the bonding wires, for example: a 1.2mil (═ 30.48um) wire diameter copper wire requires a 90um x 90um pad. The size of the bonding pad cannot be larger than the source of the MOSFETThe size of the pole, because so there is a large free area under the pad, reduces the sample Density (Pattern Density) of the source, and affects the electrical characteristics, i.e. the sampling tube M₁Is limited by the size of the pad, for example: power tube M with withstand voltage of 20V shown in FIG. 3₀The equivalent resistance of (1) is 15M omega, and the power tube M₀And a sampling tube M₁Is about 64 at V_IN＝5V，I_OUTWhen 1A, the power tube M₀The consumed power is 15mW, the extra power consumption caused by sampling is 78mW, and the power consumption is higher than that of the power tube M₀Is also large!

Disclosure of Invention

Conventional current sampling methods generate a large amount of power consumption because the sampled current flows from the input stream to ground. Although the sampling current is small relative to the output current, the voltage difference on the path is large, resulting in large sampling power consumption. Excessive sampling power consumption can reduce the overall efficiency of the system, and even trigger thermal protection, which affects the normal operation of the system, so that the sampling power consumption is reduced, or the sampling current is reduced, or the voltage difference on the path is reduced. The structure for sampling the current of the MOSFET power tube with low power consumption provided by the invention starts from the two aspects, realizes low power consumption sampling, and gets rid of the limitation of the size ratio of the power tube and the sampling tube.

The technical scheme adopted by the invention is as follows: the method comprises the following steps: amplifier 1 and sampling tube M₁Power tube M₀And MOS transistor M₂Sampling tube M₁And a power tube M₀Common grid, sampling tube M₁And a power tube M₀Common drain for inputting V_INVoltage, sampling tube M₁The source electrode of the MOS transistor is a sampling electrode, the sampling electrode and the MOS transistor M₂Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M₂Grid of (3), MOS transistor M₂The output end is connected with a sampling resistor R₄(ii) a Power tube M₀Is an output stage for outputting V_OUTA voltage; further comprising: MOS transistor M₃A voltage dividing resistor R₅A voltage dividing resistor R₆Divider resistor R₅And a voltage dividing resistor R₆Is connected in series to the power tube M₀Between the source and the drain, a voltage dividing resistor R₅And a voltage dividing resistor R₆The common contact is connected with the positive input end of the amplifier 1; MOS transistor M₃Drain electrode of the MOS transistor M is connected with the output electrode₃And MOS transistor M₂Common gate and common source, MOS transistor M₃And MOS transistor M₂Constituting a current mirror.

Further, two independent bare chips are used as the substrate of the device, and the power tube M₀And a sampling tube M₁On the die 1; amplifier 1 and MOS tube M₃MOS transistor M₂Sampling resistor R₄A voltage dividing resistor R₅And a voltage dividing resistor R₆Distributed on the bare chip 2, and the voltage-dividing resistor R₅Non-parallel voltage-dividing resistor R₆One end of the connection is connected into V_INA voltage.

Further, the power tube M₀And a sampling tube M₁The MOS tubes of the same type are selected from N-type MOS tubes.

Further, the MOS transistor M₂And MOS transistor M₃The types are the same, and all adopt P type MOS tube, MOS tube M₂The source of the sampling resistor is connected with the sampling electrode, and the drain of the sampling resistor is connected with the sampling resistor R4.

Further, the MOS transistor M₃And MOS transistor M₂A control loop is connected between the MOS tube M and the MOS tube M for ensuring the MOS tube M₃And MOS transistor M₂The drain voltages are the same, the control loop comprising: amplifier 2, P type MOS tube M₄MOS transistor M₂And MOS transistor M₃The drain electrode of the amplifier 2 is respectively connected with the reverse input end and the forward input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M₄Grid, MOS transistor M₄Source electrode connected MOS transistor M₂The drain electrode is connected with the sampling resistor R₄。

Further, the MOS transistor M₄N-type MOS transistor M can also be selected₂And MOS transistor M₃The drain electrodes of the two transistors are respectively connected to the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M₄Grid, MOS transistor M₄Drain electrode connected with MOS transistor M₂The drain electrode and the source electrode are connected with a sampling resistor R₄。

It can be seen from the above technical solutions thatThe invention has the following advantages: the current sampling circuit is added with a divider resistor R₅A voltage dividing resistor R₆By lowering the voltage dividing resistance R₅And R₆Can reduce the sampling tube M₁The original sampling current is obtained, which is equivalent to increasing the area ratio of the power tube and the sampling tube; on the basis, the MOS transistor M₂And MOS transistor M₃Current mirrors formed so that the sampling tube M₁The original sampling current is redistributed, and the MOS tube M is enlarged₂And MOS transistor M₃According to the current mirror proportion, most of original sampling current can be returned to be output to become output current, and a small part of original sampling current flows into the ground through the sampling resistor to become final sampling current.

Simultaneously, as the area ratio of power tube and sampling pipe diminishes, the ratio of original sampling current and power tube electric current is more accurate, and the joining of divider resistance and current mirror can produce certain influence to the accuracy of final sampling current, however, resistance partial pressure and current mirror degree of accuracy all rely on the matching between the device, under the integrated circuit technology, be better than the separation device far away to the control of matching, consequently, the joining of divider resistance and current mirror can be ignored to the accuracy influence of final sampling current.

Drawings

FIG. 1 is a diagram of a prior art current sampling architecture;

FIG. 2 is a diagram of a conventional seal structure when different technologies are used to design MOSFETs and control circuits;

FIG. 3 is a layout of a power MOSFET and a sampling MOSFET designed by a conventional discrete device process;

FIG. 4 is a schematic circuit diagram of the present patent;

FIG. 5 is a control loop of the present patent for ensuring that the drain voltages of the current mirrors are the same;

fig. 6 is yet another control loop of the present patent with respect to ensuring that the current mirror drain voltages are the same.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings.

FIG. 4 is a schematic diagram of the present invention, including: amplifier 1 and sampling tube M₁Power tube M₀And MOS transistor M₂Sampling tube M₁And a power tube M₀The two are of the same type, both are of N type, and share a grid electrode and a drain electrode, and the drain electrode inputs V_INVoltage, sampling tube M₁The source electrode of the MOS transistor is a sampling electrode, the sampling electrode and the MOS transistor M₂Connected and commonly connected to the inverting input terminal of the amplifier 1, and the output terminal of the amplifier 1 is connected with the MOS transistor M₂Grid of (3), MOS transistor M₂Is connected with the sampling resistor R₄(ii) a Power tube M₀Is an output electrode for outputting V_OUTA voltage; further comprising: MOS transistor M₃A voltage dividing resistor R₅A voltage dividing resistor R₆The circuit adopts two independent bare chips as the substrate of the device, and the power tube M shown in figure 4₀And a sampling tube M₁On the bare chip 1, an amplifier 1 and a MOS transistor M₃MOS transistor M₂Sampling resistor R₄A voltage dividing resistor R₅And a voltage dividing resistor R₆Distributed on the bare chip 2, and the voltage-dividing resistor R₅And a voltage dividing resistor R₆Is connected in series to the power tube M₀Between the source and the drain of (1), for sampling V_INAnd V_OUTA voltage difference therebetween; voltage dividing resistor R₅And a voltage dividing resistor R₆Voltage V of the common junction_FBEqual to:

V_FB＝(V_IN–V_OUT)*R₆/(R₅+R₆)+V_OUT

voltage dividing resistor R₅And a voltage dividing resistor R₆Is connected to the positive input of the amplifier 1, the voltage V_FBConnected to the positive input end of the amplifier 1, and a sampling tube M₁Voltage V of the sampling electrode_S1Is connected to the reverse input end of the amplifier 1 and the P-type MOS tube M₂Source electrode of MOS transistor M₂The grid of the MOS transistor M is connected with the output end of the amplifier 1₂As the output of the final sampled current,is connected to a sampling resistor R₄(ii) a Composed of an amplifier 1 and a MOS transistor M₂The negative feedback loop formed ensures that:

V_S1＝V_FB，

sampling tube M₁The current of (a) is:

I₁＝(V_IN-V_S1)/R₁，

can be simplified as follows:

I₁＝I₀/N/(1+R₆/R₅)，

MOS transistor M₂The amplifier can also be an N-type MOS tube, and if the N-type MOS tube is selected, the forward input end and the reverse input end of the amplifier 1 need to exchange connection modes.

MOS transistor M₃And MOS transistor M₂The common gate is connected with the common source to form a current mirror, and the MOS transistor M₃Is connected with the output electrode, and a MOS tube M is assumed₃MOS transistor M₂The area ratio of (A) is M: 1, the corresponding current ratios are:

I₂＝I₃/M，

wherein, I₂Is a MOS transistor M₂Current of (I)₃Is a MOS transistor M₃Due to:

I₁＝I₂+I₃，

therefore:

I₂＝I₀/N/(1+R₆/R₅)/(1+M)，

compared with the traditional mode, the final sampling current is reduced by a multiple of the current of the power tube:

K＝(1+R₆/R₅)*(1+M)，

because, another part of the sampling tube M₁Current of via MOS transistor M₃To the drain of V_OUT：

I₃＝I₀*M/(1+M)/N/(1+R₆/R₅)，

The power consumption generated by the improved sampling circuit can be divided into R₅And R₆In connection therewith:

P_R＝(V_IN-V_OUT)*(V_IN-V_OUT)/(R₅+R₆)，

and with I₃In connection therewith:

P_I3＝I₃*(V_IN-V_OUT)，

and with I₂In connection therewith:

P_I2＝I₂*V_IN，

voltage dividing resistor R₅And a voltage dividing resistor R₆To V is outputted to_OUT，I₃Is also finally output to V_OUTBoth currents become I_OUTThe final output current is their sum:

I_OUT＝I₀*[1+M/(1+M)/N/(1+R₆/R₅)+R₀/(R₅+R₆)]

thus, P_RAnd P_I3Although generated by the sampling circuit, the power consumption of the part is M₀The same power consumption is generated, and the same power consumption is attributed to the power consumption caused by the output current, and in addition, R₅And R₆Is a voltage dividing resistor, the value of which is usually large, for example: tens of k Ω to hundreds of k Ω, resulting in R₀/(R₅+R₆)<<1, the current and power consumption produced are negligible, so that it can be seen that the extra power consumption caused by sampling is only P_I2It is connected with the power tube M₀The proportion of power consumption generated is:

P_I2/P_M0＝V_IN/(V_IN–V_OUT)/N/K，

in the case of N being constant, P_I2Can be adjusted by adjusting the divider resistance R₅And a voltage dividing resistor R₆Is reduced while increasing the current mirror M₃And M₂Ratio of (d) to the final sampled current I flowing to ground₂Further reduction to meet power consumption requirements, such as: if the voltage dividing resistor R is used₅And a voltage dividing resistor R₆In a ratio of 1: 2, MOS transistor M₃And MOS transistor M₂In a ratio of 50: 1, in the same case V_IN＝5V，I_OUT＝1A，R₀The power consumed by the output current is still about 15mW when N is 64 and 15m Ω, and the extra power consumption P caused by sampling_I2Is 0.51mW, i.e., 3.4%. Compared with the additional power consumption of 78mW under the traditional method, the additional power consumption is reduced by 153 times, and actually I_OUT≠I₀Is instead I_OUT＝1.005*I₀However, in the above calculation, I_OUTIs approximately I₀The error caused by this simplification is negligible.

Voltage dividing resistor R₅And a voltage dividing resistor R₆Ratio of (1) and MOS transistor M₃And MOS transistor M₂The ratio of (a) to (b) is adjusted not only in consideration of power consumption but also to ensure circuit performance, for example: if the voltage dividing resistor R is used₆And a voltage dividing resistor R₅Is too high, sampling tube M₁The voltage drop between the drain and the source is very small, and the sampled voltage needs the amplifier to have lower input offset voltage, otherwise the power tube M₀And a sampling tube M₁The current ratio of (a) cannot be guaranteed, which undoubtedly increases the design difficulty of the amplifier; conversely, if the ratio is decreased, the sampling tube M is increased₁Voltage drop between drain and source, sampling tube M₁The source of the transistor M is very close to the output voltage, and when the voltage difference is too small, the MOS transistor M₃Will not have enough space to ensure the normal operation of the current mirror, and therefore, the divider resistor R is optimized₆And a voltage dividing resistor R₅The ratio of (a) to (b) should be balanced in terms of power consumption and accuracy while ensuring normal operation of the circuit.

MOS transistor M₃And MOS transistor M₂Forming a current mirror structure such that the current mirror can be mounted on the MOS transistor M₃And MOS transistor M₂Area ratio shunting sampling pipe M₁Current of MOS transistor M₃And MOS transistor M₂The MOSFET needs to work in the same working area, and under the working state, the MOSFET has 2 working areas, namely a linear area and a constant current area, so as to ensure that the MOS transistor M₃And MOS transistor M₂In the same operating region, their drain voltages are the same, which usually requires adding a control loop for ensuring the drain voltages are the same, as shown in fig. 5, the MOS transistor M₂And MOS transistor M₃The drain electrodes of the two transistors are respectively connected with the reverse input end and the forward input end of the amplifier 2, and the control loop passes through the amplifier 2 and the P-type MOS transistor M₄The negative feedback loop is formed to force the MOS transistor M₂And MOS transistor M₃The drain electrode of the MOS transistor M always keeps equal voltage, thereby ensuring that the MOS transistor M is in a state of being in a non-contact state₂And MOS transistor M₃The same as the working area of the working area; FIG. 6 shows that if MOS transistor M₄The control loop can still work by selecting the N-type MOS transistor, and the MOS transistor M₂And MOS transistor M₃The drain electrodes of the two transistors are respectively connected to the positive input end and the negative input end of the amplifier 2, and the output end of the amplifier 2 is connected with the MOS tube M₄Grid, MOS transistor M₄Drain electrode connected with MOS transistor M₂The drain electrode and the source electrode are connected with a sampling resistor R₄。

Enlarged MOS transistor M₃And MOS transistor M₂By a ratio of (A) to (B) which can reduce P_I2However, too large a proportion would result in I₂Becomes very small at low output currents, I₂Not only one of the branch currents of the current mirror, but also in the two feedback loops of amplifier 1 and amplifier 2, if I₂Too low, the two loops have the problems of instability or too slow response, so the MOS transistor M is optimized₃And MOS transistor M₂In proportions that balance power consumption and proper operation of the loop under various conditions.