阅读说明：本技术 Linux下CPU核间中断通信的实现方法及装置 (Method and device for realizing inter-CPU (central processing unit) core interrupt communication under Linux ) 是由 葛正中 林坤 李涛 赵伦 马明礼 于 2020-04-14 设计创作，主要内容包括：本发明实施例提供一种Linux下CPU核间中断通信的实现方法及装置,所述方法包括：在用户空间执行向目标任务发送消息的操作,将消息写入用户空间消息队列中；执行写控制信号器件的操作,触发目标任务所在的目标CPU核发生中断；执行自定义内核中断处理流程,以使得目标CPU核直接跳转至目标任务；从用户空间消息队列中读取消息。本发明实施例消息内容的收发均在用户空间进行,通过外部的控制信号器件触发目标任务所在的目标CPU核发生中断,中断发生后,无须经过内核调度器触发重调度,即可快速从内核态返回到指定消息收发流程,整个过程高效、可靠,缩短了CPU核任务间消息收发的响应时间,可有效提升5G基站系统的实时性能。(The embodiment of the invention provides a method and a device for realizing inter-CPU (central processing unit) core interrupt communication under Linux, wherein the method comprises the following steps: executing the operation of sending the message to the target task in the user space, and writing the message into a user space message queue; executing the operation of a writing control signal device, and triggering a target CPU core where a target task is located to generate interruption; executing a custom kernel interrupt processing flow to enable a target CPU core to directly jump to a target task; the message is read from the user space message queue. The receiving and sending of the message content are carried out in the user space, the target CPU core where the target task is located is triggered to be interrupted through an external control signal device, after the interruption occurs, rescheduling can be quickly returned to the designated message receiving and sending flow from the kernel mode without triggering by a kernel scheduler, the whole process is efficient and reliable, the response time of message receiving and sending among the tasks of the CPU core is shortened, and the real-time performance of the 5G base station system can be effectively improved.)

1. A method for realizing interruption communication between CPU cores under Linux is characterized by comprising the following steps:

executing the operation of sending a message to a target task in a user space, and writing the message into a user space message queue;

executing the operation of a writing control signal device, and triggering a target Central Processing Unit (CPU) core where the target task is located to generate interruption;

executing a custom kernel interrupt processing flow to enable the target CPU core to directly jump to the target task;

and reading the message from the user space message queue.

2. The method for implementing inter-CPU-core interrupt communication under Linux according to claim 1, wherein said executing the operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

3. The method for implementing inter-CPU-core interrupt communication under Linux according to claim 1, wherein said executing the operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

4. The method for implementing inter-CPU-core interrupt communication under Linux according to claim 1, wherein the executing a custom kernel interrupt processing flow to cause the target CPU core to directly jump to the target task specifically is:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

5. The method for implementing inter-CPU-core interrupt communication under Linux according to claim 1, wherein the control signal device is specifically an erasable programmable logic device EPLD register.

6. An apparatus for implementing inter-CPU core interrupt communication under Linux, comprising:

the message sending module is used for executing the operation of sending the message to the target task in the user space and writing the message into a user space message queue;

the interrupt triggering module is used for executing the operation of a writing control signal device and triggering a target Central Processing Unit (CPU) core where the target task is located to generate interrupt;

the interrupt processing module is used for executing a custom kernel interrupt processing flow so as to enable the target CPU core to directly jump to the target task;

and the message reading module is used for reading the message from the user space message queue.

7. The apparatus for implementing CPU inter-core interrupt communication under Linux according to claim 6, wherein said interrupt trigger module is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

8. The apparatus for implementing CPU inter-core interrupt communication under Linux according to claim 6, wherein said interrupt trigger module is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

9. The apparatus for implementing CPU inter-core interrupt communication under Linux according to claim 6, wherein said interrupt processing module is specifically configured to:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

10. The apparatus for implementing CPU inter-core interrupt communication under Linux according to claim 6, wherein said control signal device is specifically an erasable programmable logic device EPLD register.

11. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method for implementing inter-CPU-core interrupt communication under Linux according to any one of claims 1 to 5 when executing said program.

12. A non-transitory computer readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method for implementing inter-CPU core interrupt communication under Linux according to any one of claims 1 to 5.

Technical Field

The invention relates to the technical field of computers, in particular to a method and a device for realizing inter-CPU (central processing unit) core interrupt communication under Linux.

Background

The service software of the 5G (the 5th Generation, fifth Generation mobile communication technology) base station system runs on a multitasking Linux operating system, and each CPU (Central processing unit) core runs a plurality of tasks (processes), and the tasks are executed in a time-sharing manner by depending on the scheduling of the operating system core. The Linux messaging mechanism is completed in a kernel mode, and when the Linux messaging mechanism is used by an application program, mutual copying of message contents between a user mode and the kernel mode is involved, and the copying belongs to system overhead.

When a CPU is in a high-load and non-idle state, a task on one CPU core sends a message to a task on the other CPU core, the task on the first CPU core needs to enter a kernel state, the message content of a user state is copied to the kernel state, a target task on the second CPU core is awakened, task scheduling on the second CPU core is triggered, a task to be switched and executed is selected through task scheduling of an operating system kernel, messages in a message queue are read and copied to the user state, and finally the user state task receives the message.

The existing task message transceiving processing flow between CPU cores has the following defects: when one CPU core breaks the operation of the other CPU core, the core state is required to enter to trigger IPI interruption (Inter-processor interrupts), and the process of entering the core state from the user state is time-consuming; reading of the existing message receiving and sending contents is carried out in a kernel mode, when a message is sent, the message needs to be copied from a user mode to the kernel mode, and when a task receives the message, the message needs to be copied from the kernel mode to the user mode; if the CPU of the target task is busy, the target CPU core needs to be switched to the target task through kernel scheduling, and the process is not real-time enough, so that the task message receiving and sending response time among the CPU cores is prolonged, and the real-time performance of the whole system is influenced.

Disclosure of Invention

In order to solve or at least partially solve the problem that the real-time performance is affected due to the fact that the task message receiving and sending response time between the CPU cores is long, the embodiment of the invention provides a method and a device for achieving communication interruption between the CPU cores under Linux.

In a first aspect, an embodiment of the present invention provides a method for implementing inter-CPU core interrupt communication under Linux, including:

executing the operation of sending a message to a target task in a user space, and writing the message into a user space message queue;

executing the operation of a writing control signal device, and triggering a target Central Processing Unit (CPU) core where the target task is located to generate interruption;

executing a custom kernel interrupt processing flow to enable the target CPU core to directly jump to the target task;

and reading the message from the user space message queue.

Optionally, the executing the operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

Optionally, the executing the operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

Optionally, the executing a custom kernel interrupt processing flow to make the target CPU core directly jump to the target task specifically includes:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

Optionally, the control signal device is embodied as an erasable programmable logic device EPLD register.

In a second aspect, an embodiment of the present invention provides an apparatus for implementing inter-CPU core interrupt communication under Linux, including:

the message sending module is used for executing the operation of sending the message to the target task in the user space and writing the message into a user space message queue;

the interrupt triggering module is used for executing the operation of a write control signal device and triggering a target CPU core where the target task is located to generate interrupt;

the interrupt processing module is used for executing a custom kernel interrupt processing flow so as to enable the target CPU core to directly jump to the target task;

and the message reading module is used for reading the message from the user space message queue.

Optionally, the interrupt triggering module is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

Optionally, the interrupt triggering module is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

Optionally, the interrupt processing module is specifically configured to:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

Optionally, the control signal device is embodied as an erasable programmable logic device EPLD register.

In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements, when executing the program, the method steps for implementing inter-CPU core interrupt communication under Linux as provided in the first aspect.

In a fourth aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for implementing inter-CPU-core interrupt communication under Linux, as provided in the first aspect.

The method and the device for realizing the interrupt communication among the CPU cores under the Linux provided by the embodiment of the invention have the advantages that the receiving and the sending of the message content are carried out in the user space, the message content does not need to be copied from the user space to the kernel space when being sent, and is copied from the kernel space to the user space when being received, triggering a target CPU core where a target task is located to generate an interrupt through an external control signal device, the triggering interrupt process is carried out in a user mode, and after the interrupt occurs, the target CPU core executes a self-defined interrupt processing flow without triggering rescheduling through a kernel scheduler, the method can quickly return to the designated message transceiving flow from the kernel state, the whole process is efficient and reliable, the response speed of message transceiving between different CPU core tasks in the system is improved, the response time of message transceiving between the CPU cores is shortened, and the real-time performance of the 5G base station system can be effectively improved under the high-load state of the CPU.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional process for processing task messages between CPU cores in a CPU high load state;

FIG. 2 is a schematic flow chart of a method for implementing inter-CPU inter-core interrupt communication under Linux according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart illustrating a method for implementing inter-CPU core interrupt communication under Linux according to another embodiment of the present invention;

FIG. 4 is a schematic structural diagram of an apparatus for implementing inter-CPU inter-core interrupt communication under Linux according to an embodiment of the present invention;

fig. 5 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic flow chart of the conventional CPU inter-core task message processing under the CPU high load state, when the CPU1 and the CPU2 are in the high load and non-idle waiting state, the task a running on the CPU1 sends a message to the task B on the CPU2, and at this time, the CPU2 is busy executing other user-mode tasks and cannot receive the message immediately. The messaging response time at this point is relatively long and cannot be guaranteed to be completed in the desired time. As shown in fig. 1, step (1) shows that task a sends a message, and a standard Linux system needs to send a message and enter a kernel through system call, which is time-consuming; step (2) is that task A links the sent message content to the system message content queue, because the message content is in the user mode memory, but the message sending and receiving interaction is carried out in the kernel mode, the message content in the user mode memory needs to be copied to the kernel mode at this point, and then is linked to the kernel mode message structure; step (3) is that task A initiates an operation of notifying task B, including setting the state of task kernel state message structure B as ready state; step (4) triggering IPI interruption aiming at the CPU2 for the task A, wherein the IPI interruption is used for interrupting the task currently executed by the CPU2, and the standard Linux system needs kernel-mode authority when triggering the IPI interruption; step (5) triggers the kernel scheduler after the CPU2 receives the IPI interrupt, and the kernel scheduler selects the next task to be executed by the CPU 2. The kernel scheduler is responsible for overall planning the operation of all tasks in the whole Linux system, including system tasks, user tasks, soft interrupt tasks and the like, in the base station system, the kernel scheduler manages tens of thousands of tasks, and a plurality of tasks in a ready state at the same time are more, so that when the load of a CPU is higher and is busy, the next execution task selected by the kernel scheduler is not guaranteed to be task B, and possibly to be a system task with higher priority, and the time for the task B to finally receive the message is not real-time enough; step (6) is that after the task B is successfully selected and executed, the message content in the kernel-mode message structure is read; and (7) copying the read message content into a user mode memory by the task B, and finally returning to the user mode part of the task B to receive the message sent by the task A.

In order to solve the problems that the existing CPU inter-core task message receiving and sending response time is long and the real-time performance is affected, the embodiment of the invention provides a method and a device for realizing inter-core CPU interrupt communication under Linux.

Fig. 2 is a schematic flow diagram of a method for implementing inter-CPU-core interrupt communication under Linux according to an embodiment of the present invention, and as shown in fig. 2, the method for implementing inter-CPU-core interrupt communication under Linux includes:

step 100, executing an operation of sending a message to a target task in a user space, and writing the message into a user space message queue;

specifically, the user mode task starts to execute the operation of sending the message to the target task, and the content data corresponding to the message is hung in the user space message queue which can be accessed by the target task.

Step 101, executing the operation of a writing control signal device, and triggering a target Central Processing Unit (CPU) core where the target task is located to generate interruption;

specifically, in this embodiment, after writing the message into the user space message queue, the user-mode task executes the operation of the write control signal device, and triggers the target CPU core where the target task is located to generate an interrupt, thereby interrupting the task execution of the target CPU core. The operation can be carried out in a user space without entering a kernel space through system calling, and timeliness of interrupting execution of a target CPU task is improved.

It is worth to be noted that the interruption of the target CPU core where the target task is triggered is completed by an external control signal device, which belongs to a hardware behavior action, thereby further improving the operation efficiency.

102, executing a custom kernel interrupt processing flow to enable the target CPU core to directly jump to the target task;

specifically, after the target CPU core is interrupted, a predefined user-defined kernel interrupt processing flow is executed, so that the target task in a user mode can be directly skipped without task selection of a kernel scheduler of a Linux system.

In the embodiment, the target CPU core executes the custom interrupt processing flow after receiving the interrupt, so that the target task in the user mode can be directly jumped without task scheduling of a kernel scheduler of a Linux system. This process ensures the real-time and reliability of the message received by the target task.

Step 103, reading the message from the user space message queue.

And finally, executing the target task, accessing the user space message queue, reading the specific content of the message, and finally realizing the receiving and sending of the task message among different CPU cores. This operation avoids copying data from kernel space to user space and is therefore more efficient.

In the method for realizing the interrupt communication between the CPU cores under the Linux provided by the embodiment of the invention, the receiving and sending of the message content are carried out in the user space, the message content does not need to be copied from the user space to the kernel space when being sent, and is copied from the kernel space to the user space when being received, triggering a target CPU core where a target task is located to generate an interrupt through an external control signal device, the triggering interrupt process is carried out in a user mode, and after the interrupt occurs, the target CPU core executes a self-defined interrupt processing flow without triggering rescheduling through a kernel scheduler, the method can quickly return to the designated message transceiving flow from the kernel state, the whole process is efficient and reliable, the response speed of message transceiving between different CPU core tasks in the system is improved, the response time of message transceiving between the CPU cores is shortened, and the real-time performance of the 5G base station system can be effectively improved under the high-load state of the CPU.

In another embodiment of the present invention, on the basis of the above embodiment, the executing operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

Specifically, after the message is written into the user space message queue, the user-mode task executes the operation of the write control signal device, and triggers the target CPU core where the target task is located to generate an interrupt, thereby interrupting the task execution of the target CPU core.

In this embodiment, the user-mode task writes an interrupt operation instruction value into the control signal device by executing an operation of writing the control signal device, and after receiving the interrupt operation instruction value, the control signal device sends a control signal to a general purpose input output GPIO pin on the affinity CPU core corresponding to the interrupt operation instruction value, where the affinity CPU core is a target CPU core, and after receiving the control signal, the GPIO pin on the target CPU core triggers an interrupt to interrupt operation of the target CPU core.

For example, the interrupt operation instruction value is an 8-bit value, each bit of the value corresponds to a pin on the CPU, and each pin corresponds to an interrupt on the trigger affinity CPU core.

The embodiment provides an implementation mode for triggering the target CPU core to generate the interrupt by executing the operation of the write control signal device, the target CPU core is triggered to interrupt by a pin on the target CPU core controlled by the write control signal device in the user space, the interrupt is triggered by adopting the hardware mode, the efficiency is high, the condition that the interrupt enters the kernel space through system call is avoided, the task execution after the interrupt can avoid the scheduling of a Linux kernel scheduler, and the timeliness of the task execution of the target CPU can be effectively improved.

In another embodiment of the present invention, on the basis of the above embodiment, the executing operation of the write control signal device triggers the target CPU core where the target task is located to generate an interrupt, specifically:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

Specifically, the present embodiment presents another implementation in which the device operation triggering the target CPU core to generate an interrupt is performed by writing a control signal. The user mode task writes an interrupt operation instruction value into a control signal device by executing operation of writing the control signal device, the control signal device sends a control signal to a Peripheral Component Interface Express (PCIE) interface after receiving the interrupt operation instruction value, the PCIE interface sends an interrupt request to an affinity CPU core corresponding to the interrupt operation instruction value, the affinity CPU core is a target CPU core, the target CPU core sends an interrupt response to the PCIE interface after receiving the interrupt request, the PCIE interface returns an interrupt vector value to the target CPU core after receiving the interrupt response, the target CPU core searches a corresponding interrupt service program in a memory according to the interrupt vector value, then reads the corresponding interrupt service program, and then processes the interrupt.

According to the method for realizing the inter-CPU core interrupt communication under the Linux, the PCIE interface is controlled to trigger the target CPU core interrupt by writing the control signal device in the user space, the interrupt is triggered by adopting the hardware mode, the efficiency is high, the condition that the interrupt enters the kernel space through system calling is avoided, the task execution after the interrupt can avoid the scheduling of a Linux kernel scheduler, and the timeliness of the target CPU task execution can be effectively improved.

Based on the content of the above embodiment, the executing the custom kernel interrupt processing flow to make the target CPU core directly jump to the target task specifically includes:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

Specifically, after the target CPU core is interrupted, executing a user-defined kernel interrupt processing flow, firstly storing the context of the interrupted task, further hooking the interrupted task, then searching the context corresponding to the target task, and if the context corresponding to the target task is found, directly jumping to the target task and executing the target task.

According to the method for realizing the inter-CPU core interrupt communication under the Linux, the target CPU core executes the custom kernel interrupt processing flow, the dispatching of a Linux kernel scheduler is avoided, the target CPU core directly executes the target task, and the timeliness of the inter-task message transmission is improved.

In another embodiment of the present invention, based on the above embodiment, the control signal device is specifically an erasable programmable logic device EPLD register.

Specifically, the control signal Device is used to issue a control signal to trigger the target CPU core to generate an interrupt, and in this embodiment, the control signal Device may be an EPLD (Erasable Programmable Logic Device) register.

It should be noted that the EPLD register is optional, and the control signal device may also be other devices capable of sending out a control signal, such as an FPGA (Field Programmable Gate Array).

The method for realizing the inter-CPU core interrupt communication under the Linux provided by the embodiment of the invention triggers the target CPU core where the target task is located to generate the interrupt and is completed by the EPLD, belongs to the action of hardware behaviors, and further improves the operation efficiency.

Fig. 3 is a schematic flow chart of a method for implementing inter-CPU core interrupt communication under Linux according to another embodiment of the present invention. As shown in step (1) in fig. 3, the user mode task a starts to send a message operation, and links the message content to a queue accessible by the task B, and this operation is performed in the user mode, and does not need to enter the kernel mode, and does not need to perform an operation of copying from the user mode to the kernel mode, thereby improving the operation efficiency; as shown in step (2), step (3) and step (4) in fig. 3, after the hooking message content queue is completed, the task a writes the epld register, after the epld receives the instruction, the gpio pin of the affinity CPU2 is controlled to trigger the interrupt, and the execution of the CPU2 is interrupted, which can be performed in the user state, without entering the kernel state through system call, so that the timeliness of the operation of interrupting the CPU2 is improved, the triggering interrupt operation is completed by the epld, which belongs to a hardware behavior action, and the efficiency is also higher; as shown in step (5) and step (6) in fig. 3, after receiving the interrupt, the target CPU2 executes a custom kernel interrupt processing flow, first stores the context of the interrupted task of the CPU2, then searches for the context of the target task B, and after obtaining the context of the task B, directly jumps to the task B without task selection by the kernel scheduler, which ensures the real-time performance and reliability of the message received by the task B; as shown in step (7) in fig. 3, the task B reads the message sent by the task a in the user mode, which avoids the operation of copying data from the kernel mode to the user mode when the standard system finally receives the message, and is more efficient.

Fig. 4 is a schematic structural diagram of an apparatus for implementing inter-CPU core interrupt communication under Linux according to an embodiment of the present invention, including: a message sending module 410, an interrupt triggering module 420, an interrupt handling module 430, and a message reading module 440, wherein,

a message sending module 410, configured to execute an operation of sending a message to a target task in a user space, and write the message into a user space message queue;

specifically, the message sending module 410 is configured to execute an operation of sending a message to a target task, and hang content data corresponding to the message to a user space message queue accessible to the target task, so that the content data of the message does not need to be copied from a user space to a kernel space, and the operation efficiency can be effectively improved.

An interrupt triggering module 420, configured to execute an operation of a write control signal device, and trigger a target central processing unit CPU core where the target task is located to generate an interrupt;

specifically, the interrupt triggering module 420 is configured to execute an operation of a write control signal device, trigger a target CPU core where a target task is located to generate an interrupt, and interrupt task execution of the target CPU core. The operation can be carried out in a user space without entering a kernel space through system calling, and timeliness of interrupting execution of a target CPU task is improved.

The interrupt processing module 430 is configured to execute a custom kernel interrupt processing flow, so that the target CPU core directly jumps to the target task;

specifically, the interrupt processing module 430 is configured to execute a predefined custom kernel interrupt processing flow after the target CPU kernel is interrupted, so that the target task in the user mode can be directly skipped without task selection by a kernel scheduler of the Linux system.

In the embodiment, the target CPU core executes the custom interrupt processing flow after receiving the interrupt, so that the target task in the user mode can be directly jumped without task scheduling of a kernel scheduler of a Linux system. This process ensures the real-time and reliability of the message received by the target task.

A message reading module 440, configured to read the message from the user space message queue.

Finally, the target task is executed, and the message reading module 440 is configured to access the user space message queue, read specific content of the message, and finally implement receiving and sending of task messages between different CPU cores. This operation avoids copying data from kernel space to user space and is therefore more efficient.

The device for realizing the interrupt communication among the CPU cores under the Linux provided by the embodiment of the invention has the advantages that the receiving and the sending of the message content are carried out in the user space, the message content does not need to be subjected to the process of copying from the user space to the kernel space when being sent and copying from the kernel space to the user space when being received, triggering a target CPU core where a target task is located to generate an interrupt through an external control signal device, the triggering interrupt process is carried out in a user mode, and after the interrupt occurs, the target CPU core executes a self-defined interrupt processing flow without triggering rescheduling through a kernel scheduler, the method can quickly return to the designated message transceiving flow from the kernel state, the whole process is efficient and reliable, the response speed of message transceiving between different CPU core tasks in the system is improved, the response time of message transceiving between the CPU cores is shortened, and the real-time performance of the 5G base station system can be effectively improved under the high-load state of the CPU.

Based on the content of the foregoing embodiment, the interrupt triggering module 420 is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a general input/output pin on a target CPU core according to the interrupt operation instruction value;

and triggering the target CPU core to interrupt after the general input/output pin on the target CPU core receives the control signal.

Specifically, after writing the message into the user space message queue, the interrupt triggering module 420 executes the operation of the write control signal device, and triggers the target CPU core where the target task is located to generate an interrupt, thereby interrupting the task execution of the target CPU core.

In this embodiment, the interrupt triggering module 420 writes an interrupt operation instruction value into the control signal device by executing an operation of writing the control signal device, and after receiving the interrupt operation instruction value, the control signal device sends a control signal to a general purpose input output GPIO pin on the affinity CPU core corresponding to the interrupt operation instruction value, where the affinity CPU core is a target CPU core, and after receiving the control signal, the GPIO pin on the target CPU core triggers an interrupt to interrupt operation of the target CPU core.

For example, the interrupt operation instruction value is an 8-bit value, each bit of the value corresponds to a pin on the CPU, and each pin corresponds to an interrupt on the trigger affinity CPU core.

In this embodiment, an implementation manner is provided in which the interrupt trigger module 420 executes the operation of the write control signal device to trigger the target CPU core to generate the interrupt, the target CPU core is triggered to be interrupted by controlling a pin on the target CPU core through the write control signal device in the user space, the interrupt is triggered by using the above hardware manner, the efficiency is high, and entry into the kernel space through system call is avoided, so that the task execution after the interrupt can avoid the scheduling of the Linux kernel scheduler, and the timeliness of the task execution of the target CPU can be effectively improved.

In another embodiment of the present invention, based on the above embodiment, the interrupt triggering module 420 is specifically configured to:

writing an interrupt operation instruction value into the control signal device so that the control signal device sends a control signal to a Peripheral Component Interconnect Express (PCIE) interface according to the interrupt operation instruction value;

and after receiving the control signal, the PCIE interface triggers the target CPU core to generate interruption.

Specifically, this embodiment provides another implementation manner in which the interrupt triggering module 420 performs the operation of the write control signal device to trigger the target CPU core to generate the interrupt. The interrupt trigger module 420 writes an interrupt operation instruction value into a control signal device by executing an operation of writing the control signal device, the control signal device sends a control signal to a Peripheral Component Interface Express (PCIE) interface after receiving the interrupt operation instruction value, the PCIE interface sends an interrupt request to an affinity CPU core corresponding to the interrupt operation instruction value, the affinity CPU core is a target CPU core, the target CPU core sends an interrupt response to the PCIE interface after receiving the interrupt request, the PCIE interface returns an interrupt vector value to the target CPU core, the target CPU core searches a corresponding interrupt service program in a memory according to the interrupt vector value, then reads the corresponding interrupt service program, and further processes the interrupt.

According to the device for realizing the inter-CPU-core interrupt communication under the Linux, the PCIE interface is controlled to trigger the target CPU core interrupt by writing the control signal device in the user space, the interrupt is triggered by adopting the hardware mode, the efficiency is high, the situation that the interrupt enters the kernel space through system calling is avoided, the task execution after the interrupt can avoid the scheduling of a Linux kernel scheduler, and the timeliness of the target CPU task execution can be effectively improved.

Based on the content of the foregoing embodiment, the interrupt processing module 430 is specifically configured to:

storing the context of the interrupted task, and searching the context corresponding to the target task;

and if the context corresponding to the target task is found, directly jumping to the target task.

Specifically, the interrupt processing module 430 is configured to execute a custom kernel interrupt processing flow after the target CPU core is interrupted, first store the context of the interrupted task, and then articulate the interrupted task, then search for the context corresponding to the target task, and if the context corresponding to the target task is found, directly skip to the target task and execute the target task.

According to the device for realizing the inter-CPU core interrupt communication under the Linux, the target CPU core executes the custom kernel interrupt processing flow, the dispatching of a Linux kernel scheduler is avoided, the target CPU core directly executes the target task, and the timeliness of the inter-task message transmission is improved.

Based on the content of the above embodiments, the control signal device is specifically an erasable programmable logic device EPLD register.

Specifically, the control signal Device is used to issue a control signal to trigger the target CPU core to generate an interrupt, and in this embodiment, the control signal Device may be an EPLD (Erasable Programmable Logic Device) register.

It should be noted that the EPLD register is optional, and the control signal device may also be other devices capable of sending out a control signal, such as an FPGA (Field Programmable Gate Array).

The device for realizing the inter-CPU-core interrupt communication under the Linux provided by the embodiment of the invention triggers the target CPU core where the target task is located to generate the interrupt and is completed by the EPLD, belongs to a hardware behavior action, and further improves the operation efficiency.

Fig. 5 is a schematic entity structure diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 5, the electronic device may include: a processor (processor)510, a communication Interface (Communications Interface)520, a memory (memory)530 and a communication bus 540, wherein the processor 510, the communication Interface 520 and the memory 530 communicate with each other via the communication bus 540. The processor 510 may call a computer program stored in the memory 530 and executable on the processor 510 to execute the method for implementing inter-CPU core interrupt communication under Linux provided by the above-mentioned method embodiments, for example, including: executing the operation of sending a message to a target task in a user space, and writing the message into a user space message queue; executing the operation of a writing control signal device, and triggering a target CPU core where the target task is located to generate interruption; executing a custom kernel interrupt processing flow to enable the target CPU core to directly jump to the target task; and reading the message from the user space message queue.

Furthermore, the logic instructions in the memory 530 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The embodiment of the present invention further provides a non-transitory computer readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for implementing inter-CPU core interrupt communication under Linux provided in the above-mentioned method embodiments, for example, including: executing the operation of sending a message to a target task in a user space, and writing the message into a user space message queue; executing the operation of a writing control signal device, and triggering a target CPU core where the target task is located to generate interruption; executing a custom kernel interrupt processing flow to enable the target CPU core to directly jump to the target task; and reading the message from the user space message queue.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.