阅读说明：本技术 一种计算装置 (Computing device ) 是由 曾耿华 王渊 邹小波 于 2021-06-30 设计创作，主要内容包括：本发明实施例提供了一种计算装置,包括：第一芯片,和围绕设置在所述第一芯片周围的若干个第二芯片,其中,所述第一芯片和所述第二芯片均设置在所述第一板卡上；第三芯片,和围绕设置在所述第三芯片周围的若干个第四芯片,其中,所述第三芯片和所述第四芯片均设置在所述第一板卡上；所述第一板卡与所述第二板卡连接；这样,本发明实施例能在保持小体积的情况下具备高性能,通过紧凑的布局和双板的结构设计,实现了放置更多芯片的功能。(An embodiment of the present invention provides a computing apparatus, including: the first chip and the second chips are arranged around the first chip in a surrounding mode, wherein the first chip and the second chips are arranged on the first board card; the first board card comprises a third chip and a plurality of fourth chips arranged around the third chip in a surrounding manner, wherein the third chip and the fourth chips are both arranged on the first board card; the first board card is connected with the second board card; therefore, the embodiment of the invention has high performance under the condition of keeping small volume, and realizes the function of placing more chips through compact layout and double-plate structural design.)

1. A computing device, comprising:

the chip packaging structure comprises a first chip (1) and a plurality of second chips (2) arranged around the first chip (1), wherein the first chip (1) and the second chips (2) are arranged on a first board card (3);

the circuit board comprises a third chip (4) and a plurality of fourth chips (5) arranged around the third chip (4), wherein the third chip (4) and the fourth chips (5) are arranged on the first board card (3);

the first board card (3) is connected with the second board card (6).

2. A computing device according to claim 1, characterized in that the first board (3) and the second board (6) are connected by means of a flexible board (7).

3. A computing device according to claim 1, characterized in that a first power supply module (8) is arranged on the first board (3), the first power supply module (8) and the second chip (2) being arranged around the first chip (1);

and a second power supply module (9) is arranged on the second board card (6), and the second power supply module (9) and the fourth chip (5) are arranged around the third chip (4).

4. A computing device according to claim 1, characterised in that high speed signal areas (10) are provided on both the first board (3) and the second board (6), wherein,

a first power supply module (8) area on the first board card (3) and a high-speed signal area (10) on the first board card (3) are arranged separately from each other;

the area of a second power supply module (9) on the second board card (6) and the area of a high-speed signal (10) on the second board card (6) are arranged separately from each other.

5. A computing device according to claim 4, characterised in that the high speed signal area (10) on the first board (3) is arranged between the first power supply module (8) area and the first chip (1);

the second power module (9) area on the second board card (6) is arranged between the second power module (9) area and the second chip (2).

6. A computing device as claimed in claim 1, characterized in that said first board (3) and said second board (6) are of a laminated structure, and that power supply layers are provided on said first board (3) and on said second board (6).

7. A computing device according to claim 1, characterized in that the power supply topology of the first power supply module (8) or the second power supply module (9) are each provided with a converter module and a voltage regulator module connected in series with each other.

8. The computing device of claim 6, wherein the VDD port of the converter module and/or the VDD port of the voltage regulator module are each grounded via a capacitor bank, wherein the capacitor bank comprises a first capacitor and a second capacitor arranged in parallel, and wherein a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor.

Technical Field

The present invention relates to computing devices, and particularly to a computing device.

Background

There are many architectures of computing devices, such as CPU-centric, ARM-centric, GPU-centric, FPGA-centric, with their own advantages and limitations for different applications.

For communication and radar application occasions, the signal frequency is high, and the real-time requirement is strong, so that an FPGA with parallel computing capability and a peripheral high-bandwidth data interface are needed. But a high computational power FPGA means that a larger size chip is required to accommodate more computational units, which also results in greater power consumption. Meanwhile, the high bandwidth means more signal connections, which results in the increase of the size of the trace, the occupation of the placement space of the chip, and the reduction of the performance density of the device.

Disclosure of Invention

To solve the above technical problem, embodiments of the present invention provide a computing device for solving the problems of miniaturization and realization of high performance density of the computing device.

In order to achieve the purpose, the technical scheme of the embodiment of the invention is realized as follows:

an embodiment of the present invention provides a computing device, including:

the first chip and the second chips are arranged around the first chip in a surrounding mode, wherein the first chip and the second chips are arranged on the first board card;

the first board card comprises a third chip and a plurality of fourth chips arranged around the third chip in a surrounding manner, wherein the third chip and the fourth chips are both arranged on the first board card;

the first board card is connected with the second board card.

In the embodiment of the present invention, the first board card and the second board card are connected by a flexible board.

In the embodiment of the invention, a first power module is arranged on the first board card, and the first power module and the second chip are arranged around the first chip;

and a second power supply module is arranged on the second board card, and the second power supply module and the fourth chip are arranged around the third chip.

In the embodiment of the present invention, the first board card and the second board card are both provided with high-speed signal areas, wherein,

a first power module area on the first board card and a high-speed signal area on the first board card are arranged separately from each other;

and a second power module area on the second board card and a high-speed signal area on the second board card are arranged separately from each other.

In the embodiment of the present invention, a high-speed signal area on the first board card is disposed between the first power module area and the first chip;

and a second power module area on the second board card is arranged between the second power module area and the second chip.

In the embodiment of the invention, the first board card and the second board card are both of a laminated structure, and the first board card and the second board card are both provided with power supply layers.

In the embodiment of the present invention, the power topology of the first power module or the second power module is respectively provided with a converter module and a voltage stabilizing module which are connected in series with each other.

In an embodiment of the present invention, the VDD port of the converter module and/or the VDD port of the voltage stabilizing module are both grounded through a capacitor bank, where the capacitor bank includes a first capacitor and a second capacitor arranged in parallel, and a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor.

An embodiment of the present invention provides a computing apparatus, including: the first chip and the second chips are arranged around the first chip in a surrounding mode, wherein the first chip and the second chips are arranged on the first board card; the first board card comprises a third chip and a plurality of fourth chips arranged around the third chip in a surrounding manner, wherein the third chip and the fourth chips are both arranged on the first board card; the first board card is connected with the second board card; therefore, the embodiment of the invention has high performance under the condition of keeping small volume, and realizes the function of placing more chips through compact layout and double-plate structural design.

Drawings

Fig. 1 is a schematic structural diagram of a computing device according to an embodiment of the present invention;

fig. 2 is a layout diagram of a first power module or a second power module according to an embodiment of the invention;

fig. 3 is a power supply topology diagram of the first power supply module or the second power supply module according to the embodiment of the invention;

fig. 4 is a diagram of a decoupling scheme of the first power module or the second power module according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

At present, in the prior art, a scheme of adding an AD/DA chip to a conventional FPGA chip is designed based on chassis architectures such as VPX and CPCI, and occasions using the product are communication and radar occasions, and the size is not a key influence factor for ground application scenes. But for portable devices, on-board applications, the volume will be limited and the volume of conventional VPX and CPCI will no longer be acceptable; meanwhile, the device has larger volume, so that the weight of the computing device is heavier, and the device has obvious disadvantages on occasions with strict requirements on weight, such as portability, airborne performance and the like. The number of chips is reduced by adopting a small-sized architecture design for reducing the size, so that the performance density of the whole computing device is reduced, and the requirements of computing resources, high bandwidth, high speed and the like required by high performance cannot be met.

For a computing device with an FPGA chip and an AD/DA chip, computing resources, bandwidth, channel number and working frequency are all embodied in high performance. Intuitively, the more chips and the higher the speed, the better the performance. In order to realize high performance, the invention adopts methods of reasonable layout, optimized power network design, optimized signal network design and the like.

An embodiment of the present invention provides a computing device, as shown in fig. 1, including a first board card 3 and a second board card 6, where the first board card 3 and the second board card 6 are connected by a flexible board 7, and the first board card 3 and the second board card 6 are mounted back to back. Specifically, the heat dissipation surfaces of the first board card 3 and the second board card 6 face to two sides, the contact area between the chip heat dissipation surface and the surface of the housing is the largest, the path is the smallest, and the heat transfer efficiency is the highest according to a heat transfer formula. The first board card 3 and the second board card may be the same or different, and the first board card 3 and the second board card may be circuit boards.

Specifically, a first chip 1, a second chip 2 and a first power module 8 are arranged on the first board card 3, wherein, the first chip 1 is arranged at the center of the first board card 3, the first chip 1 includes but is not limited to an FPGA chip, the second chip 2 has a plurality of chips, and particularly, the second chip 2 includes, but is not limited to, a digital-to-analog conversion chip and a digital signal processing module, and more particularly, the second chip 2 comprises a DA chip 1 (digital-to-analog conversion chip), a DA chip 2 (digital-to-analog conversion chip) and a DSP chip (digital signal processing module), the DA chip 1 and the DA chip 2 are arranged above the first chip 1, the DSP chip is arranged close to the flexible board 7 and on the upper right of the first chip 1, the first power module 8 is arranged on the left side of the first chip 1, and the left side of the first board card 3 is connected with the second board card 6 through the flexible board 7.

The right side of the second board card 6 is connected to the flexible board 7, the second board card 6 is provided with a third chip 4, a fourth chip 5 and a second power module 9, the third chip 4 is arranged at the center of the second board card 6, the third chip 4 includes but is not limited to an FPGA chip, the fourth chip 5 includes but is not limited to an analog-to-digital conversion chip, and more specifically, the fourth chip 5 includes an AD chip 1 (analog-to-digital conversion chip), an AD chip 2 (analog-to-digital conversion chip), an AD chip 3 (analog-to-digital conversion chip), an AD chip 4 (analog-to-digital conversion chip), an AD chip 5 (analog-to-digital conversion chip), an AD chip 6 (analog-to-digital conversion chip), an AD chip 7 (analog-to-digital conversion chip) and an AD chip 8 (analog-to-digital conversion chip), wherein the AD chip 1, the AD chip 2, the AD chip 4 (analog-to-digital conversion chip), and the AD chip 8 (analog-to-digital conversion chip) are included in the same chip, AD chip 3 and AD chip 4 set up the top of third chip 4, and AD chip 5, AD chip 6, AD chip 7 and AD chip 8 set up the below of third chip 4, second power module 9 and a plurality of fourth chip 5 is around setting up around third chip 4, specifically, second power module 9 sets up the right side of third chip 4.

Therefore, the chip is limited by the size and the area, the chip is divided into two board cards according to the connection relation, a back-to-back installation mode is adopted, the radiating surfaces face to two sides, the contact area between the chip radiating surface and the surface of the shell is the largest, the path is the smallest, and the heat transfer efficiency is the highest according to a heat transfer formula. The FPGA (namely the first chip 1 or the second chip 2) is used as a calculation center and is placed in the center of the board card, all peripheral resources are tightly distributed around the FPGA, and the layout mode is favorable for the principle that signal routing partitions and high-speed wire routing are shortest, so that the interference among signals can be reduced, the signal loss can be reduced, and the transmission bandwidth of the signals can be further improved. The power source is used as an interference source and is placed on the outer side of the board card, a large number of combined capacitors are placed between the power source and the power utilization chip, and the function of filtering high-frequency, medium-frequency and low-frequency noise is taken into consideration.

It should be noted here that the first chip 1, the second chip 2, the third chip 4, and the fourth chip 5 may be any chips. According to the embodiment of the invention, the reasonable layout is generated by adjusting the arrangement positions of the chips on the first board card 3 or the second board card 6, so that the interference among the chips is reduced, the degree of signal loss is reduced, and the transmission bandwidth of signals is improved.

Furthermore, in the embodiment of the present invention, since the density of each chip on the board card is very high, the space reserved for routing the power module is small, and limited by the size, and sufficient power rails cannot be provided for a plurality of chips or modules to supply power, different power supplies can only be combined, but noise of different power rails interferes with each other after combination, thereby affecting the performance of the chip.

Therefore, on one hand, the embodiment of the invention filters out high-frequency noise on a power rail by adopting a laminated design for a power supply and further fully utilizing parasitic capacitance between a power supply plane and a ground plane, and simultaneously, because noise on an isolated power supply of the ground plane cannot be connected into a signal line from a line path, the safety of the signal line is protected.

Specifically, the first board card 3 and the second board card 6 are both of a stacked structure, and the first board card 3 and the second board card 6 both include power supply layers, that is, as shown in fig. 2, the board card structure has 17 layers, where the power supply layers are at the 9 th layer and the 10 th layer, and here, it should be noted that the number of stacked layers is determined by the number of signals, the number of chips of the computing device is large, the number of signals is also large, and therefore the number of signal stacked layers is also large.

On the other hand, although the ground plane protects the lines from interference, the noise on the power plane is eventually transmitted to the power consumption chip, and although the power supply rejection ratio of the power consumption chip can attenuate the noise from the power supply to a certain extent, for a high performance chip (for example, a converter chip), the signal-to-noise ratio is often required to be high, and under such a requirement, the power supply rejection capability of the chip itself cannot meet a predetermined requirement.

Therefore, an embodiment of the present invention provides a power supply topology, as shown in fig. 3, including a converter module and a voltage stabilization module, specifically, a VDD port and an EN port of the converter module are both connected to a power supply positive electrode (Vbatt), and the power supply positive electrode is further grounded through a capacitor, a switch port and an FB port of the converter module are both connected to a first post-stabilization voltage output terminal, the first post-stabilization voltage output terminal is connected to a pre-stabilization voltage input terminal, the pre-stabilization voltage input terminal is connected to the VDD port and the EN port of the voltage stabilization module, and an OUT port and an FB port of the voltage stabilization module are connected to a second post-stabilization voltage output terminal.

Preferably, the converter module is a DC/DC chip, so that for a non-sensitive power utilization chip, the DC/DC chip is adopted to directly supply power, the efficiency is high, and the space is small. The converter module is an LDO chip, and for the ADDA chip type sensitive power utilization chip, the LDO chip is used for supplying power, so that noise on a sensitive circuit can be effectively attenuated.

In addition, the embodiment of the invention enables the system to have a lower impedance value in the whole frequency range through the resistor group, wherein the large capacitor loads a low frequency range, the small capacitor loads a high frequency range, and further the whole frequency range is covered. The method provides better filtering performance, specifically, as shown in fig. 4, the VDD port shown in the figure may be a VDD port on the converter module or a VDD port on the voltage regulator module, the VDD port is grounded through a capacitor bank, the capacitor bank includes a first capacitor and a second capacitor arranged in parallel, where the number of the first capacitor and the second capacitor may be multiple, and the capacitance value of the first capacitor is greater than that of the second capacitor.

Further, in the embodiment of the present invention, as shown in fig. 1, a high-speed signal area 10 on the first board card 3 is disposed between the first power module 8 area and the first chip 1; the second power module 9 area on the second board card 6 is arranged between the second power module 9 area and the second chip 2.

Therefore, when the circuit is used, a design scheme of key signals and power supply partitions is adopted, the key signals are prevented from passing through a high-noise power supply area by the design scheme, the signal transmission quality is ensured, the signal lines are strictly designed according to controllable impedance, the signal integrity of the whole link is ensured, and the signals can stably run at a high transmission speed.

The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and these modifications and adaptations should be considered within the scope of the invention.