Self-calibration composite structure ADC

文档序号：1365704 发布日期：2020-08-11 浏览：5次中文

阅读说明：本技术 一种自校准复合结构adc (Self-calibration composite structure ADC ) 是由陈功郭函曾雪李�浩张涛凌味未石跃李蠡董倩宇于 2020-06-16 设计创作，主要内容包括：本发明公开了一种自校准复合结构ADC,采用动态比较器替代传统普通型比较器,无静态直流功耗,大大降低了ADC整体功耗；考虑到ADC测量误差主要来源于具体工艺生产出的电容的容值与设计的容值之间的误差,增设了电容自校准模块,通过电容自校准模块对电容性数模转换模块的内部电容进行校准；采用全并行4位模数转换模块直接对模拟信号进行粗量化,得到高位数字信号,协同电容性数模转换模块与动态比较器的逐次比较环节,大大节省逐次比较的时间,提高ADC量化编码的速度,得以实现高速、高精度和低功耗的性能。(The invention discloses a self-calibration composite structure ADC, which adopts a dynamic comparator to replace a traditional common comparator, has no static direct current power consumption, and greatly reduces the overall power consumption of the ADC; considering that ADC measurement errors mainly come from errors between capacitance values of capacitors produced by a specific process and designed capacitance values, a capacitor self-calibration module is additionally arranged, and internal capacitors of the capacitive digital-to-analog conversion module are calibrated through the capacitor self-calibration module; the full-parallel 4-bit analog-to-digital conversion module is adopted to directly carry out coarse quantization on the analog signal to obtain a high-bit digital signal, and the successive comparison link of the capacitive digital-to-analog conversion module and the dynamic comparator is cooperated, so that the successive comparison time is greatly saved, the ADC quantization coding speed is improved, and the performances of high speed, high precision and low power consumption can be realized.)

1. A self-calibrating, composite-structured ADC, comprising: the circuit comprises a capacitor self-calibration module U1, a dynamic comparator U2, a capacitive digital-to-analog conversion module U3, a full-parallel 4-bit analog-to-digital conversion module U4, a D trigger U5, a D trigger U6, a D trigger U7, a D trigger U8, a main control module U9, a CMOS complementary switch SW1, a CMOS complementary switch SW2, a gate voltage bootstrap switch SW3, a single-pole double-throw switch SW4 and a sampling capacitor Cs;

the clock signal CLK input end of the dynamic comparator U2 is respectively connected with the clock signal CLK input end of the main control module U9 and the clock signal CLK input end of the fully parallel 4-bit analog-to-digital conversion module and is used as the clock signal CLK input end of the self-calibration composite structure ADC; the reference voltage Vref input end of the capacitor self-calibration module U1 is respectively connected with the reference voltage Vref input end of the capacitive digital-to-analog conversion module U3 and the reference voltage Vref input end of the fully-parallel 4-bit analog-to-digital conversion module U4 and is used as the reference voltage Vref input end of the self-calibration composite structure ADC; the communication end a of the CMOS complementary switch SW1 is connected with the communication end a of the CMOS complementary switch SW2 and serves as the common-mode voltage Vcm input end of the self-calibration composite structure ADC; the input end a of the grid voltage bootstrap switch SW3 is used as the analog voltage Vin input end of the self-calibration composite structure ADC; the output end of the digital signal Dout [13:0] of the main control module U9 is used as the output end of the digital signal Dout [13:0] of the self-calibration composite structure ADC; the power supply end VDD of the capacitor self-calibration module U1 is respectively connected with the power supply end VDD of the dynamic comparator U2, the power supply end VDD of the capacitive digital-to-analog conversion module U3, the power supply end VDD of the full-parallel 4-bit analog-to-digital conversion module U4, the power supply ends VDD of the D triggers U5-U8, the power supply end VDD of the main control module U9, the power supply end VDD of the CMOS complementary switch SW1, the power supply end VDD of the CMOS complementary switch SW2, the power supply end VDD of the grid voltage bootstrap switch SW3 and the power supply end VDD of the single-pole double-throw switch SW4, and is used as the power supply end VDD of the ADC with a self-calibration composite structure; the common end GND of the capacitor self-calibration module U1 is respectively connected with the common end GND of the dynamic comparator U2, the common end GND of the capacitive digital-to-analog conversion module U3, the common end GND of the fully-parallel 4-bit analog-to-digital conversion module U4, the common ends GND of the D triggers U5-U8, the common end GND of the main control module U9, the common end GND of the CMOS complementary switch SW1, the common end GND of the CMOS complementary switch SW2, the common end GND of the gate voltage bootstrap switch SW3, the common end GND of the single-pole double-throw switch SW4 and one end of the sampling capacitor Cs, and is used as the common end GND of the self-calibration composite structure ADC and grounded; the input end of a calibration control bit signal Cal [6:0] of the capacitor self-calibration module U1 is connected with the output end of a calibration control bit signal Cal [6:0] of the main control module U9; the analog signal Vasc end of the capacitor self-calibration module U1 is respectively connected with the communication end b of the CMOS complementary switch SW1 and the selectable end b of the single-pole double-throw switch SW 4; the control end ctl of the CMOS complementary switch SW1 is connected with the output end of a second self-calibration control signal SC2 of the main control module U9; the selectable end a of the single-pole double-throw switch SW4 is respectively connected with the output end b of the gate voltage bootstrap switch SW3, the other end of the sampling capacitor Cs and the input end of a sampling voltage signal Vs of the fully-parallel 4-bit analog-to-digital conversion module U4; the fixed end c of the single-pole double-throw switch SW4 is connected with the non-inverting input end of the dynamic comparator U2; the control end ctl of the single-pole double-throw switch SW4 and the input end of a first self-calibration control signal SC1 of the capacitive digital-to-analog conversion module U3 are both connected with the output end of a first self-calibration control signal SC1 of the main control module U9; the control end ctl of the gate voltage bootstrap switch SW3 is connected with the output end of a sampling control signal SP of the main control module U9; the communication end b of the CMOS complementary switch SW2 is respectively connected with the analog signal Vas end of the capacitive digital-to-analog conversion module and the inverting input end of the dynamic comparator U2; the control end ctl of the CMOS complementary switch SW2 is connected with the output end of a third self-calibration control signal SC3 of the main control module U9; the output end of the dynamic comparator U2 is connected with the input end of a comparison signal COMP of the main control module U9; the output end of a third BIT signal BIT3 of the fully parallel 4-BIT analog-to-digital conversion module U4 is connected with the input end D of a D flip-flop U5, the output end of a second BIT signal BIT2 is connected with the input end D of a D flip-flop U6, the output end of a first BIT signal BIT1 is connected with the input end D of a D flip-flop U7, and the output end of a first BIT signal BIT0 is connected with the input end D of a D flip-flop U8; the clock signal clk input end of the D flip-flop U5 is respectively connected with the clock signal clk input end of the D flip-flop U6, the clock signal clk input end of the D flip-flop U7, the clock signal clk input end of the D flip-flop U8, the high 4-bit enable control signal SB output end of the main control module U9 and the high 4-bit enable control signal SB input end of the capacitive digital-to-analog conversion module U3; the output end Q of the D flip-flop U5 is respectively connected with the input end of a buffer signal b13 of the capacitive digital-to-analog conversion module U3 and the input end of a buffer signal b13 of the main control module U9; the output end Q of the D flip-flop U6 is respectively connected with the input end of a buffer signal b12 of the capacitive digital-to-analog conversion module U3 and the input end of a buffer signal b12 of the main control module U9; the output end Q of the D flip-flop U7 is respectively connected with the input end of a buffer signal b11 of the capacitive digital-to-analog conversion module U3 and the input end of a buffer signal b11 of the main control module U9; the output end Q of the D flip-flop U8 is respectively connected with the input end of a buffer signal b10 of the capacitive digital-to-analog conversion module U3 and the input end of a buffer signal b10 of the main control module U9; the reset signal RST input end of the capacitive digital-to-analog conversion module U3 is connected with the reset signal RST output end of the main control module U9; the input end of a capacitance control bit signal Ctlb [13:0] of the capacitive digital-to-analog conversion module U3 is connected with the output end of a capacitance control bit signal Ctlb [13:0] of the main control module U9;

the fully parallel 4-bit analog-to-digital conversion module U4 is an SMIC130nm process CMOS integrated circuit, is used for directly quantizing a sampling voltage signal Vs through a reference voltage Vref, obtains buffer signals b13-b10 of 13-10-bit digital signals Dout [13:10] under the action of a D trigger U5-U8, transmits the buffer signals b13-b10 to a main control module U9, buffers the digital signals Dout [13:10], and simultaneously transmits the buffer signals B13-b to a capacitive digital-to-analog conversion module U3 to assist successive comparison; the capacitive digital-to-analog conversion module U3 is an SMIC130nm process CMOS integrated circuit, and is used for carrying out successive comparison on a sampling voltage signal Vs through a reference voltage Vref under the control of a main control module U9, forming an approach voltage at the inverting input end of a dynamic comparator U2, enabling the dynamic comparator U2 to successively obtain a corresponding comparison signal COMP, and obtaining a 9-0 bit digital signal Dout [9:0] under the cooperation of the main control module U9; the capacitance self-calibration module U1 is an SMIC130nm process CMOS integrated circuit and is used for calibrating the internal capacitance of the capacitive digital-to-analog conversion module U3; the main control module U9 is an ASIC, which is an CMOS sequential logic Application Specific Integrated Circuit (ASIC) in the SMIC130nm process, and is configured to control the capacitance self-calibration module U1 to calibrate the internal capacitance of the capacitive digital-to-analog conversion module U3; controlling successive comparisons of the capacitive digital-to-analog conversion module U3; the digital signals Dout [13:10] provided by the fully parallel 4-bit analog-to-digital conversion module U4 and the digital signals Dout [9:0] obtained by the capacitive digital-to-analog conversion module U3 in cooperation with the dynamic comparator U2 are spliced to obtain the entire 14-bit digital signals Dout [13:0 ].

2. The self-calibrating, composite-structured ADC of claim 1, wherein said capacitive digital-to-analog conversion module U3 includes: capacitors C0-C14, a bridge capacitor Cp, single-pole double-throw switches SW100-SW113, single-pole double-throw switches SW120-SW123, a CMOS complementary switch SW114, a CMOS complementary switch SW115 and AND gates U10-U13;

one end of the capacitor C7 is connected to one end of the capacitor C8, one end of the capacitor C9, one end of the capacitor C10, one end of the capacitor C11, one end of the capacitor C12, one end of the capacitor C13, one end of the bridge capacitor Cp, and the connection end b of the CMOS complementary switch SW115, and is used as an analog signal Vas end of the capacitive digital-to-analog conversion module U3; the other end of the capacitor C7 is connected with the fixed end C of the single-pole double-throw switch SW 107; the other end of the capacitor C8 is connected with the fixed end C of the single-pole double-throw switch SW 108; the other end of the capacitor C9 is connected with the fixed end C of the single-pole double-throw switch SW 109; the other end of the capacitor C10 is connected with the fixed end C of the single-pole double-throw switch SW 110; the other end of the capacitor C11 is connected with the fixed end C of the single-pole double-throw switch SW 111; the other end of the capacitor C12 is connected with the fixed end C of the single-pole double-throw switch SW 112; the other end of the capacitor C13 is connected with the fixed end C of the single-pole double-throw switch SW 113; one end of the capacitor C0 is respectively connected with one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4, one end of the capacitor C5, one end of the capacitor C6, the other end of the bridging capacitor Cp, one end of the capacitor C14 and the communication end a of the CMOS complementary switch SW 114; the other end of the capacitor C0 is connected with the fixed end C of the single-pole double-throw switch SW 100; the other end of the capacitor C1 is connected with the fixed end C of the single-pole double-throw switch SW 101; the other end of the capacitor C2 is connected with the fixed end C of the single-pole double-throw switch SW 102; the other end of the capacitor C3 is connected with the fixed end C of the single-pole double-throw switch SW 103; the other end of the capacitor C4 is connected with the fixed end C of the single-pole double-throw switch SW 104; the other end of the capacitor C5 is connected with the fixed end C of the single-pole double-throw switch SW 105; the other end of the capacitor C6 is connected with the fixed end C of the single-pole double-throw switch SW 106; the control end ctl of the CMOS complementary switch SW114 is connected with the control end ctl of the CMOS complementary switch SW115 and serves as an input end of a reset signal RST of the capacitive digital-to-analog conversion module U3; the power supply end VDD of the CMOS complementary switch SW114 is respectively connected with the power supply ends VDD of the single-pole double-throw switches SW100-SW113, the power supply end VDD of the CMOS complementary switch SW115, the power supply ends VDD of the single-pole double-throw switches SW120-SW123 and the power supply end VDD of the AND gate U10-U13 and serves as the power supply end VDD of the capacitive digital-to-analog conversion module U3; the other end of the capacitor C14 is respectively connected with a communication end b of the CMOS complementary switch SW114, a common end GND of the CMOS complementary switch SW114, a communication end a of the CMOS complementary switch SW115, a common end GND of the single-pole double-throw switches SW100-SW113, a common end GND of the single-pole double-throw switches SW120-SW123, a common end GND of the AND gates U10-U13, an optional end b of the single-pole double-throw switches SW100-SW109 and an optional end b of the single-pole double-throw switches SW120-SW123, and is used as a common end GND of the capacitive digital-to-analog conversion module U3; the selectable end b of the single-pole double-throw switch SW110 is connected with the fixed end c of the single-pole double-throw switch SW 120; the selectable end b of the single-pole double-throw switch SW111 is connected with the fixed end c of the single-pole double-throw switch SW 121; the selectable end b of the single-pole double-throw switch SW12 is connected with the fixed end c of the single-pole double-throw switch SW 122; the selectable end b of the single-pole double-throw switch SW113 is connected with the fixed end c of the single-pole double-throw switch SW 123; the selectable end a of the single-pole double-throw switch SW110 is connected with the output end Vout of the AND gate U10; the selectable end a of the single-pole double-throw switch SW111 is connected with the output end Vout of the AND gate U11; the selectable end a of the single-pole double-throw switch SW112 is connected with the output end Vout of the AND gate U12; the selectable end a of the single-pole double-throw switch SW113 is connected with the output end Vout of the AND gate U13; the control end ctl of the single-pole double-throw switch SW110 is respectively connected with the control ends ctl of the single-pole double-throw switches SW111-SW113 and serves as a first self-calibration control signal SC1 input end of the capacitive digital-to-analog conversion module U3; the selectable end a of the single-pole double-throw switch SW100 is respectively connected with the selectable ends a of the single-pole double-throw switches SW101 to SW109 and the selectable ends a of the single-pole double-throw switches SW120 to SW123 and is used as the reference voltage Vref input end of the capacitive digital-to-analog conversion module U3; the control ends ctl of the single-pole double-throw switches SW100-SW109 and the single-pole double-throw switches SW120-SW123 are respectively and sequentially used as the input ends of capacitance control bit signals Ctlb [0] -Ctlb [13] of the capacitive digital-to-analog conversion module U3; an input end Vin2 of the and gate U10 is respectively connected with input ends Vin2 of the and gates U11-U13, and is used as an input end of a high-4-bit enable control signal SB of the capacitive digital-to-analog conversion module U3; the respective input terminals Vin1 of the and gates U10-U13 are sequentially used as the input terminals of the buffer signals b10-b13 of the capacitive digital-to-analog conversion module U3, respectively.

3. The self-calibrating composite-structured ADC of claim 2, wherein said capacitance self-calibrating module U1 comprises: capacitors C100-C107 and single-pole double-throw switches SW200-SW 206;

one end of the capacitor C100 is connected with one ends of the capacitors C101-C107 respectively and serves as an analog signal Vasc end of the capacitor self-calibration module U1; the other end of the capacitor C100 is connected with a fixed end C of a single-pole double-throw switch SW 200; the other end of the capacitor C101 is connected with a fixed end C of a single-pole double-throw switch SW 201; the other end of the capacitor C102 is connected with a fixed end C of a single-pole double-throw switch SW 202; the other end of the capacitor C103 is connected with a fixed end C of a single-pole double-throw switch SW 203; the other end of the capacitor C104 is connected with a fixed end C of the single-pole double-throw switch SW 204; the other end of the capacitor C105 is connected with a fixed end C of a single-pole double-throw switch SW 205; the other end of the capacitor C106 is connected with a fixed end C of a single-pole double-throw switch SW 206; the power supply end VDD of the single-pole double-throw switch SW200 is respectively connected with the power supply ends VDD of the single-pole double-throw switches SW201 to SW206, and is used as the power supply end VDD of the capacitor self-calibration module U1 and the power supply end VDD of the capacitor self-calibration module U1; the common end GND of the single-pole double-throw switch SW200 is respectively connected with the common end GND of the single-pole double-throw switches SW201 to SW206, the selectable end b of the single-pole double-throw switches SW200 to SW206 and the other end of the capacitor C107 and serves as the common end GND of the capacitor self-calibration module U1; the selectable end a of the single-pole double-throw switch SW200 is respectively connected with the selectable ends a of the single-pole double-throw switches SW201 to SW206 and is used as a reference voltage Vref input end of a capacitor self-calibration module U1; respective control terminals ctl of the single-pole double-throw switches SW200-SW206 are sequentially used as input terminals of calibration control bit signals Cal [6] -Cal [0] of the capacitor self-calibration module U1.

4. The self-calibrating, composite-structured ADC of claim 1, wherein said fully parallel 4-bit analog-to-digital conversion module U4 includes: 16 PMOS tubes, 15 dynamic comparators and thermometer code decoder U116;

the power supply end VDD of the thermometer code decoder U116 is respectively connected with the power supply ends VDD of the 15 dynamic comparators and is used as the power supply end VDD of the full-parallel 4-bit analog-to-digital conversion module U4; the common end GND of the thermometer code decoder U116 is respectively connected with the common ends GND of the 15 dynamic comparators and is used as the common end GND of the fully parallel 4-bit analog-to-digital conversion module U4; the source electrode of the 1 st PMOS tube M101 is connected with the grid electrode thereof and is used as the reference voltage Vref input end of a full parallel 4-bit analog-to-digital conversion module U4; the source electrode of the nth PMOS tube is respectively connected with the grid electrode of the nth PMOS tube, the drain electrode of the (n-1) th PMOS tube M and the inverted input end of the (n-1) th comparator, and n is more than or equal to 1 and less than or equal to 16; the drain electrode of the 16 th PMOS tube M116 is grounded; the non-inverting input ends of the 15 dynamic comparators are connected with each other and used as the input end of a sampling voltage signal Vs of a fully parallel 4-bit analog-to-digital conversion module U4; the clock signal CLK input ends of the 15 dynamic comparators are connected with each other and are used as the clock signal CLK input end of a full-parallel 4-bit analog-to-digital conversion module U4; the output ends of the 15 dynamic comparators are respectively and sequentially connected with the 15-bit signal input end of the thermometer code decoder U116 in a one-to-one correspondence manner;

the thermometer code decoder U116 is an SMIC130nm technical CMOS combinational logic application specific integrated circuit ASIC, and is used for converting 15-bit signals of thermometer code-like patterns output by combining 15 dynamic comparators arranged in a stepped manner into 4-bit binary digital signals, wherein for the 15-bit signals, if there are several high-level signals, the decimal numbers corresponding to the 4-bit binary digital signals are several; the four output ends of the thermometer code decoder U116 are sequentially used as a third BIT signal BIT3 output end, a second BIT signal BIT2 output end, a first BIT signal BIT1 output end and a zero BIT signal BIT0 output end of the fully parallel 4-BIT analog-to-digital conversion module U4.

5. The self-calibrating composite-structured ADC of claim 3, wherein each of the dynamic comparators U2 and 15 dynamic comparators has the same structure, and comprises: a clock signal inverting circuit, a dynamic amplifier and a latch;

the clock signal CLK input end of the clock signal inverting circuit is connected with the clock signal CLK input end of the dynamic amplifier and is used as the clock signal CLK input ends of the dynamic comparators U2 and the 15 dynamic comparators; the clock signal CLKN output end of the clock signal inverting circuit is connected with the clock signal CLKN input end of the latch; the input end V-of the dynamic amplifier is used as the inverting input ends of the dynamic comparators U2 and the 15 dynamic comparators, and the input end V + of the dynamic amplifier is used as the non-inverting input ends of the dynamic comparators U2 and the 15 dynamic comparators; the output end Vx of the dynamic amplifier is connected with the input end Vx of the latch, and the output end Vy of the dynamic amplifier is connected with the input end Vy of the latch; the power supply end VDD of the clock signal inverting circuit is respectively connected with the power supply end VDD of the dynamic amplifier and the power supply end VDD of the latch and is used as the power supply ends VDD of the dynamic comparators U2 and the 15 dynamic comparators; the common end GND of the clock signal inverting circuit is respectively connected with the common end GND of the dynamic amplifier and the common end GND of the latch and is used as the common end GND of the dynamic comparators U2 and 15 dynamic comparators; the output terminal Vout of the latch is used as the output terminals of the dynamic comparator U2 and 15 dynamic comparisons;

the clock signal inverting circuit includes: a PMOS transistor M201 and an NMOS transistor M202;

the source electrode of the PMOS tube M201 is used as a power supply end VDD of the clock signal inverter circuit, and the grid electrode of the PMOS tube M201 is connected with the grid electrode of the NMOS tube M202 and is used as a clock signal CLK input end of the clock signal inverter circuit; the drain electrode of the PMOS tube M201 is connected with the drain electrode of the NMOS tube M202 and is used as a clock signal CLKN output end of the clock signal inverter circuit; the source electrode of the NMOS tube M202 is used as a common end GND of the clock signal inverting circuit;

the dynamic amplifier includes: a PMOS tube M203, a PMOS tube M204, a PMOS tube M205, an NMOS tube M206 and an NMOS tube M207;

the source of the PMOS transistor M203 is used as a power supply terminal VDD of the dynamic amplifier, the gate thereof is used as a clock signal CLK input terminal of the dynamic amplifier, and the drain thereof is connected with the source of the PMOS transistor M204 and the source of the PMOS transistor M205 respectively; the grid electrode of the PMOS tube M204 is used as the input end V-of the dynamic amplifier, and the drain electrode of the PMOS tube M204 is respectively connected with the drain electrode of the NMOS tube M206 and the grid electrode of the NMOS tube M206 and is used as the output end Vy of the dynamic amplifier; the grid electrode of the PMOS tube M205 is used as the input end V + of the dynamic amplifier, and the drain electrode of the PMOS tube M205 is respectively connected with the drain electrode of the NMOS tube M207 and the grid electrode of the NMOS tube M207 and is used as the output end Vx of the dynamic amplifier; the source electrode of the NMOS tube M206 is connected with the source electrode of the NMOS tube M207 and is used as a common end GND of the dynamic amplifier;

the latch includes: a PMOS tube M208, a PMOS tube M209, a PMOS tube M210, a PMOS tube M211, a PMOS tube M212, an NMOS tube M213, an NMOS tube M214, an NMOS tube M215, a PMOS tube M216, a PMOS tube M217, an NMOS tube M218, a PMOS tube M219, an NMOS tube M220 and an NMOS tube M221;

the grid electrode of the PMOS tube M208 is respectively connected with the source electrode of the PMOS tube M208 and the source electrode of the PMOS tube M216 and serves as the power supply end VDD of the latch, and the drain electrode of the PMOS tube M208 is respectively connected with the source electrode of the PMOS tube M209, the source electrode of the PMOS tube M210, the source electrode of the PMOS tube M211 and the source electrode of the PMOS tube M212; the grid electrode of the PMOS tube M209 is respectively connected with the drain electrode of the PMOS tube M209, the drain electrode of the PMOS tube M210, the drain electrode of the NMOS tube M214, the drain electrode of the NMOS tube M213, the grid electrode of the PMOS tube M211, the grid electrode of the PMOS tube M219 and the grid electrode of the NMOS tube M220; the drain electrode of the PMOS tube M211 is respectively connected with the drain electrode of the PMOS tube M212, the grid electrode of the PMOS tube M210, the source electrode of the NMOS tube M213, the drain electrode of the NMOS tube M215, the grid electrode of the PMOS tube M217 and the grid electrode of the NMOS tube M218; the grid electrode of the NMOS tube M215 is used as an input end Vx of the latch; the grid electrode of the NMOS tube M214 is used as an input end Vy of the latch; the grid of the NMOS tube M213 is used as the clock signal CLKN input end of the latch; the grid electrode of the PMOS tube M216 is respectively connected with the grid electrode of the NMOS tube M221, the drain electrode of the PMOS tube M217 and the drain electrode of the NMOS tube M218, and the drain electrode of the PMOS tube M216 is respectively connected with the source electrode of the PMOS tube M217 and the source electrode of the PMOS tube M219; the drain electrode of the PMOS tube M219 is connected with the drain electrode of the NMOS tube M220 and is used as the output end Vout of the latch; the source electrode of the NMOS tube M220 is respectively connected with the source electrode of the NMOS tube M218 and the drain electrode of the NMOS tube M221; the source of the NMOS transistor M214 is connected to the source of the NMOS transistor M215 and the source of the NMOS transistor M221, respectively, and serves as the common terminal GND of the latch.

6. The self-calibrating composite-structure ADC according to claim 1, wherein said D flip-flops U5-U8 are identical in structure and comprise: a PMOS tube M301, an NMOS tube M302, an NMOS tube M303, a PMOS tube M304, a PMOS tube M305, an NMOS tube M306, an NMOS tube M307, a PMOS tube M308, a PMOS tube M309 and an NMOS tube M310;

the source electrode of the PMOS tube M301 is respectively connected with the source electrode of the PMOS tube M305 and the source electrode of the PMOS tube M309 and serves as a power supply end VDD of the D flip-flop U5-U8, the grid electrodes of the PMOS tube M301 and the NMOS tube M307 are respectively connected with the grid electrode of the NMOS tube M302 and the grid electrode of the NMOS tube M304 and the grid electrode of the D flip-flop U5-U8, and the drain electrodes of the PMOS tube M301 and the NMOS tube M302 and the NMOS tube M303 and the PMOS tube M308 are respectively connected with the drain electrode of the NMOS tube M302 and the grid electrode of the NMOS tube M308; the source electrode of the NMOS tube M302 is respectively connected with the source electrode of the NMOS tube M306 and the source electrode of the NMOS tube M310 and is used as the common end GND of the D flip-flop U5-U8; the source electrode of the NMOS tube M303 is connected with the drain electrode of the PMOS tube M304 and serves as an input end D of a D trigger U5-U8, and the drain electrodes of the NMOS tube M303 and the PMOS tube M are respectively connected with the source electrode of the PMOS tube M304, the grid electrode of the PMOS tube M305 and the grid electrode of the NMOS tube M306; the drain electrode of the NMOS tube M306 is respectively connected with the drain electrode of the PMOS tube M305, the source electrode of the NMOS tube M307 and the drain electrode of the PMOS tube M308; the drain electrode of the NMOS tube M307 is respectively connected with the source electrode of the PMOS tube M308, the grid electrode of the PMOS tube M309 and the grid electrode of the NMOS tube M310; the drain electrode of the NMOS tube M310 is connected with the drain electrode of the PMOS tube M309 and serves as an output end Q of the D flip-flop U5-U8.

7. The self-calibrating, composite-structure ADC of claim 2, wherein said and gates are identical in structure to each of U10-U13, and each comprise: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, a PMOS tube M405 and an NMOS tube M406;

the grid electrode of the PMOS tube M401 is connected with the grid electrode of the NMOS tube M403 and serves as an input end Vin1 of an AND gate U10-U13, the source electrode of the PMOS tube M401 is respectively connected with the source electrode of the PMOS tube M402 and the source electrode of the PMOS tube M405 and serves as a power supply end VDD of the AND gate U10-U13, and the drain electrode of the PMOS tube M35is respectively connected with the drain electrode of the PMOS tube M402, the drain electrode of the NMOS tube M403, the grid electrode of the PMOS tube M405 and the grid electrode of the NMOS tube M406; the drain electrode of the PMOS tube M405 is connected with the drain electrode of the NMOS tube M406 and is used as the output end Vout of the AND gate U10-U13; the source electrode of the NMOS tube M406 is connected with the source electrode of the NMOS tube M404 and is used as a common end GND of the AND gate U10-U13; the gate of the NMOS transistor M404 is connected to the gate of the PMOS transistor M402 and serves as the input terminal Vin2 of the AND gate U10-U13, and the drain thereof is connected to the source of the NMOS transistor M403.

8. The self-calibrating composite-structured ADC of claim 1, wherein said gate voltage bootstrapped switch SW3 comprises: a PMOS tube M501, an NMOS tube M502, a PMOS tube M503, a capacitor C501, a PMOS tube M504, an NMOS tube M505, an NMOS tube M506, a capacitor C502, a PMOS tube M507, a PMOS tube M508, an NMOS tube M509, a capacitor C503, a PMOS tube M510, a PMOS tube M511, an NMOS tube M512, an NMOS tube M513, a PMOS tube M514, an NMOS tube M515, an NMOS tube M516, an NMOS tube M517, an NMOS tube M518, a PMOS tube M519, a PMOS tube M520, an NMOS tube M521, a PMOS tube M522 and a PMOS tube M523;

the grid of the PMOS transistor M501 is connected to the grid of the NMOS transistor M502, the grid of the PMOS transistor M511, the grid of the NMOS transistor M512, the grid of the PMOS transistor M522, the grid of the PMOS transistor M523, and the grid of the NMOS transistor M521, respectively, and serves as a control end ctl of the gate voltage bootstrap switch SW3, the drain of which is connected to the drain of the NMOS transistor M502, one end of the capacitor C501, the source of the NMOS transistor M505, the grid of the NMOS transistor M506, the grid of the PMOS transistor M514, and the grid of the NMOS transistor M515, the source of which is connected to the drain of the PMOS transistor M503, the drain of the PMOS transistor M508, the source of the PMOS transistor M511, the grid of the NMOS transistor M513, the source of the PMOS transistor M514, the drain of the PMOS transistor M522, the source of the PMOS transistor M523, and the grid of the PMOS transistor M507, respectively, and serves as a power supply end VDD of the gate; the source electrode of the NMOS transistor M502 is connected to the source electrode of the NMOS transistor M506, the source electrode of the NMOS transistor M515, the gate electrode of the PMOS transistor M520, and the source electrode of the NMOS transistor M521, respectively, and serves as the common end GND of the gate voltage bootstrap switch SW 3; the source electrode of the PMOS tube M503 is respectively connected with the other end of the capacitor C501, the source electrode of the PMOS tube M507 and the drain electrode of the PMOS tube M504, and the grid electrode of the PMOS tube M503 is respectively connected with the source electrode of the PMOS tube M504 and the drain electrode of the NMOS tube M505; the grid electrode of the PMOS tube M504 is connected with the grid electrode of the NMOS tube M505; the drain of the NMOS tube M506 is respectively connected with one end of the capacitor C502, the source of the NMOS tube M512 and the source of the NMOS tube M516; the source electrode of the PMOS tube M508 is respectively connected with the other end of the capacitor C502, the grid electrode of the NMOS tube M509 and the source electrode of the PMOS tube M510, and the grid electrode of the PMOS tube M508 is respectively connected with the drain electrode of the PMOS tube M510, the source electrode of the NMOS tube M513, the grid electrode of the NMOS tube M516, the grid electrode of the NMOS tube M517 and the grid electrode of the NMOS tube M518; the drain electrode of the PMOS tube M511 is respectively connected with the drain electrode of the NMOS tube M512 and the gate electrode of the PMOS tube M510; the drain electrode of the NMOS tube M513 is respectively connected with the drain electrode of the PMOS tube M514 and the drain electrode of the NMOS tube M515; the source electrode of the NMOS tube M509 is respectively connected with the drain electrode of the PMOS tube M507 and one end of the capacitor C503, and the drain electrode of the NMOS tube M509 is respectively connected with the source electrode of the NMOS tube M518 and the source electrode of the PMOS tube M522; the drain electrode of the NMOS tube M518 is respectively connected with the source electrode of the PMOS tube M519, the drain electrode of the NMOS tube M516 and the source electrode of the NMOS tube M517 and serves as an input end a of a grid voltage bootstrap switch SW 3; the drain electrode of the PMOS tube M520 is respectively connected with the other end of the capacitor C503 and the grid electrode of the PMOS tube M519, and the source electrode of the PMOS tube M520 is respectively connected with the drain electrode of the NMOS tube M521 and the drain electrode of the PMOS tube M523; the drain of the PMOS transistor M519 is connected to the drain of the NMOS transistor M517, and serves as the output terminal b of the gate voltage bootstrapped switch SW 3.

9. The self-calibrating composite-structured ADC of claim 3, wherein said CMOS complementary switch SW1, CMOS complementary switch SW2, CMOS complementary switch SW114 and CMOS complementary switch SW115 are identical in structure, and comprise: PMOS transistor M601, NMOS transistor M602, NMOS transistor M603 and PMOS transistor M604;

the source electrode of the PMOS tube M601 is a power supply end VDD of a CMOS complementary switch SW1, a CMOS complementary switch SW2, a CMOS complementary switch SW114 and a CMOS complementary switch SW115, the grid electrodes of the PMOS tube M601 are respectively connected with the grid electrode of the NMOS tube M602 and the grid electrode of the NMOS tube M603, the PMOS tube M is used as a control end ctl of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW115, and the drain electrodes of the PMOS tube M602 and the PMOS tube M604 are respectively connected with the drain electrode of the NMOS tube M602; the source electrode of the NMOS tube M602 is used as a common end GND of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW 115; the source of the NMOS transistor M603 is connected with the drain of the PMOS transistor M604 and serves as a communication end a of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW115, and the drain of the NMOS transistor M603 is connected with the source of the PMOS transistor M604 and serves as a communication end b of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW 115;

the structures of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW206 are the same, and the method comprises the following steps: a PMOS tube M701, an NMOS tube M702, an NMOS tube M703, a PMOS tube M704, an NMOS tube M705 and a PMOS tube M706;

the grid electrode of the PMOS tube M701 is respectively connected with the grid electrode of the NMOS tube M702, the grid electrode of the NMOS tube M703 and the grid electrode of the PMOS tube M706, and is used as the control end ctl of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW206, and the drain electrode of the PMOS tube M701 is respectively connected with the drain electrode of the NMOS tube M702, the grid electrode of the PMOS tube M704 and the grid electrode of the NMOS tube M705; the source electrode of the PMOS tube M701 is used as a power supply end VDD of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW 206; the source electrode of the NMOS tube M702 is used as a common end GND of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW 206; the drain electrode of the NMOS tube M703 is respectively connected with the source electrode of the PMOS tube M704, the drain electrode of the NMOS tube M705 and the source electrode of the PMOS tube M706, and is used as the fixed end c of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW 206; the source electrode of the NMOS transistor M703 is connected with the drain electrode of the PMOS transistor M704 and is used as an optional end a of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW 206; the source of the NMOS transistor M705 is connected with the drain of the PMOS transistor M706 and serves as an optional end b of the single-pole double-throw switch SW4, the single-pole double-throw switches SW100-SW113, the single-pole double-throw switches SW120-SW123 and the single-pole double-throw switches SW200-SW 206.

Technical Field

The invention relates to the field of digital-analog hybrid integrated circuits, in particular to a self-calibration composite structure ADC.

Background

Analog-to-digital converters (ADCs), which are a type of digital-to-analog hybrid integrated circuits that convert analog signals into digital signals, are widely used in various fields such as voice, image, and communication, and their performance directly affects the performance of the entire circuit system.

The resistor, the comparator and the switch capacitor which are connected in series are key circuits of the ADC, and due to the process limitation, the real capacitance value is difficult to be equal to the capacitance value designed on a drawing, so that a capacitance mismatch error is generated, and the precision of the ADC is influenced; how to ensure the performance of the comparator and reduce the power consumption of the comparator; how to realize the on-chip integration of the large-resistance resistor directly influences the performance of the ADC.

The existing research on ADCs is many, but as the application scene becomes more and more severe, there is a need in the market for a high-speed, high-precision and low-power ADC. However, in the conventional technology, for example, an ADC having a fully parallel structure, high speed and high precision are two factors that are restricted from each other and cannot be compatible with each other, and power consumption is increased in order to improve precision and speed, so that the conventional technology needs to be innovative in order to achieve the indexes of high speed, high precision, and low power consumption.

Disclosure of Invention

Aiming at the defects in the prior art, the self-calibration composite structure ADC provided by the invention solves the problem that the traditional technology cannot give consideration to high speed, high precision and low power consumption, and realizes the analog-digital conversion process with high resolution, high sampling rate and low power consumption.

In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a self-calibrating composite structure ADC comprising: the circuit comprises a capacitor self-calibration module U1, a dynamic comparator U2, a capacitive digital-to-analog conversion module U3, a full-parallel 4-bit analog-to-digital conversion module U4, a D trigger U5, a D trigger U6, a D trigger U7, a D trigger U8, a main control module U9, a CMOS complementary switch SW1, a CMOS complementary switch SW2, a gate voltage bootstrap switch SW3, a single-pole double-throw switch SW4 and a sampling capacitor Cs;

The invention has the beneficial effects that: the dynamic comparator is adopted to replace the traditional common comparator, so that the static direct-current power consumption is avoided, and the overall power consumption of the ADC is greatly reduced; considering that ADC measurement errors mainly come from errors between capacitance values of capacitors produced by a specific process and designed capacitance values, a capacitor self-calibration module is additionally arranged, and internal capacitors of the capacitive digital-to-analog conversion module are calibrated through the capacitor self-calibration module; the full-parallel 4-bit analog-to-digital conversion module is adopted to directly carry out coarse quantization on the analog signal to obtain a high-bit digital signal, and the successive comparison link of the capacitive digital-to-analog conversion module and the dynamic comparator is cooperated, so that the successive comparison time is greatly saved, the ADC quantization coding speed is improved, and the performances of high speed, high precision and low power consumption can be realized.

Further, the capacitive digital-to-analog conversion module U3 includes: capacitors C0-C14, a bridge capacitor Cp, single-pole double-throw switches SW100-SW113, single-pole double-throw switches SW120-SW123, a CMOS complementary switch SW114, a CMOS complementary switch SW115 and AND gates U10-U13;

The beneficial effects of the above further scheme are: a 14-bit capacitive digital-to-analog conversion module based on 14 switch capacitors and 1 grounding capacitor is designed and used for carrying out successive approximation quantization coding on a sampling voltage signal in cooperation with a dynamic comparator under the control of a main control module; since, in general, for a switched capacitor, the capacitance value of each higher bit must be increased by 2 times that of the adjacent lower bit capacitor, that is, the capacitance value of the capacitor C13 should be 8192 times that of the capacitor C0 under the conventional technology, which is far beyond the limit of the conventional integrated circuit process, the bridging capacitor Cp is designed to couple the higher 7-bit switched capacitor and the lower 7-bit switched capacitor, only the capacitance value of the bridging capacitor needs to be set to 1.015873 times that of the capacitor C0, and the potential formed by charging and discharging of the lower 7-bit switched capacitor can be coupled to the analog signal Vas end in the 1/64 state, in this case, the capacitance value of each of the lower 7-bit switched capacitor needs to be 64 times that of the capacitor C0 at most, the capacitance value of each of the higher 7-bit switched capacitor only needs to be set in one-to-one correspondence with the lower 7 bits, and the design makes the two capacitors with the largest capacitance values, that is, namely, the capacitor C, the method is easy to realize, and effectively saves the integrated circuit layout; in order to enable the effective resetting of the switched capacitor, CMOS complementary switches SW114 and SW115 are used to form a controlled discharge path to ground; and 4 AND gates are used for realizing that the high-4-bit approximation is completed once in a single clock period under the drive of a high-4-bit enable control signal SB of the main control module and the assistance of 4-bit data output by the fully parallel 4-bit analog-to-digital conversion module, so that the time of successive approximation quantization coding is greatly shortened, and the rate is effectively improved.

Further, the capacitance self-calibration module U1 includes: capacitors C100-C107 and single-pole double-throw switches SW200-SW 206;

The beneficial effects of the above further scheme are: due to the limitation of an integrated circuit process, the real capacitance values of all capacitors are difficult to be equal to the capacitance values designed on a drawing, if the capacitance of a capacitive digital-to-analog conversion module also generates deviation, the overall precision of an ADC is influenced, in order to effectively improve the precision, a capacitor self-calibration module is designed at the other end, connected with the capacitive digital-to-analog conversion module, of a dynamic comparator, a 7-bit switched capacitor array is formed by 7 switched capacitors, 7-bit resolution can be achieved by adopting a successive approximation quantization coding mode under the control of a main control module, the mismatch voltage of each bit of switched capacitor of the capacitive digital-to-analog conversion module is measured, and the ADC quantization coding error caused by the capacitance mismatch error is corrected.

Further, the fully parallel 4-bit analog-to-digital conversion module U4 includes: 16 PMOS tubes, 15 dynamic comparators and thermometer code decoder U116;

The beneficial effects of the above further scheme are: the ADC with the fully parallel structure is the most common ADC with the common structure, has the advantages of extremely high speed and extremely high resource requirement, and has the defects that because the comparators with the number which is one less than the corresponding power of 2 are needed for realizing the resolution of several bits, and the resistor ladder which is formed by connecting resistors with corresponding magnitude in series is needed, the high resolution cannot be realized under the conditions of low power consumption and small size, the fully parallel ADC with the resolution of 4 bits is designed to assist a capacitive digital-to-analog conversion module to complete the approximation of 4 bits at one time by utilizing the characteristic of high speed of the fully parallel structure ADC, and only 16 equivalent resistors and 15 comparators are needed under the condition, so that the layout size of an integrated circuit cannot be greatly influenced; meanwhile, in order to effectively reduce power consumption, a dynamic comparator without static power consumption is adopted, and a resistor with a large resistance value is adopted to form a resistor ladder, so that current is reduced, and the effect of low power consumption is achieved; because the on-chip resistor in the integrated circuit process is difficult to realize large resistance, the grid source electrode of the PMOS is connected, and the source electrode and the drain electrode of the PMOS are equivalent to a large-resistance resistor in the real process to form a pseudo resistor ladder to replace the conventional resistor.

Further, the dynamic comparators U2 and 15 dynamic comparators have the same structure, including: a clock signal inverting circuit, a dynamic amplifier and a latch;

the clock signal inverting circuit includes: a PMOS transistor M201 and an NMOS transistor M202;

the dynamic amplifier includes: a PMOS tube M203, a PMOS tube M204, a PMOS tube M205, an NMOS tube M206 and an NMOS tube M207;

The beneficial effects of the above further scheme are: the PMOS tube which adopts a common source configuration forms an amplifying circuit, the NMOS tube which is connected with a grid drain and locked in a saturation region working state is used as a load of the amplifying circuit, the two circuits form a symmetrical differential amplifying circuit, and in order to enable the static power consumption of the amplifying circuit to be 0, the PMOS tube which is controlled by a clock signal in a switching pulse mode is used for providing tail current of the amplifying circuit, so that a dynamic amplifier is formed; however, the dynamic amplifier is always in a state of on-off cycle reciprocation, and the output of the dynamic amplifier needs to be latched to form final stable output, so that a latch controlled by an inverted clock relative to the dynamic amplifier is designed, on one hand, voltage state latching is performed, on the other hand, a double-end signal output by the dynamic amplifier is further amplified and converted through a specific MOS tube combination, a complementary CMOS pair for controlling a push-pull structure, namely gate voltages of on and off of a PMOS tube M217 and an NMOS tube M218 in the design, a single-end high-low level digital signal is obtained and used as final output, and compared with a traditional comparator, the dynamic amplifier is high in comparison precision, small in offset error and low in power consumption.

Further, the D flip-flops U5-U8 are all identical in structure and comprise: a PMOS tube M301, an NMOS tube M302, an NMOS tube M303, a PMOS tube M304, a PMOS tube M305, an NMOS tube M306, an NMOS tube M307, a PMOS tube M308, a PMOS tube M309 and an NMOS tube M310;

Further, the and gates U10-U13 are all the same in structure and include: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, a PMOS tube M405 and an NMOS tube M406;

Further, the gate voltage bootstrap switch SW3 includes: a PMOS tube M501, an NMOS tube M502, a PMOS tube M503, a capacitor C501, a PMOS tube M504, an NMOS tube M505, an NMOS tube M506, a capacitor C502, a PMOS tube M507, a PMOS tube M508, an NMOS tube M509, a capacitor C503, a PMOS tube M510, a PMOS tube M511, an NMOS tube M512, an NMOS tube M513, a PMOS tube M514, an NMOS tube M515, an NMOS tube M516, an NMOS tube M517, an NMOS tube M518, a PMOS tube M519, a PMOS tube M520, an NMOS tube M521, a PMOS tube M522 and a PMOS tube M523;

The beneficial effects of the above further scheme are: the NMOS tube M517 and the PMOS tube M519 form a CMOS complementary switch, although the on-off capacity of the CMOS complementary switch is strong enough compared with that of a single MOS tube, in order to ensure the controllability of the ADC sampling capacity, the equivalent resistance of the switch connected with the sampling capacitor under any signal amplitude needs not to be changed, which is the point that the CMOS complementary switch does not have, and therefore the grid voltage of the CMOS complementary switch needs to be stabilized; on the basis of a complementary CMOS switch, the design utilizes the principle that charges stored in capacitors can not change suddenly through a specific MOS tube circuit to switch the connection state of two electrode plates of the three capacitors so as to form boost voltage, and differential pressure which does not change along with input voltage is obtained between two electrodes of grid elements of an NMOS tube M517 and a PMOS tube M519, so that the complementary CMOS switch is opened under fixed voltage, and equivalent resistance under the integral conduction state is not changed.

Further, the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW115 are all the same in structure, and include: PMOS transistor M601, NMOS transistor M602, NMOS transistor M603 and PMOS transistor M604;

Drawings

FIG. 1 is a circuit diagram of a self-calibrating composite ADC;

FIG. 2 is a circuit diagram of a capacitive digital-to-analog conversion module;

FIG. 3 is a circuit diagram of a capacitance self-calibration module;

FIG. 4 is a circuit diagram of a fully parallel 4-bit analog-to-digital conversion module;

FIG. 5 is a circuit diagram of a dynamic comparator;

FIG. 6 is a circuit diagram of a D flip-flop;

FIG. 7 is a diagram of an AND gate circuit;

FIG. 8 is a circuit diagram of a gate voltage bootstrapped switch;

FIG. 9 is a CMOS complementary switch circuit diagram;

FIG. 10 is a circuit diagram of a single pole double throw switch;

FIG. 11 is a timing diagram of the operation of the self-calibrating composite ADC quantization encoding;

FIG. 12 is a graph of the results of an experiment on the dynamic performance of a self-calibrating composite ADC.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.

In an embodiment of the present invention, a self-calibrating composite ADC is designed based on the SMIC130nm library by using a CMOS scheme and processed by the SMIC130nm process at 130nm, as shown in fig. 1, and has a structure including: the circuit comprises a capacitor self-calibration module U1, a dynamic comparator U2, a capacitive digital-to-analog conversion module U3, a full-parallel 4-bit analog-to-digital conversion module U4, a D trigger U5, a D trigger U6, a D trigger U7, a D trigger U8, a main control module U9, a CMOS complementary switch SW1, a CMOS complementary switch SW2, a gate voltage bootstrap switch SW3, a single-pole double-throw switch SW4 and a sampling capacitor Cs;

As shown in fig. 2, the capacitive digital-to-analog conversion module U3 includes: capacitors C0-C14, a bridge capacitor Cp, single-pole double-throw switches SW100-SW113, single-pole double-throw switches SW120-SW123, a CMOS complementary switch SW114, a CMOS complementary switch SW115 and AND gates U10-U13;

In the scheme, a 14-bit capacitive digital-to-analog conversion module based on 14 switch capacitors and 1 grounding capacitor is used for performing successive approximation quantization coding on a sampling voltage signal in cooperation with a dynamic comparator under the control of a main control module; since, in general, for a switched capacitor, the capacitance value of each higher bit must be increased by 2 times that of the adjacent lower bit capacitor, that is, the capacitance value of the capacitor C13 should be 8192 times that of the capacitor C0 under the conventional technology, which is far beyond the limit of the conventional integrated circuit process, the bridging capacitor Cp is designed to couple the higher 7-bit switched capacitor and the lower 7-bit switched capacitor, only the capacitance value of the bridging capacitor needs to be set to 1.015873 times that of the capacitor C0, and the potential formed by charging and discharging of the lower 7-bit switched capacitor can be coupled to the analog signal Vas end in the 1/64 state, in this case, the capacitance value of each of the lower 7-bit switched capacitor needs to be 64 times that of the capacitor C0 at most, the capacitance value of each of the higher 7-bit switched capacitor only needs to be set in one-to-one correspondence with the lower 7 bits, and the design makes the two capacitors with the largest capacitance values, that is, namely, the capacitor C, the method is easy to realize, and effectively saves the integrated circuit layout; in order to enable the effective resetting of the switched capacitor, CMOS complementary switches SW114 and SW115 are used to form a controlled discharge path to ground; and 4 AND gates are used for realizing that the high-4-bit approximation is completed once in a single clock period under the drive of a high-4-bit enable control signal SB of the main control module and the assistance of 4-bit data output by the fully parallel 4-bit analog-to-digital conversion module, so that the time of successive approximation quantization coding is greatly shortened, and the rate is effectively improved.

Because of the SMIC130nm process library adopted by the design, the MIM.1 type capacitor in the process library is the capacitor with the minimum unit capacitance value, and the minimum area of the capacitor is 9 mu m²The capacitance per unit area is 1 fF/mum²In order to save the layout area and reduce the power consumption, the capacitance value of the capacitor C0 is set to be 9fF, and in such cases, the maximum capacitor C13 and the maximum capacitor C6 are 576fF, and the sampling capacitor Cs is also 576 fF.

As shown in fig. 3, the capacitance self-calibration module U1 includes: capacitors C100-C107 and single-pole double-throw switches SW200-SW 206;

Due to the limitation of the integrated circuit process, the true capacitance values of all capacitors are difficult to be equal to the capacitance values designed on the drawing, and if the capacitance of the capacitive digital-to-analog conversion module also generates deviation, the overall accuracy of the ADC is influenced, which is also the reason for designing a capacitance self-calibration module. In order to effectively improve the precision, a capacitor self-calibration module is designed at the other end of the dynamic comparator connected with the capacitive digital-to-analog conversion module, a 7-bit switched capacitor array is formed by 7 switched capacitors, 7-bit resolution can be realized by adopting a successive approximation quantization coding mode under the control of a main control module, and mismatch voltage of each switched capacitor of the capacitive digital-to-analog conversion module is measured so as to correct ADC quantization coding errors caused by the capacitor mismatch errors.

As shown in fig. 4, the fully parallel 4-bit analog-to-digital conversion module U4 includes: 16 PMOS tubes, 15 dynamic comparators and thermometer code decoder U116;

The ADC with the fully parallel structure is the most common ADC with the common structure, has the advantages of extremely high speed and extremely high resource requirement, and has the defects that because the comparators with the number which is one less than the corresponding power of 2 are needed for realizing the resolution of several bits, and the resistor ladder which is formed by connecting resistors with corresponding magnitude in series is needed, the high resolution cannot be realized under the conditions of low power consumption and small size, the fully parallel ADC with the resolution of 4 bits is designed to assist a capacitive digital-to-analog conversion module to complete the approximation of 4 bits at one time by utilizing the characteristic of high speed of the fully parallel structure ADC, and only 16 equivalent resistors and 15 comparators are needed under the condition, so that the layout size of an integrated circuit cannot be greatly influenced; meanwhile, in order to effectively reduce power consumption, a dynamic comparator without static power consumption is adopted, and a resistor with a large resistance value is adopted to form a resistor ladder, so that current is reduced, and the effect of low power consumption is achieved; because the on-chip resistor in the integrated circuit process is difficult to realize large resistance, the grid source electrode of the PMOS is connected, and the source electrode and the drain electrode of the PMOS are equivalent to a large-resistance resistor in the real process to form a pseudo resistor ladder to replace the conventional resistor.

As shown in fig. 5, the dynamic comparators U2 and 15 dynamic comparators have the same structure, including: a clock signal inverting circuit, a dynamic amplifier and a latch;

the clock signal inverting circuit includes: a PMOS transistor M201 and an NMOS transistor M202;

the dynamic amplifier includes: a PMOS tube M203, a PMOS tube M204, a PMOS tube M205, an NMOS tube M206 and an NMOS tube M207;

The PMOS tube which adopts a common source configuration forms an amplifying circuit, the NMOS tube which is connected with a grid drain and locked in a saturation region working state is used as a load of the amplifying circuit, the two circuits form a symmetrical differential amplifying circuit, and in order to enable the static power consumption of the amplifying circuit to be 0, the PMOS tube which is controlled by a clock signal in a switching pulse mode is used for providing tail current of the amplifying circuit, so that a dynamic amplifier is formed; however, the dynamic amplifier is always in a state of on-off cycle reciprocation, and the output of the dynamic amplifier needs to be latched to form final stable output, so that a latch controlled by an inverted clock relative to the dynamic amplifier is designed, on one hand, voltage state latching is performed, on the other hand, a double-end signal output by the dynamic amplifier is further amplified and converted through a specific MOS tube combination, a complementary CMOS pair for controlling a push-pull structure, namely gate voltages of on and off of a PMOS tube M217 and an NMOS tube M218 in the design, a single-end high-low level digital signal is obtained and used as final output, and compared with a traditional comparator, the dynamic amplifier is high in comparison precision, small in offset error and low in power consumption.

As shown in FIG. 6, the D flip-flops U5-U8 are all identical in structure and comprise: a PMOS tube M301, an NMOS tube M302, an NMOS tube M303, a PMOS tube M304, a PMOS tube M305, an NMOS tube M306, an NMOS tube M307, a PMOS tube M308, a PMOS tube M309 and an NMOS tube M310;

As shown in fig. 7, the and gates U10-U13 have the same structure, and each include: a PMOS tube M401, a PMOS tube M402, an NMOS tube M403, an NMOS tube M404, a PMOS tube M405 and an NMOS tube M406;

As shown in fig. 8, the gate voltage bootstrap switch SW3 includes: a PMOS tube M501, an NMOS tube M502, a PMOS tube M503, a capacitor C501, a PMOS tube M504, an NMOS tube M505, an NMOS tube M506, a capacitor C502, a PMOS tube M507, a PMOS tube M508, an NMOS tube M509, a capacitor C503, a PMOS tube M510, a PMOS tube M511, an NMOS tube M512, an NMOS tube M513, a PMOS tube M514, an NMOS tube M515, an NMOS tube M516, an NMOS tube M517, an NMOS tube M518, a PMOS tube M519, a PMOS tube M520, an NMOS tube M521, a PMOS tube M522 and a PMOS tube M523;

The NMOS tube M517 and the PMOS tube M519 form a CMOS complementary switch, although the on-off capacity of the CMOS complementary switch is strong enough compared with that of a single MOS tube, in order to ensure the controllability of the ADC sampling capacity, the equivalent resistance of the switch connected with the sampling capacitor under any signal amplitude needs not to be changed, which is the point that the CMOS complementary switch does not have, and therefore the grid voltage of the CMOS complementary switch needs to be stabilized; on the basis of a complementary CMOS switch, the design utilizes the principle that charges stored in capacitors can not change suddenly through a specific MOS tube circuit to switch the connection state of two electrode plates of the three capacitors so as to form boost voltage, and differential pressure which does not change along with input voltage is obtained between two electrodes of grid elements of an NMOS tube M517 and a PMOS tube M519, so that the complementary CMOS switch is opened under fixed voltage, and equivalent resistance under the integral conduction state is not changed.

As shown in fig. 9, the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW115 are identical in structure, and include: PMOS transistor M601, NMOS transistor M602, NMOS transistor M603 and PMOS transistor M604;

the source electrode of the PMOS tube M601 is a power supply end VDD of a CMOS complementary switch SW1, a CMOS complementary switch SW2, a CMOS complementary switch SW114 and a CMOS complementary switch SW115, the grid electrodes of the PMOS tube M601 are respectively connected with the grid electrode of the NMOS tube M602 and the grid electrode of the NMOS tube M603, the PMOS tube M is used as a control end ctl of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW115, and the drain electrodes of the PMOS tube M602 and the PMOS tube M604 are respectively connected with the drain electrode of the NMOS tube M602; the source electrode of the NMOS tube M602 is used as a common end GND of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114 and the CMOS complementary switch SW 115; the source of the NMOS transistor M603 is connected to the drain of the PMOS transistor M604, and serves as a connection terminal a of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114, and the CMOS complementary switch SW115, and the drain thereof is connected to the source of the PMOS transistor M604 and serves as a connection terminal b of the CMOS complementary switch SW1, the CMOS complementary switch SW2, the CMOS complementary switch SW114, and the CMOS complementary switch SW 115.

As shown in fig. 10, the single-pole double-throw switch SW4, the single-pole double-throw switches SW100 to SW113, the single-pole double-throw switches SW120 to SW123, and the single-pole double-throw switches SW200 to SW206 have the same structure, including: a PMOS tube M701, an NMOS tube M702, an NMOS tube M703, a PMOS tube M704, an NMOS tube M705 and a PMOS tube M706;

As shown in fig. 11, the main control module U9 controls the respective sections to perform quantization coding at the timing: in the first three clock cycles, the sampling control signal SP is set to a high level, the analog voltage Vin charges the sampling capacitor Cs, the reset signal RST is also set to a high level, and the switched capacitor array of the capacitive d/a conversion module U3 is in a reset state with both ends grounded. It should be noted that, since the high four-bit capacitor switch of the capacitive digital-to-analog conversion module U3 is directly controlled by the level of the fully parallel 4-bit analog-to-digital conversion module U4 after being buffered by 4 flip-flops, in order to enable the four capacitors to be in the reset state with both ends grounded, four and gates are designed, and between the three clock cycles, the high 4-bit enable control signal SB is in the low level state, and both ends of the high four-bit capacitors are grounded.

When the rising edge of the fourth clock cycle approaches, the sampling control signal SP is switched to a low level, so that the gate voltage bootstrap switch SW3 is turned off, and the sampling capacitor Cs is in a "hold state" at this time, which is to reserve a sufficient quantization encoding time for the fully parallel 4-bit analog-to-digital conversion module U4. At this time, the states of the reset signal RST and the high 4-bit enable control signal SB remain unchanged.

When the rising edge of the fifth clock period comes, the reset signal RST is inverted to be low level, the switch capacitor array of the capacitive digital-to-analog conversion module U3 stops resetting, and successive approximation preparation is well prepared; at this time, the high 4-bit enable control signal SB is inverted to a high level, and when the high 4-bit enable control signal SB is in a rising edge state, the four D flip-flops are triggered, the 4-bit quantized encoded data of the fully parallel 4-bit analog-to-digital conversion module U4 is output, and the high 4-bit enable control signal SB is kept in a high level state in the following whole successive approximation process, so that, on one hand, the high 4-bit state is latched, and on the other hand, a channel of a single-pole double-throw switch corresponding to the high 4-bit capacitor of the capacitive digital-to-analog conversion module U3 is opened, so that the four capacitive switches are directly controlled by the level state of the high 4-bit data.

After 6-15 clock cycles, the level states of the reset signal RST, the sampling control signal SP and the high 4-bit enable control signal SB are all kept unchanged, the ADC performs a normal successive approximation quantization encoding process, that is, when a comparison signal COMP of the dynamic comparator U2 of the previous bit is obtained, the level state corresponding to the value of the signal is used to directly control the capacitance switch of the bit in the capacitive digital-to-analog conversion module U3, and the next bit of the capacitive digital-to-analog conversion module U3 is connected to the reference voltage Vref, so that the quantized value of the bit is obtained in the next clock cycle, and finally the whole digital signal Dout [13:0] is obtained.

It should be noted that, in order to make the quantization coding more accurate, each time the self-calibration composite ADC is powered on, under the control of the main control module U9, the capacitor self-calibration module U1 measures the mismatch voltage of the internal capacitor of the capacitive digital-to-analog conversion module U3, so as to obtain the mismatch voltage through quantization, and calibrate the quantization coding structure of the entire ADC. The single-pole double-throw switch SW4 is used for switching a calibration path and a common sampling path under the control of a first self-calibration control signal SC1 output by the main control module U9; the second self-calibration control signal SC2 and the third self-calibration control signal SC3 respectively control the connection state of the non-inverting input terminal and the inverting input terminal of the dynamic comparator U2 and the common-mode voltage Vcm, perform mismatch voltage measurement with the assistance of the common-mode voltage Vcm, and after the common-mode voltage Vcm respectively charges and disconnects the capacitor self-calibration module U1 and the capacitor digital-to-analog conversion module U3, the capacitor self-calibration module U1 can be used to perform mismatch voltage measurement on the internal capacitor of the capacitor digital-to-analog conversion module U3 according to the principle of successive approximation, and under the present design, the relationship between each measurement result of the capacitor self-calibration module U1 and the mismatch voltage of the capacitor corresponding to each bit of the capacitor digital-to-analog conversion module U3 is:

wherein the content of the first and second substances,for the measurement of the ith bit capacitance of the capacitive digital-to-analog conversion module U3 by the capacitance self-calibration module U1,for mismatch voltages of the ith bit capacitance of the capacitive digital-to-analog conversion module U3, i and j are both codes used to mark bits.

After the main control module U9 stores the mismatch voltage, the error correction can be performed on the measurement result during normal measurement.

In conclusion, the dynamic comparator is adopted to replace the traditional common comparator, so that the static direct-current power consumption is avoided, and the overall power consumption of the ADC is greatly reduced; considering that ADC measurement errors mainly come from errors between capacitance values of capacitors produced by a specific process and designed capacitance values, a capacitor self-calibration module is additionally arranged, and internal capacitors of the capacitive digital-to-analog conversion module are calibrated through the capacitor self-calibration module; the full-parallel 4-bit analog-to-digital conversion module is adopted to directly carry out coarse quantization on the analog signal to obtain a high-bit digital signal, and the successive comparison link of the capacitive digital-to-analog conversion module and the dynamic comparator is cooperated, so that the successive comparison time is greatly saved, the ADC quantization coding speed is improved, and the performances of high speed, high precision and low power consumption can be realized.

Under the condition that a 3.3V power supply supplies power and the period of a clock signal CLK is 25ns, a 66.65KHz sinusoidal signal is input, 16384 points are sampled, and Fast Fourier Transform (FFT) is carried out on a simulation result, so that the result is shown in figure 12, the signal-to-noise offset ratio SNDR is 77.81dB, the effective bit ENOB is 12.63 bits, the conversion rate is 2.6MS/s, and the high-speed and high-precision performance is proved.

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