阅读说明：本技术 一种提升信噪比的模拟数字转换器 (Analog-digital converter for improving signal-to-noise ratio ) 是由 何海星 范玉进 张建军 郝帅龙 云天嵩 刘博� 李鑫儒 于 2020-05-11 设计创作，主要内容包括：本发明创造提供了一种提升信噪比的模拟数字转换器,包括：模拟前端,所述模拟前端用于接收模拟信号,并对所述模拟信号进行预处理；模拟数字转换模块,所述模拟数字转换模块包括：至少两个模拟数字转换单元,所述至少两个模拟数字转换单元分别对预处理后的信号进行采样,并转换为数字信号；数字求和计算芯片,所述数字求和计算器用于对转换后的数字信号进行求和,以得到最终数字信号；所述模拟前端与所述模拟数字转换模块中每个模拟数字转换单元电连接,所述每个模拟数字转换单元与所述数字求和计算芯片电连接。实现了对信号噪声的互相消减,能够有效提升信噪比。(The invention provides an analog-digital converter for improving signal-to-noise ratio, which comprises: the analog front end is used for receiving an analog signal and preprocessing the analog signal; an analog-to-digital conversion module, the analog-to-digital conversion module comprising: the at least two analog-digital conversion units respectively sample the preprocessed signals and convert the preprocessed signals into digital signals; a digital summation calculator for summing the converted digital signals to obtain a final digital signal; the analog front end is electrically connected with each analog-digital conversion unit in the analog-digital conversion module, and each analog-digital conversion unit is electrically connected with the digital summation calculation chip. Mutual reduction of signal noise is realized, and the signal-to-noise ratio can be effectively improved.)

1. An analog-to-digital converter for improving signal-to-noise ratio, comprising:

the analog front end is used for receiving an analog signal and preprocessing the analog signal;

an analog-to-digital conversion module, the analog-to-digital conversion module comprising: the at least two analog-digital conversion units respectively sample the preprocessed signals and convert the preprocessed signals into digital signals;

a digital summation calculator for summing the converted digital signals to obtain a final digital signal;

the analog front end is electrically connected with each analog-digital conversion unit in the analog-digital conversion module, and each analog-digital conversion unit is electrically connected with the digital summation calculation chip.

2. The ADC of claim 1, wherein the ADC module is an AD9232 ADC chip.

3. The signal-to-noise ratio boosted adc of claim 1, further comprising:

the timing circuit system is used for providing a clock signal to the analog-digital conversion unit so as to enable the digital signals converted by the analog-digital conversion unit to be in the same time domain;

the timing circuit system and the analog-digital conversion unit are respectively and independently electrically connected.

4. The signal-to-noise ratio boosted adc of claim 3, further comprising:

and the clock input unit is electrically connected with the timing circuit system and is used for inputting a reference clock signal to the timing circuit system.

5. The signal-to-noise ratio-enhanced analog-to-digital converter of claim 1, wherein the analog front end comprises: an amplifier for amplifying a received analog signal.

6. The signal-to-noise ratio boosted adc of claim 1, further comprising: and the digital signal average processing unit is used for averaging the final digital signal according to the later data bit number processing requirement and is electrically connected with the digital summation computing chip.

Technical Field

The invention belongs to the technical field of signal processing, and particularly relates to an analog-digital converter for improving the signal-to-noise ratio.

Background

The AD conversion is analog-to-digital conversion. As the name implies, an analog signal is converted to a digital signal. Mainly includes an integral type, a successive approximation type, a parallel-to-compare type/serial-to-parallel type, a sigma-delta modulation type, and a voltage-to-frequency conversion type. The a/D converter is used to convert analog quantity into digital quantity through a certain circuit. The analog quantity may be an electrical signal such as voltage or current, or a non-electrical signal such as pressure, temperature, humidity, displacement, or sound. Typically, a/D conversion typically goes through 4 processes of sampling, holding, quantizing, and encoding.

With the development of the technology in the electronic industry, the application and requirements of high-speed AD acquisition are higher and higher, the signal-to-noise ratio index is limited by the AD chip process and precision, the sampling signal-to-noise ratio of a single-channel signal is difficult to improve, but in practice, many applications require higher signal-to-noise ratio, and the existing analog-to-digital converter is difficult to meet the corresponding signal-to-noise ratio requirement.

Summary of the invention

In view of the above, the present invention is directed to an analog-to-digital converter for improving the signal-to-noise ratio, so as to improve the signal-to-noise ratio of the analog-to-digital conversion.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

an analog-to-digital converter for boosting a signal-to-noise ratio, the analog-to-digital converter comprising:

the analog front end is used for receiving an analog signal and preprocessing the analog signal;

an analog-to-digital conversion module, the analog-to-digital conversion module comprising: the at least two analog-digital conversion units respectively sample the preprocessed signals and convert the preprocessed signals into digital signals;

a digital summation calculator for summing the converted digital signals to obtain a final digital signal;

the analog front end is electrically connected with each analog-digital conversion unit in the analog-digital conversion module, and each analog-digital conversion unit is electrically connected with the digital summation calculation chip.

Further, the analog-to-digital conversion module is an AD9232 analog-to-digital conversion chip.

Further, the analog-to-digital converter for improving the signal-to-noise ratio further includes:

the timing circuit system is used for providing a clock signal to the analog-digital conversion unit so as to enable the digital signals converted by the analog-digital conversion unit to be in the same time domain;

the timing circuit system and the analog-digital conversion unit are respectively and independently electrically connected.

Further, the analog-to-digital converter for improving the signal-to-noise ratio further includes:

and the clock input unit is electrically connected with the timing circuit system and is used for inputting a reference clock signal to the timing circuit system.

Further, the analog front end comprises: an amplifier for amplifying a received analog signal.

Furthermore, the analog-to-digital converter for improving the signal-to-noise ratio further comprises: and the digital signal average processing unit is used for averaging the final digital signal according to the later data bit number processing requirement and is electrically connected with the digital summation computing chip.

The analog-digital converter for improving the signal-to-noise ratio provided by the invention processes the sampling signals respectively by arranging at least two analog-digital conversion units, mutually reduces different phases generated by different processing signals of different analog-digital conversion units, and adds and processes the signals by using a subsequent digital summation calculation chip, thereby realizing mutual reduction of signal noise and effectively improving the signal-to-noise ratio.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the invention without limitation. In the drawings:

fig. 1 is a schematic diagram of an analog-to-digital converter for improving signal-to-noise ratio according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings, which are merely for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting the invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.

In the description of the invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "connected" and "connected" are to be construed broadly, e.g. as being fixed or detachable or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the creation of the present invention can be understood by those of ordinary skill in the art through specific situations.

The invention will be described in detail with reference to the following embodiments with reference to the attached drawings.

Fig. 1 is a schematic diagram of an analog-to-digital converter for improving signal-to-noise ratio according to an embodiment of the present invention. Referring to fig. 1, the analog-to-digital converter for improving the signal-to-noise ratio includes: the analog front end is used for receiving an analog signal and preprocessing the analog signal; an analog-to-digital conversion module, the analog-to-digital conversion module comprising: the at least two analog-digital conversion units respectively sample the preprocessed signals and convert the preprocessed signals into digital signals; a digital summation calculator for summing the converted digital signals to obtain a final digital signal; the analog front end is electrically connected with each analog-digital conversion unit in the analog-digital conversion module, and each analog-digital conversion unit is electrically connected with the digital summation calculation chip.

In this embodiment, the purpose of the analog front-end (AFE) is to process the analog signal from the signal source, digitize it and analyze it. The AFE typically includes the following functions, as needed: signal amplification, frequency conversion, modulation and demodulation. Typically the AFE is a general purpose unit. The AFE may be a digital circuit in small numbers, an analog circuit device in large numbers, with a simple state machine controlling the multiplexer to transmit the signal to one or more data converters. The AFE may also be a mostly digital circuit, a few analog circuit devices, including one or more data converters with other microcontroller peripherals.

The analog front end may include: an amplifier for amplifying a received analog signal. And corresponding hardware such as a frequency converter, a modulator-demodulator and the like can be added according to actual requirements. So as to better perform preprocessing on the received analog signals.

An analog-to-digital conversion module, the analog-to-digital conversion module comprising: and the at least two analog-digital conversion units respectively sample the preprocessed signals and convert the signals into digital signals. The analog-digital conversion unit is used for sampling the analog signal and completing digital conversion through later quantization and coding.

Since noise is inevitably introduced during quantization, this noise limits the dynamic range. Assuming the input signal is constant, the signal-to-noise ratio (SNR) increases with increasing sampled signal, since the total power of the quantization noise is itself fixed and independent of frequency. Meanwhile, noise is also caused due to nonlinearity of the ADC and jitter of sampling.

As can be seen from the above, the noise portion is generated by the ADC itself, which is random and uncontrollable. In order to control the part of the noise, in this embodiment, the analog-to-digital conversion module may include: at least two analog-to-digital conversion units. The at least two analog-to-digital conversion units may respectively sample the analog signals. The resolution ratio of each analog-digital conversion unit is the same, and because each analog-digital conversion unit has positive or negative phase in the sampling process, the signal-to-noise ratio can be effectively reduced by utilizing multi-path acquisition and subsequent processing.

In this embodiment, the AD9253 high-speed analog-to-digital converter can be selected as the analog-to-digital conversion module, and has the advantages of 4 channels, 14 bits, low power consumption, and full-power analog bandwidth. Since it has 4 channels, which is equivalent to having 4 analog-to-digital conversion units, signal sampling can be performed separately.

The analog-to-digital converter for improving the signal-to-noise ratio further comprises: and the digital summation calculator is used for summing the converted digital signals to obtain a final digital signal. The digital summation calculation chip can receive the digital data converted by the analog-digital conversion module, and obtains corresponding summation data through a synthesis algorithm for processing by a subsequent program. Optionally, the summation processing may be performed by increasing the number of bits, so as to obtain digital data with a higher number of bits. Because part of noise can be reduced in multi-path acquisition, the signal-to-noise ratio can be effectively improved. Even in extreme cases, the noise cannot be reduced. But the signal-to-noise ratio is still the same as for the single acquisition. Therefore, the signal-to-noise ratio can be effectively improved. Meanwhile, the higher the acquisition channel is, the higher the signal-to-noise ratio is. Therefore, in the present embodiment, multi-channel acquisition may be adopted, and for example, a mode of connecting a plurality of AD9253 high-speed analog-to-digital converters in parallel may be adopted to further improve the signal-to-noise ratio. The following table reflects the relationship between the number of channels and the signal-to-noise ratio.

Number of AD channels	Signal-to-noise ratio increment (dB)
		2	3
4	6
		8	9
16	12
		32	15

Optionally, the analog-to-digital converter for improving the signal-to-noise ratio further includes: the timing circuit system is used for providing a clock signal to the analog-digital conversion unit so as to enable the digital signals converted by the analog-digital conversion unit to be in the same time domain; the timing circuit system and the analog-digital conversion unit are respectively and independently electrically connected. Due to the need to ensure that the time domains of the analog-digital conversion units are consistent. Therefore, the clock of each analog-digital conversion unit can be ensured to be consistent through the timing circuit system.

Preferably, the analog-to-digital converter for improving the signal-to-noise ratio further includes: and the clock input unit is electrically connected with the timing circuit system and is used for inputting a reference clock signal to the timing circuit system. Through the clock input unit, the timing circuit system starts timing through a uniform trigger signal. The time of each analog-digital conversion unit is convenient to unify.

In a preferred implementation manner of this embodiment, the analog-to-digital converter for improving the signal-to-noise ratio further includes: and the digital signal average processing unit is used for averaging the final digital signal according to the later data bit number processing requirement and is electrically connected with the digital summation computing chip. The adding and digital signals are processed conveniently and can be directly linked with post-processing.

The analog-digital converter for improving the signal-to-noise ratio provided by the invention processes the sampling signals respectively by arranging at least two analog-digital conversion units, mutually reduces different phases generated by different processing signals of different analog-digital conversion units, and adds and processes the signals by using a subsequent digital summation calculation chip, thereby realizing mutual reduction of signal noise and effectively improving the signal-to-noise ratio.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the invention, so that any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present invention, should be included in the scope of the present invention.