阅读说明：本技术 包括输入/输出焊盘的半导体装置 (Semiconductor device including input/output pad ) 是由 李性柱 金柱赫 于 2020-10-16 设计创作，主要内容包括：本文描述了包括输入/输出焊盘的半导体装置。存储器装置包括：数据焊盘,被设置在第一焊盘区域中并且被配置为接收数据；数据选通焊盘,被设置在第一焊盘区域中并且被配置为接收数据选通信号；时钟焊盘,被设置在与第一焊盘区域相邻的第二焊盘区域中并且被配置为接收时钟信号；数据转换电路,被设置在第一焊盘区域中,并且被配置为基于数据选通信号将通过数据焊盘输入的数据转换为并行数据；以及数据驱动电路,被设置在第一焊盘区域中,并且被配置为基于时钟信号通过全局输入和输出线来传输并行数据。(Semiconductor devices including input/output pads are described herein. The memory device includes: a data pad disposed in the first pad region and configured to receive data; a data strobe pad disposed in the first pad region and configured to receive a data strobe signal; a clock pad disposed in a second pad region adjacent to the first pad region and configured to receive a clock signal; a data conversion circuit disposed in the first pad region and configured to convert data input through the data pad into parallel data based on a data strobe signal; and a data driving circuit disposed in the first pad region and configured to transmit parallel data through the global input and output lines based on a clock signal.)

1. A memory device, comprising:

a data pad disposed in the first pad region and configured to receive data;

a data strobe pad disposed in the first pad region and configured to receive a data strobe signal;

a clock pad disposed in a second pad region adjacent to the first pad region and configured to receive a clock signal;

a data conversion circuit disposed in the first pad region and configured to convert the data input through the data pad into parallel data based on the data strobe signal; and

a data driving circuit disposed in the first pad region and configured to transmit the parallel data through a global input and output line based on the clock signal.

2. The memory device of claim 1, further comprising:

a core region; and

a data receiving circuit disposed in the first pad region and configured to receive data transmitted from the core region through the global input and output lines.

3. The memory device according to claim 2, wherein the data driving circuit and the data receiving circuit share the global input and output line connected between the core region and the first pad region.

4. The memory device of claim 2, further comprising:

a pipe latch circuit configured to store the data received from the data receiving circuit and convert the stored data into serial data to output the serial data; and

an output driving circuit configured to output the serial data through the data pad in synchronization with the clock signal.

5. The memory device of claim 1, further comprising:

a voltage pad disposed in the first pad region and configured to receive a power supply voltage and a ground voltage.

6. The memory device of claim 5, wherein the data pad is disposed symmetrically with another data pad about the voltage pad.

7. The memory device according to claim 6, wherein the data conversion circuit and the data driving circuit are provided in an upper portion of the voltage pad adjacent to the data pad among the data pad and a plurality of voltage pads.

8. A memory device, comprising:

a plurality of data pads disposed in the first pad region and configured to input and output data;

a plurality of voltage pads disposed in the first pad region and configured to receive a power supply voltage and a ground voltage;

a plurality of clock pads disposed in a second pad region adjacent to the first pad region and configured to receive a clock signal; and

a data alignment circuit disposed in the first pad region and configured to align the input and output data in response to the clock signal,

wherein two of the plurality of data pads correspond to one of the plurality of voltage pads, the one voltage pad being disposed between the two data pads.

9. The memory device according to claim 8, wherein the data alignment circuit is disposed on an upper portion of a corresponding data pad among the plurality of data pads and a voltage pad adjacent to the corresponding data pad among the plurality of voltage pads.

10. The memory device of claim 9, wherein the data alignment circuit is partially disposed in the upper portion of the adjacent voltage pad, and another data alignment circuit adjacent to the data alignment circuit is partially disposed in a remaining portion of the upper portion of the adjacent voltage pad.

11. The memory device of claim 8, further comprising:

a data strobe pad disposed in the first pad region and configured to receive a data strobe signal.

12. The memory device of claim 11, wherein the data alignment circuit comprises:

a data conversion circuit configured to convert the data input to the plurality of data pads into parallel data in response to the data strobe signal; and

a data driving circuit configured to transmit the parallel data through a global input and output line in response to the clock signal.

13. The memory device of claim 12, wherein the data alignment circuit further comprises:

a data receiving circuit configured to receive data transferred from a core region of the memory device through the global input and output lines.

14. The memory device according to claim 13, wherein the data driving circuit and the data receiving circuit share the global input and output line connected between the core region and the first pad region.

15. The memory device of claim 13, wherein the data alignment circuit further comprises:

a pipe latch circuit configured to store data received from the data receiving circuit and convert the stored data into serial data to output the serial data; and

an output driving circuit configured to output the serial data to the plurality of data pads in synchronization with the clock signal.

16. A semiconductor device, comprising:

a core region; and

a pad region including a first pad region and a second pad region disposed adjacent to the first pad region,

wherein a plurality of data pads configured to input and output data, a data strobe pad configured to receive a data strobe signal, and a plurality of voltage pads configured to receive a power supply voltage and a ground voltage are disposed in the first pad region,

wherein a clock pad configured to receive a clock signal is disposed in the second pad region, and

wherein a data alignment circuit configured to align the input and output data in response to the clock signal is disposed in the first pad region to overlap the plurality of data pads and the plurality of voltage pads.

17. The semiconductor device according to claim 16, wherein two of the plurality of data pads correspond to one of the plurality of voltage pads, the one voltage pad being provided between the two data pads.

18. The semiconductor device according to claim 16, wherein a plurality of command/address pads configured to receive a command/address are provided in the second pad region.

19. The semiconductor device according to claim 16, further comprising a global input and output line connected between the core region and the first pad region.

Technical Field

Various embodiments relate to a semiconductor device, and more particularly, to a memory device that aligns and processes data sequentially input or output through input and output pads.

Background

As the operating speed of semiconductor systems such as memory systems increases, memory devices included in the memory systems are required to have high data transfer rates. In particular, as the user's desire for performance is higher, memory devices applied to mobile environments are required to transmit data at higher bandwidths.

The memory device may align input/output data in a multi-bit prefetch method to process data at a high transfer rate and high bandwidth. That is, in a write operation, the memory device may align sequentially input data and then store the aligned data in the memory cell array in parallel. In a read operation, the memory device may read data from the memory cell array in parallel and then sequentially output the data.

When data is input to the memory device in synchronization with the data strobe signal, the input data may be processed in synchronization with the clock signal. Therefore, the memory device needs to perform a cross-domain operation to allow data synchronized with the data strobe signal to be synchronized with the clock signal.

Disclosure of Invention

Various embodiments are directed to a semiconductor device having a plurality of input/output pads and an optimized arrangement of circuits for aligning input/output data within a limited area.

According to one embodiment, a memory device may include: a data pad disposed in the first pad region and configured to receive data; a data strobe pad disposed in the first pad region and configured to receive a data strobe signal; a clock pad disposed in a second pad region adjacent to the first pad region and configured to receive a clock signal; a data conversion circuit disposed in the first pad region and configured to convert data input through the data pad into parallel data based on a data strobe signal; and a data driving circuit disposed in the first pad region and configured to transmit parallel data through the global input and output lines based on a clock signal.

According to one embodiment, a memory device may include: a plurality of data pads disposed in the first pad region and configured to input and output data; a plurality of voltage pads disposed in the first pad region and configured to receive a power supply voltage and a ground voltage; a plurality of clock pads disposed in a second pad region adjacent to the first pad region and configured to receive a clock signal; and a data alignment circuit disposed in the first pad region and configured to align input and output data in response to a clock signal, wherein two data pads of the plurality of data pads correspond to one voltage pad of the plurality of voltage pads, and the one voltage pad is disposed between the two data pads.

According to one embodiment, a semiconductor apparatus may include: a core region; a pad region including a first pad region and a second pad region disposed adjacent to the first pad region, wherein a plurality of data pads configured to input and output data, a data strobe pad configured to receive a data strobe signal, and a plurality of voltage pads configured to receive a power supply voltage and a ground voltage are disposed in the first pad region, wherein a clock pad configured to receive a clock signal is disposed in the second pad region, and wherein a data alignment circuit configured to align the input and output data in response to the clock signal is disposed in the first pad region to overlap the plurality of data pads and the plurality of voltage pads.

Drawings

FIG. 1 is a diagram illustrating a memory device performing a multi-bit prefetch operation.

Fig. 2 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

Fig. 3 is a diagram illustrating a data alignment circuit shown in fig. 2.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

Note that references to "one embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily to the same embodiment(s).

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.

It will be further understood that the terms "comprises," "comprising," "… …," "includes," and "including … …," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms may also include the plural forms and vice versa, unless the context clearly dictates otherwise. The articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

FIG. 1 is a diagram illustrating a memory device 100 that performs a multi-bit prefetch operation. The memory device 100 may include a CORE AREA (CORE AREA)110, a peripheral AREA (PERI AREA)120, and a PAD AREA (PAD AREA) 130.

The memory device 100 may include a plurality of memory cells (not shown) in the core area 110. In a write operation, the memory device 100 may align sequentially input data and then store the aligned data in a plurality of memory cells in parallel. In a read operation, the memory device 100 may read data from a plurality of memory cells in parallel and then sequentially output the read data.

For such an operation, the memory device 100 may sequentially input and output data in synchronization with the data strobe signal and process internally transferred data in synchronization with the clock signal. Referring to fig. 1, the memory device 100 may include a data strobe domain circuit 122 and a clock domain circuit 124 in the peripheral region 120. The data strobe domain circuit 122 may align data in response to a data strobe signal, and the clock domain circuit 124 may process the aligned data in response to a clock signal.

In addition, the memory device 100 may include a plurality of input/output pads in the pad region 130. The plurality of input/output pads may be divided into a data pad DQ and a data strobe pad DQs for inputting/outputting data and data strobe signals, and a command/address pad C/a and a clock pad CLK for receiving command/address and clock signals.

The memory device 100 may perform a cross-domain operation to allow data synchronized with a data strobe signal to be synchronized with a clock signal. That is, the memory device 100 can adjust the delay of data by reflecting the timing difference between the data strobe signal and the clock signal.

Referring to fig. 1, when the data strobe domain circuit 122 and the clock domain circuit 124 are disposed in the peripheral region 120, a difference in length between a signal path from the data strobe pad DQS to the data strobe domain circuit 122 and a signal path from the clock pad CLK to the clock domain circuit 124 may increase. In order to match the timing with the clock signal transmitted through the relatively long path, the memory device 100 may include a delay line for delaying the data output from the data strobe domain circuit 122 in the peripheral region. The delay line may have a relatively large amount of delay and thus increase the area of the memory device 100.

Fig. 2 is a diagram illustrating a memory device 200 according to one embodiment of the present disclosure. The memory device 200 may include a core region 210 and a pad region 220.

As described above, the memory device 200 may include a plurality of memory cells (not shown) in the core area 210. In a write operation, the memory device 200 may align sequentially input data and then store the aligned data in a plurality of memory cells in parallel. In a read operation, the memory device 200 may read data from a plurality of memory cells in parallel and then sequentially output the read data.

The pad region 220 of the memory device 200 may be divided into a first pad region 222 and a second pad region 224 disposed adjacent to the first pad region 222. In the first pad region 222, a data pad DQ and a data strobe pad DQs for inputting and outputting data and a data strobe signal may be disposed. In the second pad region 224, a command/address pad C/a and a clock pad CLK for receiving command/address and clock signals may be disposed.

According to one embodiment of the present disclosure, the data alignment circuit 226 provided in the first pad region 222 may align data input/output through the data pad DQ in response to a clock signal input through the clock pad CLK. That is, the data alignment circuit 226 may align data sequentially input through the data pads DQ and then transfer the aligned data to the core region 210 through the global input/output line GIO connected between the core region 210 and the first pad region 222. The data alignment circuit 226 may align data read from the plurality of memory cells through the global input output line GIO and then sequentially transfer the aligned data to the data pad DQ.

The data alignment circuit 226 is disposed to overlap the corresponding data pad DQ so that the length of a data line between the data alignment circuit 226 and the data pad DQ can be reduced. However, since the data alignment circuit 226 has a larger area than the data pad DQ, the memory device 200 may further include voltage pads VDD, VSS, and VDQ for receiving a power supply voltage, a ground voltage, and a voltage for the data pad DQ in the first pad region 222.

In this case, the data pads DQ may be symmetrically disposed with respect to the voltage pads VDD, VSS, and VDQ. That is, two data pads DQ may be symmetrically disposed with respect to one voltage pad VDD, VSS, or VDQ, and such a structure of the data pads DQ and the voltage pads VDD, VSS, and VDQ may be repeatedly disposed.

Accordingly, the data alignment circuit 226 may be disposed in an upper portion of the corresponding data pad DQ and in upper portions of the voltage pads VDD, VSS, and VDQ adjacent to the corresponding data pad DQ. In other words, the data alignment circuit 226 may be disposed in a portion perpendicular to the corresponding data pad DQ and the voltage pads VDD, VSS, and VDQ adjacent to the corresponding data pad DQ. Fig. 2 illustrates an example in which the data pad DQ corresponding to the data alignment circuit 226 is adjacent to the voltage pad VDD for receiving a power supply voltage. In the embodiment shown in fig. 2, the data alignment circuit 226 may be disposed in an upper portion of the data pad DQ and the voltage pad VDD. As a result, a space in which the data alignment circuit 226 having a relatively larger area than the data pad DQ is disposed adjacent to the data pad DQ can be secured.

Referring to fig. 2, the data alignment circuit 226 may be disposed to overlap a corresponding data pad DQ and to partially overlap an adjacent voltage pad VDD. Another data alignment circuit may be disposed to overlap the remaining portion (i.e., non-overlapping portion) of the adjacent voltage pad VDD. That is, the data alignment circuit may share an upper portion of the adjacent voltage pad VDD.

Fig. 3 is a diagram illustrating the data alignment circuit 226 shown in fig. 2.

The data alignment circuit 226 may parallelize data sequentially input to the data pads DQ and transmit the parallelized data to the core region through the global input/output lines GIO. To this end, the data alignment circuit 226 may include an input circuit 310, a data conversion circuit 320, a selection circuit 330, and a data driving circuit 340.

The input circuit 310 may include a plurality of input buffers. The input circuit 310 may receive data input through the data pad DQ and transmit the data to the data conversion circuit 320. The data conversion circuit 320 may convert data transmitted through the input circuit 310 into parallel data in response to the data strobe signal DQS/DQSB. When the selection circuit 330 selects and outputs a plurality of parallel data converted by the data conversion circuit 320, the data driving circuit 340 may transmit output data of the selection circuit 330 through the global input output line GIO in response to the clock signal CLK/CLKB. For reference, the data strobe signal DQSB is a complementary signal of the data strobe signal DQS, and the clock signal CLKB is a complementary signal of the clock signal CLK.

The memory device 200 may include a data conversion circuit 320 performing an operation based on the data strobe signal DQS/DQSB and a data driving circuit 340 performing an operation based on the clock signal CLK/CLKB in the first pad region 222. Accordingly, a difference in path length between the data strobe signal DQS/DQSB and the clock signal CLK/CLKB may be reduced. As a result, the memory device 200 can perform a cross-domain operation by adjusting the timing of a buffer, a repeater, or the like without a delay line having a relatively large amount of delay. The delay line may be eliminated and the size of a driver circuit for driving the delay line may be reduced, so that the entire area and power consumption of the memory device 200 may be reduced.

In addition, the data alignment circuit 226 may sequentially output the parallel data read through the global input output line GIO to the data pad DQ. To this end, the data alignment circuit 226 may further include a data receiving circuit 350, a pipe latch circuit 360, an output driving circuit 370, and an output circuit 380.

The data receiving circuit 350 may receive data loaded on the global input output line GIO and selectively output the data according to a bandwidth that may be set. The pipe latch circuit 360 may store output data of the data reception circuit 350, convert the stored data into serial data, and output the serial data. The output driver circuit 370 may output the serial data converted by the pipe latch circuit 360 to the data pad DQ through the output circuit 380 in synchronization with the clock signal CLK/CLKB.

The data driving circuit 340 and the data receiving circuit 350 may share the global input/output line GIO connected between the core region 210 and the first pad region 222 of the memory device 200. Accordingly, in the memory device 200, the number of data lines ("4", see fig. 2) connected from the core region 210 to the first pad region 222 (i.e., the pad region 220) may be reduced. When the data driving circuit 340 and the data receiving circuit 350 are disposed in another region except the pad region 220, the data driving circuit 340 and the data receiving circuit 350 do not share a data line between the disposed region and the pad region 220. Therefore, the number of data lines ("6" to "8", see fig. 1) may be increased, and the entire length of the data lines may be increased.

Further, an output driving circuit 370 that finally outputs data in synchronization with the clock signal CLK/CLKB is provided in the first pad region 222, so that a path through which data in synchronization with the clock signal CLK/CLKB is output to the data pad DQ can be reduced. According to the memory device 200, delay that may additionally occur in data synchronized with the clock signal CLK/CLKB can be reduced, and data can be output at more accurate timing.

According to the embodiments of the present invention, a plurality of input/output pads and circuits for aligning input/output data can be optimally disposed in a limited area of a memory device. The input/output lines can be shared by a plurality of input/output pads and circuits, so that the entire area of the memory device can be reduced. Thus, die yield of the memory device may be increased.

Further, the memory device can adjust the timing of performing the cross-domain operation without using a delay line having a relatively large amount of delay. As the delay line is removed from the memory device, the size of a driver circuit for driving the delay line may also be reduced, so that power consumption and the area of the memory device may be reduced.

Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.