阅读说明：本技术 一种用于电力线载波通信的功率放大电路 (Power amplification circuit for power line carrier communication ) 是由 不公告发明人 于 2019-10-22 设计创作，主要内容包括：本发明提供一种用于电力线载波通信的功率放大电路,包括输入电路、偏置电路、驱动电路、缓冲电路、转换速率增强电路和输出电路；所述输入电路用于将输入电压信号转换成电流信号；所述偏置电路用于为所述驱动电路提供偏置；所述驱动电路用于对所述输入电路产生的电流信号进行放大,输出电压信号给所述缓冲电路；所述缓冲电路用于隔离所述驱动电路和所述输出电路；所述转换速率增强电路用于提高所述输出电路的转换速率；所述输出电路用于向负载输出功率放大后的信号。本发明可在最大限度降低静态功耗的同时实现超高输出摆幅和线性度,能够满足电力线载波通信应用的功率需求。(The invention provides a power amplification circuit for power line carrier communication, which comprises an input circuit, a bias circuit, a drive circuit, a buffer circuit, a conversion rate enhancement circuit and an output circuit, wherein the input circuit is connected with the bias circuit; the input circuit is used for converting an input voltage signal into a current signal; the bias circuit is used for providing bias for the driving circuit; the driving circuit is used for amplifying the current signal generated by the input circuit and outputting a voltage signal to the buffer circuit; the buffer circuit is used for isolating the drive circuit and the output circuit; the slew rate enhancement circuit is used for improving the slew rate of the output circuit; the output circuit is used for outputting the signal after power amplification to a load. The invention can realize ultrahigh output swing amplitude and linearity while reducing static power consumption to the maximum extent, and can meet the power requirement of power line carrier communication application.)

1. A power amplification circuit for power line carrier communications, comprising: the circuit comprises an input circuit, a bias circuit, a driving circuit, a buffer circuit, a slew rate enhancement circuit and an output circuit;

the input circuit is used for converting an input voltage signal into a current signal;

the bias circuit is used for providing bias for the driving circuit;

the driving circuit is used for amplifying the current signal generated by the input circuit and outputting a voltage signal to the buffer circuit;

the buffer circuit is used for isolating the drive circuit and the output circuit;

the slew rate enhancement circuit is used for improving the slew rate of the output circuit;

the output circuit is used for outputting the signal after power amplification to a load.

2. The power amplification circuit of claim 1, wherein:

the input circuit comprises a first NPN type triode, a second NPN type triode and a first transistor;

the bias circuit comprises a second transistor, a third transistor, a fourth transistor and a fifth transistor;

the driving circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

the buffer circuit comprises a twelfth transistor, a thirteenth transistor, a first voltage buffer circuit and a second voltage buffer circuit;

the slew rate enhancement circuit comprises a first transient enhancement circuit and a second transient enhancement circuit;

the output circuit includes a fourteenth transistor and a fifteenth transistor.

3. The power amplification circuit of claim 2, wherein: a base electrode of the first NPN type triode is connected with a first input voltage signal, an emitting electrode of the first NPN type triode is connected with an emitting electrode of the second NPN type triode and a drain electrode of the first transistor, and a collecting electrode of the first NPN type triode is connected with the bias circuit; a base electrode of the second NPN type triode is connected with a second input voltage signal, an emitting electrode of the second NPN type triode is connected with an emitting electrode of the first NPN type triode and a drain electrode of the first transistor, and a collecting electrode of the second NPN type triode is connected with the bias circuit; the grid electrode of the first transistor is connected with a fourth bias voltage, the source electrode of the first transistor is connected with the ground, and the drain electrode of the first transistor is connected with the common end of the first NPN type triode and the second NPN type triode.

4. The power amplification circuit of claim 2, wherein: the grid electrode of the second transistor is connected with a third bias voltage, the source electrode of the second transistor is connected with a power supply voltage, and the drain electrode of the second transistor is connected with the source electrode of the third transistor; the grid electrode of the third transistor is connected with a fifth bias voltage, the source electrode of the third transistor is connected with the collector electrode of the first NPN type triode, and the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor; a gate of the fourth transistor is connected to a sixth bias voltage, a source thereof is connected to a drain of the fifth transistor, and a drain thereof is connected to a drain of the third transistor; the gate of the fifth transistor is connected to a fourth bias voltage, the source is connected to ground, and the drain is connected to the source of the fourth transistor.

5. The power amplification circuit of claim 2, wherein: the grid electrode of the sixth transistor is connected with a third bias voltage, the source electrode of the sixth transistor is connected with a power supply voltage, and the drain electrode of the sixth transistor is connected with the source electrode of the seventh transistor; a gate of the seventh transistor is connected to a fifth bias voltage, a source of the seventh transistor is connected to a drain of the sixth transistor, and a drain of the seventh transistor is connected to a source of the eighth transistor and a drain of the ninth transistor; a gate of the eighth transistor is connected to a second bias voltage, a source of the eighth transistor is connected to a drain of the seventh transistor, a drain of the ninth transistor, and a first input port of the first voltage buffer circuit, and a drain of the eighth transistor is connected to a source of the ninth transistor, a drain of the tenth transistor, and a first input port of the second voltage buffer circuit; a gate of the ninth transistor is connected to a first bias voltage, a source of the ninth transistor is connected to a drain of the eighth transistor, a drain of the tenth transistor, and a first input port of the second voltage buffer circuit, and a drain of the ninth transistor is connected to a source of the eighth transistor, a drain of the seventh transistor, and a first input port of the first voltage buffer circuit; a gate of the tenth transistor is connected to a sixth bias voltage, a source of the tenth transistor is connected to a drain of the eleventh transistor, and a drain of the tenth transistor is connected to a drain of the eighth transistor, a source of the ninth transistor, and a first input port of the second voltage buffer circuit; the eleventh transistor has a gate connected to a fourth bias voltage, a source connected to ground, and a drain connected to the source of the tenth transistor.

6. The power amplification circuit of claim 2, wherein: a grid electrode of the twelfth transistor is connected with a third bias voltage, a source electrode of the twelfth transistor is connected with a power supply voltage, and a drain electrode of the twelfth transistor is connected with a first output port of the first voltage buffer circuit, a grid electrode of the fourteenth transistor and a first output port of the first transient state enhancement circuit; the gate of the thirteenth transistor is connected with a fourth bias voltage, the source of the thirteenth transistor is connected with the ground, and the drain of the thirteenth transistor is connected with the first output port of the second voltage buffer circuit, the gate of the fifteenth transistor and the first output port of the second transient enhancement circuit; the first voltage buffer circuit comprises a first input port, a first output port and a second output port, wherein the first input port is connected with the drain electrode of the seventh transistor, the source electrode of the eighth transistor and the drain electrode of the ninth transistor, the first output port is connected with the drain electrode of the twelfth transistor, the gate electrode of the fourteenth transistor and the first output port of the first transient state enhancement circuit, and the second output port is connected with the second output port of the second transient state enhancement circuit; the second voltage buffer circuit comprises a first input port, a first output port and a second output port, wherein the first input port is connected with the drain electrode of the tenth transistor, the source electrode of the ninth transistor and the drain electrode of the eighth transistor, the first output port is connected with the drain electrode of the thirteenth transistor, the gate electrode of the fifteenth transistor and the first output port of the second transient state enhancement circuit, and the second output port is connected with the second output port of the first transient state enhancement circuit.

7. The power amplification circuit of claim 2, wherein: the first transient state enhancement circuit comprises a first output port and a second output port, the first output port is connected with the drain electrode of the twelfth transistor, the grid electrode of the fourteenth transistor and the first output port of the first voltage buffer circuit, and the second output port is connected with the second output port of the second voltage buffer circuit; the second transient enhancement circuit comprises a first output port and a second output port, wherein the first output port is connected with the drain electrode of the thirteenth transistor, the grid electrode of the fifteenth transistor and the first output port of the second voltage buffer circuit, and the second output port is connected with the second output port of the first voltage buffer circuit.

8. The power amplification circuit of claim 2, wherein: a grid electrode of the fourteenth transistor is connected with a drain electrode of the twelfth transistor, a first output port of the first voltage buffer circuit and a first output port of the first transient state enhancing circuit, a source electrode of the fourteenth transistor is connected with a power supply voltage, and a drain electrode of the fourteenth transistor is connected with a drain electrode of the fifteenth transistor; the gate of the fifteenth transistor is connected with the first output port of the second voltage buffer circuit and the first output port of the second transient enhancement circuit, the source of the fifteenth transistor is connected with the ground, and the drain of the fifteenth transistor is connected with the drain of the fourteenth transistor to form rail-to-rail output.

Technical Field

The present invention relates to a power amplifier circuit, and more particularly, to a power amplifier circuit for power line carrier communication.

Background

Communication and information are important guarantees for smart grid construction and development. The PLC (power line communication) fully utilizes the line resources of the power grid, does not need to re-route and erect the network, and has become a main technical means for communication in the last kilometer of the smart power grid and home networks in China. The power amplifier is required to provide sufficient power and linearity under both light and heavy load conditions of the power line load. The traditional power amplifying circuit generally adopts a current negative feedback structure of a Bipolar process, and has the defects of high implementation cost, high harmonic distortion, limitation to foreign technologies and the like.

The above background disclosure is only for the purpose of assisting in understanding the inventive concepts and technical solutions of the present application and does not necessarily pertain to the prior art of the present application, and should not be used to assess the novelty and inventive step of the present application in the absence of explicit evidence to suggest that such matter has been disclosed at the filing date of the present application.

Disclosure of Invention

The invention provides a power amplifying circuit for power line carrier communication, which has the advantages of high performance, low cost and suitability for domestic power grid environment.

A power amplifying circuit for power line carrier communication comprises an input circuit, a bias circuit, a driving circuit, a buffer circuit, a conversion rate enhancement circuit and an output circuit; the input circuit is used for converting an input voltage signal into a current signal; the bias circuit is used for providing bias for the driving circuit; the driving circuit is used for amplifying the current signal generated by the input circuit and outputting a voltage signal to the buffer circuit; the buffer circuit is used for isolating the drive circuit and the output circuit; the slew rate enhancement circuit is used for improving the slew rate of the output circuit; the output circuit is used for outputting the signal after power amplification to a load.

The input circuit comprises a first NPN type triode, a second NPN type triode and a first transistor; the bias circuit comprises a second transistor, a third transistor, a fourth transistor and a fifth transistor; the driving circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the buffer circuit comprises a twelfth transistor, a thirteenth transistor, a first voltage buffer circuit and a second voltage buffer circuit; the slew rate enhancement circuit comprises a first transient enhancement circuit and a second transient enhancement circuit; the output circuit includes a fourteenth transistor and a fifteenth transistor.

Compared with the prior art, the invention has the beneficial effects that:

the power amplifying circuit for power line carrier communication provided by the invention can realize ultrahigh output swing amplitude and linearity while reducing static power consumption to the maximum extent, and can meet the power requirement of power line carrier communication application.

Drawings

Fig. 1 is a schematic circuit diagram of a power amplifier circuit for power line carrier communication according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described in further detail below with reference to the drawings in the embodiments of the present invention, and it is apparent that the embodiments described herein are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. The connection may be for fixation or for circuit connection.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the embodiments of the present invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be in any way limiting of the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In a preferred embodiment, as shown in fig. 1, a power amplifying circuit for power line carrier communication is provided, which includes: the circuit comprises an input circuit, a bias circuit, a driving circuit, a buffer circuit, a conversion rate enhancement circuit and an output circuit. The input circuit is connected with an input voltage signal and used for converting the input voltage signal into a current signal; the bias circuit is used for providing bias for the driving circuit; the driving circuit is used for amplifying a current signal generated by the input circuit and outputting a voltage signal to the buffer circuit; the buffer circuit is used for isolating the drive circuit from the output circuit and improving the stability of the system and comprises a first voltage buffer circuit and a second voltage buffer circuit; the slew rate enhancement circuit is used for improving the slew rate of the output circuit and comprises a first transient enhancement circuit and a second transient enhancement circuit; the output circuit is used for outputting the signal after power amplification to a load.

Specifically, in an embodiment of the present invention, the input circuit includes: a first NPN transistor Q1, a second NPN transistor Q2, and a first transistor M1; a base electrode of the first NPN triode Q1 is connected to a first input voltage signal VINN, an emitter electrode of the first NPN triode Q2 is connected to an emitter electrode of the second NPN triode Q2 and a drain electrode of the first transistor M1, and a collector electrode of the first NPN triode Q1 is connected to the bias circuit; a base electrode of the second NPN type triode Q2 is connected with a second input voltage signal VINP, an emitter electrode of the second NPN type triode Q1 is connected with a drain electrode of the first transistor M1, and a collector electrode of the second NPN type triode Q2 is connected with the bias circuit; the first transistor M1 has a gate connected to a fourth bias voltage VB4, a source connected to ground, and a drain connected to a common terminal of the first NPN transistor Q1 and the second NPN transistor Q2.

The bias circuit includes: a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5; the gate of the second transistor M2 is connected to a third bias voltage VB3, the source is connected to a power supply voltage VCC, and the drain is connected to the source of the third transistor M3; a gate of the third transistor M3 is connected to a fifth bias voltage VB5, a source thereof is connected to a collector of the first NPN transistor Q1, and a drain thereof is connected to a drain of the fourth transistor M4; the gate of the fourth transistor M4 is connected to a sixth bias voltage VB6, the source is connected to the drain of the fifth transistor M5, and the drain is connected to the drain of the third transistor M3; the fifth transistor M5 has a gate connected to a fourth bias voltage VB4, a source connected to ground, and a drain connected to the source of the fourth transistor M4. Wherein the bias circuit is used for providing bias for the input circuit and the driving circuit.

The driving circuit includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11; the gate of the sixth transistor M6 is connected to the third bias voltage VB3, the source is connected to the power supply voltage VCC, and the drain is connected to the source of the seventh transistor M7; the gate of the seventh transistor M7 is connected to a fifth bias voltage VB5, the source is connected to the drain of the sixth transistor M6, and the drain is connected to the source of the eighth transistor M8 and the drain of the ninth transistor M9; a gate of the eighth transistor M8 is connected to a second bias voltage VB2, a source thereof is connected to the drain of the seventh transistor M7, the drain of the ninth transistor M9 and the first input port BI1 of the first voltage buffer circuit, and a drain thereof is connected to the source of the ninth transistor M9, the drain of the tenth transistor M10 and the first input port BI2 of the second voltage buffer circuit; the gate of the ninth transistor M9 is connected to the first bias voltage VB1, the source is connected to the drain of the eighth transistor M8, the drain of the tenth transistor M10 and the first input port BI2 of the second voltage buffer circuit, and the drain is connected to the source of the eighth transistor, the drain of the seventh transistor and the first input port BI1 of the first voltage buffer circuit; a gate of the tenth transistor M10 is connected to a sixth bias voltage VB6, a source thereof is connected to a drain of the eleventh transistor M11, and a drain thereof is connected to a drain of the eighth transistor M8, a source of the ninth transistor M9, and the first input port BI2 of the second voltage buffer circuit; the eleventh transistor M11 has a gate connected to the fourth bias voltage VB4, a source connected to ground, and a drain connected to the source of the tenth transistor M10.

The buffer circuit includes a twelfth transistor M12, a thirteenth transistor M13, a first voltage buffer circuit, and a second voltage buffer circuit; the gate of the twelfth transistor M12 is connected to the third bias voltage VB3, the source is connected to the power supply voltage VCC, and the drain is connected to the first output port BO11 of the first voltage buffer circuit, the gate of the fourteenth transistor M14, and the first output port SO11 of the first transient enhancement circuit; the gate of the thirteenth transistor M13 is connected to the fourth bias voltage VB4, the source is connected to ground, and the drain is connected to the first output port BO21 of the second voltage buffer circuit, the gate of the fifteenth transistor M15, and the first output port SO21 of the second transient enhancement circuit; the first voltage buffer circuit comprises a first input port BI1, a first output port BO11 and a second output port BO12, wherein the first input port BI1 is connected to the drain of the seventh transistor M7, the source of the eighth transistor M8 and the drain of the ninth transistor M9, the first output port BO11 is connected to the drain of the twelfth transistor M12, the gate of the fourteenth transistor M14 and the first output port SO11 of the first transient enhancement circuit, and the second output port BO12 is connected to the second output port SO22 of the second transient enhancement circuit; the second voltage buffer circuit includes a first input port BI2, a first output port BO21, and a second output port BO22, wherein the first input port BI2 is connected to the drain of the tenth transistor M10, the source of the ninth transistor M9, and the drain of the eighth transistor M8, the first output port BO21 is connected to the drain of the thirteenth transistor M13, the gate of the fifteenth transistor M15, and the first output port SO21 of the second transient state enhancement circuit, and the second output port is connected to the second output port SO12 of the first transient state enhancement circuit.

The slew rate enhancement circuit comprises a first transient enhancement circuit and a second transient enhancement circuit; the first transient enhancement circuit comprises a first output port SO11 and a second output port SO12, the first output port SO11 is connected with the drain of the twelfth transistor M12, the gate of the fourteenth transistor M14 and the first output port BO11 of the first voltage buffer circuit, and the second output port SO12 is connected with the second output port BO22 of the second voltage buffer circuit; the second transient enhancement circuit comprises a first output port SO21 and a second output port SO22, wherein the first output port SO21 is connected to the drain of the thirteenth transistor M13, the gate of the fifteenth transistor M15 and the first output port BO21 of the second voltage buffer circuit, and the second output port is connected to the second output port BO12 of the first voltage buffer circuit.

The output circuit comprises a fourteenth transistor M14, a fifteenth transistor M15; wherein, the gate of the fourteenth transistor M14 is connected to the drain of the twelfth transistor M12, the first output port BO11 of the first voltage buffer circuit and the first output port SO11 of the first transient-state enhancement circuit, the source is connected to the power supply voltage VCC, and the drain is connected to the drain of the fifteenth transistor M15; the gate of the fifteenth transistor M15 is connected to the first output port BO21 of the second voltage buffer circuit and the first output port SO21 of the second transient-enhanced circuit, the source is connected to ground, and the drain is connected to the drain of the fourteenth transistor M14 to form a rail-to-rail output, which is used for driving a load to output a power amplification signal.

In the embodiments, the power amplification circuit for power line carrier communication provided by the invention adopts the MOS transistor and the unique rail-to-rail output architecture, has extremely high integration level and excellent performance, realizes ultrahigh output swing amplitude and linearity while reducing static power consumption to the maximum extent, and can meet the power requirement of power line carrier communication application.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and thus, the invention is not to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.