阅读说明：本技术 用于电能表管理芯片验证的系统及装置 (System and device for verifying electric energy meter management chip ) 是由 吕志宁 陈红芳 唐文魁 宁柏锋 刘威 邓巍 习伟 匡晓云 姚浩 于杨 简淦杨 于 2019-12-16 设计创作，主要内容包括：本发明公开了一种用于电能表管理芯片验证的系统及装置。所述用于电能表管理芯片验证的系统包括内置有待检验芯片程序的FPGA及与FPGA连接的FPGA子板；其中,FPGA子板包括与FPGA连接的信号处理模块,用于采集电压信号及电流信号,并将电压信号及电流信号转换为数字信号后发送至FPGA；FPGA根据待检验芯片程序及数字信号验证待检验芯片的功能是否满足设计要求。其中,通过将电能表管理芯片的运行程序放置于FPGA中,配合FPGA子板模拟电能表正常运行环境,从而对运行程序进行仿真验证,使得在设计电能表管理芯片的过程中可以反复调试,解决了在开发电能表管理芯片时无专用测试装置的技术问题,降低了开发成本。(The invention discloses a system and a device for verifying an electric energy meter management chip. The system for verifying the electric energy meter management chip comprises an FPGA (field programmable gate array) with a built-in chip program to be verified and an FPGA daughter board connected with the FPGA; the FPGA daughter board comprises a signal processing module connected with the FPGA, and is used for acquiring voltage signals and current signals, converting the voltage signals and the current signals into digital signals and then sending the digital signals to the FPGA; and the FPGA verifies whether the function of the chip to be detected meets the design requirement according to the program of the chip to be detected and the digital signal. The running program of the electric energy meter management chip is placed in the FPGA, and the FPGA daughter board is matched with the FPGA daughter board to simulate the normal running environment of the electric energy meter, so that the running program is subjected to simulation verification, the electric energy meter management chip can be repeatedly debugged in the process of designing the electric energy meter management chip, the technical problem that a special testing device is not used when the electric energy meter management chip is developed is solved, and the development cost is reduced.)

1. A system for verifying an electric energy meter management chip is characterized by comprising an FPGA (field programmable gate array) with a built-in chip program to be verified and an FPGA daughter board connected with the FPGA; wherein the content of the first and second substances,

the FPGA daughter board comprises a signal processing module, and the signal processing module is connected with the FPGA and used for acquiring a voltage signal and a current signal, converting the voltage signal and the current signal into digital signals and then sending the digital signals to the FPGA;

and the FPGA is used for verifying whether the function of the chip to be detected meets the design requirement according to the program of the chip to be detected and the digital signal.

2. The system for electric energy meter management chip verification of claim 1, wherein the signal processing module comprises a voltage current sampling circuit, an analog-to-digital converter, a random access memory and a metering circuit; the voltage and current sampling circuit is respectively connected with the bus and the analog-to-digital converter, the analog-to-digital converter is connected with the random access memory, the random access memory is connected with the metering circuit, and the metering circuit is connected with the FPGA.

3. The system for electric energy meter management chip verification according to claim 2, wherein the FPGA daughter board further comprises an FPGA interface, a pin corresponding to a function of the chip to be verified is disposed on the FPGA interface, and the signal processing module is connected to the FPGA through the FPGA interface.

4. The system for power meter management chip validation of claim 3, wherein the number of pins of the FPGA interface is greater than the number of pins of the chip to be verified.

5. The system for electric energy meter management chip validation of claim 4, wherein the FPGA daughter board further comprises an electric energy meter peripheral module, the electric energy meter peripheral module comprising keys, a display screen, an indicator light and a communication circuit; the key, the display screen, the indicator light and the communication circuit are respectively connected with the FPGA; wherein the content of the first and second substances,

the key is used for receiving an input signal of a user and sending the input signal to the FPGA so that the FPGA outputs a corresponding display signal to the display screen according to the input signal;

the display screen is used for receiving the display signal and displaying the display signal;

the indicator light is used for receiving the indication signal sent by the FPGA and indicating the electric energy pulse of the electric energy meter;

and the communication circuit is used for communicating with the FPGA, acquiring the power consumption data of the user and sending the power consumption data to the power system.

6. The system for electric energy meter management chip verification of claim 5, wherein the indicator light and the communication circuit are both connected to the FPGA through a resistor.

7. The system for electric energy meter management chip verification according to claim 6, wherein the FPGA comprises a configurable logic module and an input module, the configurable logic module is internally provided with the chip program to be verified, and is connected with the input module, and the FPGA interface comprises a function interface and an output interface; the configurable logic module is connected with the functional interface, and the input module is connected with the output interface.

8. The system for electric energy meter management chip authentication as recited in claim 7, wherein the FPGA further comprises a security module, the security module coupled to the configurable logic module, the security module having a security engine with a cryptographic algorithm built therein.

9. The system for electric energy meter management chip verification according to any one of claims 1 to 8, further comprising a power supply for supplying power to the FPGA, wherein an isolation device is arranged between the power supply and the FPGA.

10. An apparatus for verification of a power meter management chip, comprising a system for verification of a power meter management chip according to any one of claims 1 to 9.

Technical Field

The invention relates to the field of chip design verification, in particular to a system and a device for verifying an electric energy meter management chip.

Background

Common chips in the electric energy meter comprise a metering chip and a management chip, although foreign management chips are in the leading position in the electric energy meter all the time, with the change of international situation and the development of technology, more and more manufacturers have the capability of independent research and development, and try to use the independently researched and developed electric energy meter management chips to replace foreign imported chips, thereby breaking through the foreign monopoly situation. The electric energy meter management chip has a long research and development period and high research and development cost, and in order to reduce the times of chip generation, the chip needs to be verified repeatedly in the chip design process.

At present, in order to verify whether the electric energy meter management chip meets all requirements of an electric energy meter, an entity chip is generally required to be applied to a real electric energy meter for verification when the electric energy meter management chip is designed, the entity chip can only be redesigned when the chip does not meet the requirements, the entity chip cannot be continuously used for debugging and verification, and the design cost is increased.

Disclosure of Invention

The invention mainly aims to provide a system and a device for verifying an electric energy meter management chip, and aims to solve the technical problem that no special testing device is provided when the electric energy meter management chip is developed in the prior art.

In order to achieve the purpose, the invention provides a system for verifying an electric energy meter management chip, which comprises an FPGA (field programmable gate array) with a built-in chip program to be tested and an FPGA daughter board connected with the FPGA; wherein the content of the first and second substances,

the FPGA daughter board comprises a signal processing module, and the signal processing module is connected with the FPGA and used for acquiring a voltage signal and a current signal, converting the voltage signal and the current signal into digital signals and then sending the digital signals to the FPGA;

and the FPGA is used for verifying whether the function of the chip to be detected meets the design requirement according to the program of the chip to be detected and the digital signal.

Preferably, the signal processing module comprises a voltage and current sampling circuit, an analog-to-digital converter, a random access memory and a metering circuit; the voltage and current sampling circuit is respectively connected with the bus and the analog-to-digital converter, the analog-to-digital converter is connected with the random access memory, the random access memory is connected with the metering circuit, and the metering circuit is connected with the FPGA.

Preferably, the FPGA daughter board further comprises an FPGA interface, pins corresponding to functions of the chip to be tested are arranged on the FPGA interface, and the signal processing module is connected with the FPGA through the FPGA interface.

Preferably, the pin number of the FPGA interface is greater than the pin number of the chip to be inspected.

Preferably, the FPGA daughter board further comprises an electric energy meter external module, and the electric energy meter external module comprises a key, a display screen, an indicator light and a communication circuit; the key, the display screen, the indicator light and the communication circuit are respectively connected with the FPGA; wherein the content of the first and second substances,

the key is used for receiving an input signal of a user and sending the input signal to the FPGA so that the FPGA outputs a corresponding display signal to the display screen according to the input signal;

the display screen is used for receiving the display signal and displaying the display signal;

the indicator light is used for receiving the indication signal sent by the FPGA and indicating the electric energy pulse of the electric energy meter;

and the communication circuit is used for communicating with the FPGA, acquiring the electric quantity data of a user and sending the electric quantity to an electric power system.

Preferably, the indicator light and the communication circuit are both connected with the FPGA through a resistor.

Preferably, the FPGA includes a configurable logic module and an input module, the configurable logic module is internally provided with the chip program to be checked, the configurable logic module is connected with the input module, and the FPGA interface includes a functional interface and an output interface; the configurable logic module is connected with the functional interface, and the input module is connected with the output interface.

Preferably, the FPGA further includes a security module, the security module is connected to the configurable logic module, and a security engine having an encryption algorithm is built in the security module.

Preferably, the FPGA power supply device further comprises a power supply source for supplying power to the FPGA, and an isolation device is arranged between the power supply source and the FPGA.

The invention also provides a device for verifying the electric energy meter management chip, which comprises the system for verifying the electric energy meter management chip.

The system for verifying the electric energy meter management chip is provided with the FPGA internally provided with the chip program to be tested and the FPGA daughter board connected with the FPGA; the FPGA daughter board comprises a signal processing module connected with the FPGA, and is used for acquiring voltage signals and current signals, converting the voltage signals and the current signals into digital signals and then sending the digital signals to the FPGA; and the FPGA verifies whether the function of the chip to be detected meets the design requirement according to the program of the chip to be detected and the digital signal. The running program of the electric energy meter management chip is placed in the FPGA, and the FPGA daughter board is matched with the FPGA daughter board to simulate the normal running environment of the electric energy meter, so that the running program is subjected to simulation verification, the electric energy meter management chip can be repeatedly debugged in the process of designing the electric energy meter management chip, the technical problem that a special testing device is not used when the electric energy meter management chip is developed is solved, and the development cost is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an embodiment of a system for verifying a management chip of an electric energy meter according to the present invention;

fig. 2 is a schematic structural diagram of an embodiment of the FPGA interface in fig. 1.

The reference numbers illustrate:

reference numerals	Name (R)	Reference numerals	Name (R)
				10	FPGA	210	Signal processing module
20	FPGA daughter board	220	Electric energy meter peripheral module

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

The invention provides a system for verifying an electric energy meter management chip.

Referring to fig. 1, in an embodiment, the system for verifying the management chip of the electric energy meter includes an FPGA10 with a built-in chip program to be verified and an FPGA daughter board 20 connected to the FPGA 10; the FPGA daughter board 20 includes a signal processing module 210, and the signal processing module 210 is connected to the FPGA10, and is configured to collect a voltage signal and a current signal, convert the voltage signal and the current signal into digital signals, and send the digital signals to the FPGA 10; and the FPGA10 is used for verifying whether the function of the chip to be tested meets the design requirements according to the chip program to be tested and the digital signal.

It should be noted that the chip to be inspected refers to an electric energy meter management chip to be inspected, the chip program to be inspected refers to an operation program of the electric energy meter management chip to be inspected, an operation program of the electric energy meter management chip to be inspected is built in the FPGA (Field-Programmable Gate Array) 10, the FPGA daughter board 20 simulates other parts of the electric energy meter except the electric energy meter management chip, the FPGA daughter board and the FPGA daughter board can be used as a simulation electric energy meter in cooperation, the electric energy meter operation environment can be simulated through the FPGA daughter board 20 to obtain digital signals, the FPGA10 operates the program according to the digital signals to perform operations such as calculation, storage, display and the like, so as to verify whether each function of the electric energy meter management chip corresponding to the operation program meets design requirements.

Specifically, the signal processing module 210 includes a voltage-current sampling circuit (not shown), an analog-to-digital converter (not shown), a random access memory (not shown), and a metering circuit (not shown); the voltage and current sampling circuit is respectively connected with the bus and the analog-to-digital converter and used for sampling voltage and current, obtaining voltage signals and current signals and sending the voltage signals and the current signals to the analog-to-digital converter, the analog-to-digital converter is connected with the random access memory and used for converting the voltage signals and the current signals into initial digital signals and sending the initial digital signals to the random access memory for storage, the random access memory is connected with the metering circuit and sends the initial digital signals to the metering circuit, the metering circuit is connected with the FPGA10, the metering circuit carries out metering operation according to the initial digital signals, final digital signals are obtained, and the final digital signals are sent to the FPGA 10.

It should be understood that the above metering circuit may be a metering circuit integrated in a metering chip or a metering circuit not integrated, and the hardware form thereof is not limited in this embodiment.

In specific implementation, the FPGA daughter board 20 further includes an FPGA interface (not labeled), a pin corresponding to a function of the chip to be inspected is provided on the FPGA interface, and the signal processing module 210 is connected to the FPGA10 through the FPGA interface.

It should be understood that, the FPGA daughter board 20 should be designed according to the actual requirement of the electric energy meter, the reliability and function of the FPGA daughter board 20 are not lower than those of the existing products, in order to enable the FPGA10 to be connected with the FPGA daughter board 20 for verification of the electric energy meter management chip, an FPGA interface needs to be arranged on the FPGA daughter board 20 to implement communication with the FPGA10, a pin corresponding to the function of the electric energy meter management chip should be arranged on the FPGA interface, please refer to fig. 2 together, and fig. 2 is a schematic structural diagram of an embodiment of the FPGA interface. The pins on the FPGA interface can have the functions of external load switch control, metering chip serial port communication receiving, metering chip serial port communication sending, liquid crystal power supply control, relay detection input power supply control and the like.

Further, in order to make the verification system suitable for most types of electric energy meter management chips, the pin number of the FPGA interface may be greater than the pin number of the chip to be verified. For example, the actual power meter management chip is designed to have only about 80 pins, but 120 pins can be set when the FPGA interface is designed, and the pins which are not used can be left for standby.

Further, the FPGA daughter board 20 further includes an electric energy meter external module 220, where the electric energy meter external module 220 includes a key (not labeled), a display screen (not labeled), an indicator light (not labeled), and a communication circuit (not labeled); the key, the display screen, the indicator light and the communication circuit are respectively connected with the FPGA 10; the key is used for receiving an input signal of a user and sending the input signal to the FPGA10, so that the FPGA10 outputs a corresponding display signal to the display screen according to the input signal; the display screen is used for receiving the display signal and displaying the display signal; the indicator light is used for receiving the indication signal sent by the FPGA and indicating the electric energy pulse of the electric energy meter; and the communication circuit is used for performing data interaction with the FPGA10, reading the power consumption data of a user and sending the power consumption data to a power system.

The indicator light and the communication circuit are both connected to the FPGA10 through a resistor, or connected to the FPGA10 through a resistor, a capacitor, or the like. In order to meet the plugging and unplugging performance of the FPGA board, a design method for preventing the FPGA10 from being abnormal needs to be added, for example, a resistor is added to signals such as external switch control, leakage current detection, carrier communication, relay control, pulse output and the like for voltage division and interference resistance improvement.

It should be understood that the display screen is preferably a liquid crystal display screen, and can display data such as electric energy, a clock and the like; the communication circuit is preferably an RS485 communication circuit; besides, the electric energy meter external module can also comprise an EEPROM (Electrically Erasable Programmable read only memory), a FLASH (FLASH memory), a relay and the like, and the electric energy meter external module and the FPGA realize pulse output, relay output control and the like together.

In a specific implementation, the electric energy meter has 3 operation modes: work, low power consumption, ultra-low power consumption. The working mode refers to that the electric energy meter management chip operates at full speed only after the electric energy meter is under the normal metering condition, and the other two modes are that the electric energy meter is powered by a battery under the power failure condition, and the electric energy meter management chip only needs to operate partial functions. The electric energy meter needs to be awakened by a key under the condition of low power consumption; under the condition of ultra-low power consumption, only the data in the memory needs to be maintained without loss. Therefore, in this embodiment, a user can input a switching signal of the working mode of the electric energy meter through a key, and finally, the FPGA10 is enabled to switch the working mode of the electric energy meter.

Furthermore, the FPGA10 includes a configurable logic module (not shown) and an input module (not shown), the configurable logic module is embedded with the chip program to be checked, and is connected to the input module, the FPGA interface includes a functional interface (not shown) and an output interface (not shown); the configurable logic module is connected with the functional interface, and the input module is connected with the output interface.

It should be understood that the configurable logic module on the FPGA10 is connected to the functional interface on the FPGA daughter board 20, and the switching and functional implementation of the various modes of the FPGA daughter board 20 are realized through the configurable logic module. The input module on the FPGA10 is connected with each output interface on the FPGA daughter board 20 to form a loop, and the loop controls the output of the relay, the pulse output and the communication control.

Further, the FPGA10 further includes a security module (not shown) connected to the configurable logic module, and the security module has a security engine with an encryption algorithm built therein.

It should be understood that the encryption algorithm may be a national encryption algorithm or other algorithms, which is not limited in this embodiment, and in order to ensure the security of the electric energy meter management chip, a security engine integrated with the encryption algorithm is generally used, so that the chip has active immunity capability at the same time. In the embodiment, the encrypted electric energy meter management chip is simulated in the FPGA10 through the security module, so that the real application scene of the electric energy meter management chip is further restored, and the verification result is more accurate.

Further, the system for verifying the electric energy meter management chip further comprises a power supply (not shown) for supplying power to the FPGA10, and an isolation device is arranged between the power supply and the FPGA 10.

It should be understood that the power supply of the FPGA10 is an external power supply, so isolation needs to be considered on the power supply, interference from the external power supply is avoided, and an isolation device, such as an optical coupler, needs to be added on the circuit design.

The system design steps of the present embodiment are described below with reference to fig. 1 and 2:

step 1, firstly, designing according to final arrangement of electric energy meter management chips, representing all PINs used on the electric energy meter, combining functions of an FPGA10, and enabling the PINs on the electric energy meter management chips to correspond to FPGA interfaces, wherein the arrangement of the FPGA interfaces can be specifically shown in FIG. 2, and PINs of the FPGA interfaces are more than PINs on the electric energy meter management chips.

Step 2, the circuit designed on the FPGA daughter board 20 completely meets the requirements of all functions of the electric energy meter, wherein a voltage and current sampling circuit, an analog-to-digital converter, a random access memory and a metering circuit are designed in the signal processing module 210, the current and the current are sampled and finally converted into digital signals to be transmitted to the FPGA10, and the FPGA10 can perform operations such as calculation, storage, display and the like according to specific functional requirements; the electric energy meter external module 220 is provided with circuits such as keys, a display screen, an indicator light, keys, a communication circuit and the like, so that functions such as metering, displaying, storing, keying, communication and the like are realized.

And 3, the FPGA10 is respectively connected with a metering circuit, a key, a display screen, an indicator light, a key, a communication circuit and the like through an FPGA interface, and a resistor is added to signals such as external switch control, leakage current detection, carrier communication, relay control, pulse output and the like for voltage division and interference resistance improvement.

And 4, adding an isolating device between the power supply of the FPGA10 and the FPGA 10.

And 5, running a built-in chip program to be checked of the FPGA10 to verify the chip.

In the embodiment, the FPGA with the built-in chip program to be tested and the FPGA daughter board connected with the FPGA are arranged in the system for verifying the electric energy meter management chip; the FPGA daughter board comprises a signal processing module connected with the FPGA, and is used for acquiring voltage signals and current signals, converting the voltage signals and the current signals into digital signals and then sending the digital signals to the FPGA; and the FPGA verifies whether the function of the chip to be detected meets the design requirement according to the program of the chip to be detected and the digital signal. The running program of the electric energy meter management chip is placed in the FPGA, and the FPGA daughter board is matched with the FPGA daughter board to simulate the normal running environment of the electric energy meter, so that the running program is subjected to simulation verification, the electric energy meter management chip can be repeatedly debugged in the process of designing the electric energy meter management chip, the technical problem that a special testing device is not used when the electric energy meter management chip is developed is solved, and the development cost is reduced.

The invention also provides a device for verifying the electric energy meter management chip, wherein the device for verifying the electric energy meter management chip comprises the system for verifying the electric energy meter management chip, and the system structure of the device for verifying the electric energy meter management chip can refer to the embodiment and is not repeated herein; it can be understood that, since the device for verifying the management chip of the electric energy meter of the present embodiment adopts the technical solution of the system for verifying the management chip of the electric energy meter, the device for verifying the management chip of the electric energy meter has all the above beneficial effects.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.