阅读说明：本技术 高压太赫兹应变SiGe/InGaP异质结双极晶体管及其制备方法 (High-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor and preparation method thereof ) 是由 周春宇 李洪岩 耿欣 王冠宇 蒋巍 乔世峰 耿连民 于 2019-11-20 设计创作，主要内容包括：本发明提供一种高压太赫兹应变SiGe/InGaP异质结双极晶体管及其制备方法。InGaP材料具备InP材料高的载流子迁移率和GaP材料宽的禁带宽度特性,因此本发明利用InGaP作为集电区,可以同时提高器件的频率和功率特性,使得该器件可以实现太赫兹频段芯片的系统集成,进一步的本发明利用“能带工程”的优势,采用In<Sub>1-x</Sub>Ga<Sub>x</Sub>P(x＝0～1)作为SiGe-HBT的集电区材料,适当的选择In和Ga的组分摩尔比x,使得其和亚集电区材料SiGe具有相同的晶格常数,可以有效地提高InGaP和SiGe材料的界面特性。(The invention provides a high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor and a preparation method thereof. The InGaP material has the characteristics of high carrier mobility of the InP material and wide forbidden band width of the GaP material, so that the frequency and power characteristics of the device can be improved by using the InGaP as a collector region, the device can realize system integration of a terahertz frequency band chip, and further the invention utilizes the advantages of 'energy band engineering' and adopts In 1‑x Ga x P (x is 0-1) is used as a collector region material of the SiGe-HBT, and the composition molar ratio x of In and Ga is properly selected, so that the material has the same lattice constant with the sub-collector region material SiGe, and the interface characteristics of InGaP and the SiGe material can be effectively improved.)

1. A high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor is characterized in that the bipolar transistor selects an N-type doped single crystal Si substrate with a crystal orientation of (001); extending an N-type SiGe layer with gradually changed Ge components on the single crystal Si substrate to serve as a sub-collector region, and carrying out N + doping on the right side region of the SiGe layer; depositing a layer of SiO with the thickness of 1-2 microns on the surface of the SiGe layer₂A layer to define a location of an active region; sequentially extending an N-type InGaP layer serving as a collector region, a P-type SiGe layer serving as a base region and an intrinsic Si cap layer on the active region; depositing nitride, an oxide layer and a side wall oxide layer on the surface of the device, and depositing polycrystalline silicon on the side wall oxide layer to be used as an emitter; further selectively extending polycrystalline silicon to serve as an extrinsic base region; depositing a side wall oxide layer of the extrinsic base region; and respectively etching the emitter region, the extrinsic base region and the sub-collector region, and depositing metal silicide to form emitter, base and collector contacts.

2. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor of claim 1, wherein In is used_1-xGa_xP is used as a collector region material of the SiGe-HBT, and the component molar ratio x of In to Ga is selected, wherein x is more than or equal to 0 and less than or equal to 1, so that the collector region materialAnd the sub-collector material SiGe has the same lattice constant.

3. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor of claim 1, wherein a SiGe/Si structure heteroepitaxial InGaP material is used as the collector region.

4. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor of claim 1, wherein an N-type InGaP layer, a P-type SiGe layer and an intrinsic Si cap layer are sequentially epitaxially grown on the active region by an MBE method to serve as a collector region.

5. A preparation method of a high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor is characterized by comprising the following specific steps:

step 1, selecting monocrystalline silicon with the doping concentration of 10¹⁵cm^-3A starting material with a crystal orientation of (001) as a substrate;

step 2, depositing SiO 50 nm thick on N-doped single crystal Si substrate₂A layer;

step 3, adopting Mask1 to photo-etch the SiO₂Selectively extending an N-type SiGe layer with a gradually changed Ge component to serve as a sub-collector region of the heterojunction bipolar transistor, wherein the Ge component of the top layer of the N-type SiGe layer is 20%;

step 4, adopting Mask2 to perform ion implantation on the right side of the SiGe layer to form an N + region;

step 5, depositing SiO with the thickness of 1-2 microns on the upper surface of the device obtained in the step 4₂A layer;

step 6, etching and defining the position of the active region by adopting Mask3, and selectively extending the N-type InGaP layer, the P-type base region SiGe layer and the intrinsic Si cap layer which are used as the collector region in sequence;

step 7, depositing a nitride layer and an oxide layer on the surface of the device formed in the step 6 in sequence, and etching the nitride layer and the oxide layer by adopting Mask4 and Mask 5;

step 8, depositing an oxide layer on the surface of the device formed in the step 7, and etching the oxide layer by adopting Mask6 to form an EB side wall oxide layer;

step 9, selectively extending an N + polysilicon emitter region on the oxide layer, and forming an N + emitter region after CMP;

step 10, extending an oxide layer on the surface of the device obtained in the step 9 to be used as a surface covering layer of an emitting region;

step 11, etching the nitride layer in the step 7, and then etching the oxide layer in the step 8 by using Mask 7;

step 12, selectively depositing a P + polycrystalline silicon layer on the upper surface of the device obtained in the step 11, and etching the P + polycrystalline silicon layer by adopting Mask8 to form an extrinsic base region of the device;

step 13, depositing an oxide layer on the upper surface of the device obtained in the step 12, and etching the oxide layer by adopting Mask9 to form a side wall oxide layer;

step 14, etching the emitter region, the extrinsic base region and the sub-collector region, and depositing silicide to form a metal contact, thereby forming a collector contact, a base contact and an emitter contact.

6. The method for preparing a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 5, wherein in the step 6, selective epitaxy is performed in the active region by using an MBE method.

7. The method of claim 5, wherein In step 6, the molar ratio of In and Ga is selected so that the collector region material and the sub-collector region material, namely SiGe, have the same lattice constant.

8. The method for preparing a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 5, wherein in the step 6, a SiGe/Si structure heteroepitaxial InGaP material is used as a collector region.

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor and a preparation method thereof.

Background

As integrated circuits have been developed to the 10nm era, the feature size of devices has further decreased, and therefore, breakthrough must be made in the basic fields of device physics, materials, device structures, key processes, integration techniques, and the like. Meanwhile, silicon-based circuits enter the field of terahertz wave application, and the requirements on high performance and low power consumption of SiGe BiCMOS (silicon-germanium bipolar CMOS) are higher and higher.

A SiGe Heterojunction Bipolar Transistor (HBT) is a Si-based Bipolar Junction Transistor (BJT) with a small amount of Ge added to the base region. The base region is made of SiGe material, so that the device performance is remarkably improved, and the SiGe HBT becomes a standard bipolar transistor in high-speed application. Two key criteria for UHF semiconductor devices are the cut-off frequency (f)_T) And the highest oscillation frequency (f)_max). A Heterojunction Bipolar Transistor (HBT) developed on the basis of a mature silicon process and based on a germanium-silicon (SiGe) process utilizes the advantages of 'energy band engineering', and fundamentally solves the contradiction between the improvement of amplification factor and the improvement of frequency characteristic. Due to complete compatibility with mature silicon processes, and f_TAnd f_maxCan be close to or even comparable with the III-V group compound HBT, and the prior SiGeHBT is widely applied to high-performance microwave radio frequency devices and circuits with unique advantages.

However, in a SiGe Heterojunction Bipolar Transistor (HBT) operating in the forward active mode, the collector junction is under reverse bias, and in order to achieve optimum device performance, a large current must flow through the collector, which increases the collector junction electric field and reduces the carrier transit time at the junction. Because the carrier transmission time is determined by the saturation velocity of carriers in the material, the increase of the electric field can cause the avalanche breakdown effect caused by multiple impact ionization of the carriers in the collector region, and the avalanche multiplication factor is greatly dependent on the forbidden bandwidth of the material, so that the carrier transmission time is determined by the saturation velocity of the carriers in the materialImprove the cut-off frequency f of the device_TThe avalanche Breakdown Voltage (BV) of the common emitter collector junction_CEO) And thus limits the high speed/high power performance of the SiGe-HBT.

Disclosure of Invention

The invention aims to provide a device with frequency and power characteristics meeting system integration requirements of a terahertz frequency band chip and a preparation method thereof.

In order to solve the technical problem, firstly, the invention provides a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor. The bipolar transistor is an N-type doped single crystal Si substrate with the crystal orientation (001); extending an N-type SiGe layer with gradually changed Ge components on the single crystal Si substrate to serve as a sub-collector region, and carrying out N + doping on the right side region of the SiGe layer; depositing a layer of SiO with the thickness of 1-2 microns on the surface of the SiGe layer₂A layer to define a location of an active region; sequentially extending an N-type InGaP layer serving as a collector region, a P-type SiGe layer serving as a base region and an intrinsic Si cap layer on the active region; depositing nitride, an oxide layer and a side wall oxide layer on the surface of the device, and depositing polycrystalline silicon on the side wall oxide layer to be used as an emitter; further selectively extending polycrystalline silicon to serve as an extrinsic base region; depositing a side wall oxide layer of the extrinsic base region; and respectively etching the emitter region, the extrinsic base region and the sub-collector region, and depositing metal silicide to form emitter, base and collector contacts.

Further, In is adopted by utilizing the advantages of' energy band engineering_1-xGa_xP (x is 0-1) is used as a collector region material of the SiGe-HBT, and the composition molar ratio x of In and Ga is selected so that the collector region material and the sub-collector region material SiGe have the same lattice constant. Meanwhile, the InGaP material has the characteristics of high carrier mobility of the InP material and wide forbidden band width of the GaP material, and the frequency and power characteristics of the device can be improved at the same time.

Furthermore, a SiGe/Si structure heteroepitaxy InGaP material is adopted as a collector region, so that the frequency and power characteristics of the device can be improved simultaneously, and the device can realize system integration of the terahertz frequency band chip.

Furthermore, an N-type InGaP layer, a P-type SiGe layer and an intrinsic Si cap layer which are used as a collector region are sequentially extended in the active region by adopting an MBE method.

In addition, the invention also provides a preparation method of the high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor, which comprises the following specific steps of:

step 1, selecting monocrystalline silicon with the doping concentration of 10¹⁵cm^-3A starting material with a crystal orientation of (001) as a substrate;

step 2, depositing SiO 50 nm thick on the N-type doped single crystal Si substrate₂A layer;

step 3, adopting Mask1 to photo-etch the SiO₂Selectively extending an N-type SiGe layer with a gradually changed Ge component to serve as a sub-collector region of the heterojunction bipolar transistor, wherein the Ge component of the top layer of the N-type SiGe layer is 20%;

step 4, adopting Mask2 to perform ion implantation on the right side of the SiGe layer to form an N + region;

step 5, depositing SiO with the thickness of 1-2 microns on the upper surface of the device obtained in the step 4₂A layer;

step 6, etching and defining the position of the active region by adopting Mask3, and selectively extending the N-type InGaP layer, the P-type base region SiGe layer and the intrinsic Si cap layer which are used as the collector region in sequence;

step 7, depositing a nitride layer and an oxide layer on the surface of the device formed in the step 6 in sequence, and etching the nitride layer and the oxide layer by adopting Mask4 and Mask 5;

step 8, depositing an oxide layer on the surface of the device formed in the step 7, and etching the oxide layer by adopting Mask6 to form an EB side wall oxide layer;

step 9, selectively extending an N + polysilicon emitter region on the oxide layer, and forming an N + emitter region after CMP;

step 10, extending an oxide layer on the surface of the device obtained in the step 9 to be used as a surface covering layer of an emitting region;

step 11, etching the nitride layer in the step 7, and then etching the oxide layer in the step 8 by using Mask 7;

step 12, selectively depositing a P + polycrystalline silicon layer on the upper surface of the device obtained in the step 11, and etching the P + polycrystalline silicon layer by adopting Mask8 to form an extrinsic base region of the device;

step 13, depositing an oxide layer on the upper surface of the device obtained in the step 12, and etching the oxide layer by adopting Mask9 to form a side wall oxide layer;

step 14, etching the emitter region, the extrinsic base region and the sub-collector region, and depositing silicide to form a metal contact, thereby forming a collector contact, a base contact and an emitter contact.

Further, in step 6, selective epitaxy is performed in the active region by using an MBE method.

Further, In step 6, the composition molar ratio of In and Ga is properly selected so that the collector material and the sub-collector material SiGe have the same lattice constant.

Further, in step 6, a SiGe/Si structure heteroepitaxial InGaP material is used as the collector region.

Compared with the prior art, the invention has the following advantages:

the carrier mobility of the InP material is three times that of Si, so that the InP material is used as the collector region of the SiGe-HBT, the transmission time of a collector junction can be effectively reduced, and the frequency characteristic of a device is improved; meanwhile, the GaP material has the forbidden bandwidth twice that of Si, so that the GaP material is used as the collector region of the SiGe-HBT, the avalanche multiplication factor can be effectively reduced, and the breakdown voltage BV of the device is further improved_CEO。

The invention utilizes the characteristics of the materials, takes advantage of the energy band engineering and adopts In_1-xGa_xP (x is 0-1) is used as a collector region material of the SiGe-HBT, and the component molar ratio x of In to Ga is properly selected, so that the component molar ratio x and the sub-collector region material SiGe have the same lattice constant, and the interface characteristics of InGaP and a SiGe material can be effectively improved; therefore, the InGaP is used as a collector region, the frequency and power characteristics of the device can be improved at the same time, and the device can realize system integration of the terahertz frequency band chip.

Drawings

FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention;

FIG. 2 is a schematic view of an N-type doped single crystal Si substrate in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a device obtained through step 2 in the embodiment of the present invention;

FIG. 4 is a schematic diagram of a device obtained in step 3 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a device obtained in step 4 according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a device obtained in step 5 according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a device obtained in step 6 according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a device obtained through step 7 in an embodiment of the present invention;

FIG. 9 is a schematic diagram of a device obtained after steps 8 and 9 in the embodiment of the present invention;

FIG. 10 is a schematic diagram of a device obtained through step 10 in an embodiment of the present invention;

FIG. 11 is a schematic diagram of a device obtained in step 11 according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a device obtained through step 12 in an embodiment of the present invention; and

fig. 13 is a schematic diagram of a device obtained through step 13 in the embodiment of the present invention.

Reference numerals: 100-N type doped single crystal Si substrate, 101-SiO₂Layer, 102-SiGe subcollector region, 103-N + doped region, 104-thick SiO₂The structure comprises a layer, a 105-InGaP collector region, a 106-P type base region SiGe layer, a 107-Si cap layer, a 108-nitride layer, a 109-oxide layer, a 110-side wall oxide layer, a 111-N + emitter region, a 112-surface covering oxide layer, a 113-etched oxide layer, a 114-extrinsic base region, a 115-side wall oxide layer, a 116-emitter contact, a 117-base contact and a 118-collector contact.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As shown in FIG. 1, the present invention providesThe high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor selects an N-type doped single crystal Si substrate with a crystal orientation of (001); extending an N-type SiGe layer with a gradually changed Ge component on a substrate to serve as a sub-collector region, and carrying out N + doping on the right region; depositing a layer of thick SiO on the surface of the SiGe layer₂A layer to define a location of an active region; sequentially extending an N-type InGaP layer, a P-type SiGe layer and an intrinsic Si cap layer in an active region by adopting an MBE (molecular beam epitaxy) method; depositing nitride, an oxide layer and a side wall oxide layer on the surface of the device, and depositing polycrystalline silicon on the side wall oxide layer to be used as an emitter; etching nitride, and further selectively extending polycrystalline silicon to be used as an extrinsic base region; depositing a side wall oxide layer of the extrinsic base region; and finally, etching the emitter region, the extrinsic base region and the sub-collector region respectively to form emitter, base and collector contacts.

A preparation method of a high-voltage terahertz strain SiGe/InGaP heterojunction bipolar transistor comprises the following preparation steps:

step 1, an N-type doped single crystal Si substrate 100, as shown in fig. 2; the doping concentration of the monocrystalline silicon is selected to be 10¹⁵cm^-3A starting material with a crystal orientation of (001) as a substrate;

step 2, depositing a layer of SiO on the N-type doped single crystal Si substrate 100₂ Layer 101, as shown in FIG. 3;

step 3, adopting Mask1 to photo-etch SiO₂A layer 101, then a layer of N-type SiGe with a graded Ge composition is selectively epitaxial, as shown in fig. 4, the Ge composition of the top layer is 20%, and the layer serves as a SiGe subcollector region 102 of the heterojunction bipolar transistor;

step 4, adopting Mask2 to perform ion implantation on the right side of the SiGe layer to form an N + doped region 103, which is used to reduce the contact resistance of the collector, as shown in fig. 5;

step 5, depositing a layer of thick SiO₂Layer 104, as shown in FIG. 6;

step 6, adopting Mask3 to etch and define the position of the active region, then adopting MBE technology to selectively extend the N-type InGaP layer, the P-type base region SiGe layer 106 and the intrinsic Si cap layer 107 which are used as the InGaP collector region 105 in sequence, as shown in fig. 7;

step 7, depositing a nitride layer 108 and an oxide layer 109 on the surface of the device formed in the step 6 in sequence, and etching the nitride layer 108 and the oxide layer 109 by using a Mask4 and a Mask5, as shown in fig. 8;

step 8, depositing an oxide layer on the surface of the device formed in the step 7, and etching the oxide layer by using Mask6 to form an EB side wall oxide layer 110, as shown in FIG. 9;

step 9, selectively extending the N + polysilicon emitter region, and performing CMP to form an N + emitter region 111 shown in fig. 9;

step 10, extending an oxide layer outside the upper surface of the device obtained in step 9 as the surface of the emitter region to cover the oxide layer 112, as shown in fig. 10;

step 11, etching the nitride layer 108, and then etching the oxide layer 109 and the surface covering oxide layer 112 by using Mask7, wherein the etched structure is an etched oxide layer 113, as shown in fig. 11;

step 12, selectively depositing a P + polysilicon layer, and etching the P + polysilicon layer by using Mask8 to form an extrinsic base region 114 of the device, as shown in fig. 12;

step 13, depositing an oxide layer, and etching the oxide layer by using Mask9 to form a sidewall oxide layer 115, as shown in fig. 13;

step 14 etches the N + emitter region 111, extrinsic base regions and sub-collector regions and deposits silicide to form metal contacts, and thus a collector contact 118, a base contact 117 and an emitter-still contact 116, as shown in fig. 1.

The carrier mobility of the InP material is three times that of Si, so that the InP material is used as the collector region of the SiGe-HBT, the transmission time of a collector junction can be effectively reduced, and the frequency characteristic of a device is improved; meanwhile, the GaP material has the forbidden bandwidth twice that of Si, so that the GaP material is used as the collector region of the SiGe-HBT, the avalanche multiplication factor can be effectively reduced, and the breakdown voltage BV of the device is further improved_CEO。

The embodiment of the invention integrates the advantages of the materials, utilizes the advantages of energy band engineering and adopts In_1-xGa_xP (x is 0 to 1) is appropriately selected as a collector region material of the SiGe-HBTThe composition molar ratio x of In and Ga ensures that the composition molar ratio x and the material SiGe of the sub-collector region have the same lattice constant, and the interface characteristics of InGaP and the material SiGe can be effectively improved; meanwhile, the InGaP material has the characteristics of high carrier mobility of the InP material and wide forbidden band width of the GaP material; therefore, the InGaP is used as a collector region, the frequency and power characteristics of the device can be improved at the same time, and the device can realize system integration of the terahertz frequency band chip.

The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements made to the technical solution of the present invention by those skilled in the art without departing from the spirit of the present invention shall fall within the protection scope defined by the claims of the present invention.