阅读说明：本技术 一种上电长延时保护电路 (Go up long time delay protection circuit ) 是由 张涵 李翔宇 张晓伟 束俊鹏 解凯贺 于 2019-11-04 设计创作，主要内容包括：本发明公开了一种上电长延时保护电路,所述上电长延时保护电路包括基准电压产生电路、比较器、电阻R1、电阻R2、电阻R3、MOS管MN1/MN2/MP、电容C、基准电流源、电流镜、施密特触发器等模块。本发明在传统的上电长延时保护电路基础上增加了比较器、基准电压产生电路、迟滞电路、N型MOS管泄放回路,能够加快掉电检测的响应速度,同时消除噪声干扰的影响。本发明可任意控制电源上电过程中的延时保护等待时间,主要用在电源上电和正常工作时的任何异常掉电时的系统保护,特别是避免电源异常情况下的EEPROM的异常读写操作。(The invention discloses an upper long-time delay protection circuit which comprises a reference voltage generating circuit, a comparator, a resistor R1, a resistor R2, a resistor R3, a MOS (metal oxide semiconductor) tube MN1/MN2/MP, a capacitor C, a reference current source, a current mirror, a Schmitt trigger and other modules. The invention adds the comparator, the reference voltage generating circuit, the hysteresis circuit and the N-type MOS tube discharge circuit on the basis of the traditional upper long-time delay protection circuit, can accelerate the response speed of power failure detection, and simultaneously eliminates the influence of noise interference. The invention can arbitrarily control the time delay protection waiting time in the power supply electrifying process, is mainly used for system protection in any abnormal power failure during the electrifying and normal work of the power supply, and particularly avoids the abnormal read-write operation of the EEPROM under the abnormal condition of the power supply.)

1. A kind of upper long-time delay protective circuit, characterized by that the said upper long-time delay protective circuit includes the reference voltage generating circuit, comparator, resistance R1, resistance R2, resistance R3, MOS tube MN1/MN2/MP, electric capacity C, reference current source, current mirror, Schmidt trigger, wherein:

the reference voltage generating circuit is connected with a power supply VDD, and an output end Vr is connected with one input end Vip of the comparator;

the other input end Vin of the comparator is respectively connected with one end of a resistor R1 and one end of a resistor R2, and the output end of the comparator is connected with the grid electrode of an MOS transistor MN 1;

the other end of the resistor R1 is connected with a power supply VDD;

the other end of the resistor R2 is respectively connected with one end of a resistor R3 and the drain electrode of the MOS transistor MN 2;

the other end of the resistor R3 is grounded;

the source electrode of the MOS transistor MN1 is grounded, and the drain electrode is respectively connected with one end of the capacitor C, the drain electrode of the MOS transistor MP and the input end of the Schmitt trigger;

the other end of the capacitor C is grounded;

the source electrode of the MOS tube MP is connected with a power supply VDD, and the grid electrode of the MOS tube MP is connected with the output end of the current mirror;

the input end of the current mirror is connected with the output end of the reference current source;

the output end EN of the Schmitt trigger is connected with the grid electrode of the MOS tube MN 2.

2. The upper-length-delay protection circuit according to claim 1, wherein the reference voltage generation circuit is composed of a bandgap reference and a voltage divider circuit.

3. The upper-delay-and-delay protection circuit of claim 1, wherein the comparator is an open-loop operational amplifier or a dynamic latch comparator.

4. The upper-length-delay protection circuit according to claim 1, wherein the reference current source is a self-biased current source or a current generated by a bandgap reference.

5. The upper-length delay protection circuit of claim 1, wherein the schmitt trigger is composed of a MOS transistor.

Technical Field

The invention belongs to the technical field of integrated circuit design and manufacture, and relates to an upper long-time delay protection circuit.

Background

The power-on long-time delay protection circuit is generally applied to power-on sequence control among different module units in a complex circuit system, and particularly to read-write protection of important components such as an EEPROM (electrically erasable programmable read-only memory) in a key circuit. In a modern radar system, the power supply is various, and the power-on sequence and time between different power supplies are uncertain. If the power-on is not stable or the power failure occurs suddenly in the power-on process, the data in the key module is not read and written normally, which may cause the irrecoverable damage of hardware and threaten the reliability and safety of the whole system. The technology of the power-on long-delay protection circuit is developed, and the read-write operation can be permitted after the power supply is stably powered on and is delayed for a long time. The circuit system can also respond quickly when the power supply is suddenly powered down, and key modules in the circuit system are effectively protected.

The traditional power-on long-time delay protection circuit has a power-on protection threshold with larger error along with the change of the process and the environment, and is easy to be interfered by noise near the protection threshold.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides the upper long-time delay protection circuit which is simple in circuit structure and easy to realize.

The purpose of the invention is realized by the following technical scheme:

an upper-length delay protection circuit comprises a reference voltage generation circuit, a comparator, a resistor R1, a resistor R2, a resistor R3, a MOS transistor MN1/MN2/MP, a capacitor C, a reference current source, a current mirror and a Schmitt trigger, wherein:

the reference voltage generating circuit is connected with a power supply VDD, and an output end Vr is connected with one input end Vip of the comparator;

the other input end Vin of the comparator is respectively connected with one end of a resistor R1 and one end of a resistor R2, and the output end of the comparator is connected with the grid electrode of an MOS transistor MN 1;

the other end of the resistor R1 is connected with a power supply VDD;

the other end of the resistor R2 is respectively connected with one end of a resistor R3 and the drain electrode of the MOS transistor MN 2;

the other end of the resistor R3 is grounded;

the source electrode of the MOS transistor MN1 is grounded, and the drain electrode is respectively connected with one end of the capacitor C, the drain electrode of the MOS transistor MP and the input end of the Schmitt trigger;

the other end of the capacitor C is grounded;

the source electrode of the MOS tube MP is connected with a power supply VDD, and the grid electrode of the MOS tube MP is connected with the output end of the current mirror;

the input end of the current mirror is connected with the output end of the reference current source;

the output end EN of the Schmitt trigger is connected with the grid electrode of the MOS tube MN 2.

The working principle is as follows:

the reference voltage generating circuit and the comparator module start to work in the power-on process of the power supply, the output of the comparator is pulled high under the condition that the threshold voltage is not reached or the power failure occurs, the drain NMOS tube discharges all the time, and the Schmitt trigger maintains low level all the time. When the normal work is finished after power-on, the comparator is pulled down, the delay unit starts to work, the Schmitt trigger outputs high level after a long time, and the circuit plays a role in delay protection.

Compared with the prior art, the invention has the following advantages:

1. the invention adds the comparator, the reference voltage generating circuit, the hysteresis circuit and the N-type MOS tube discharge circuit on the basis of the traditional upper long-time delay protection circuit, can accelerate the response speed of power failure detection, and simultaneously eliminates the influence of noise interference.

2. The invention can arbitrarily control the time delay protection waiting time in the power supply electrifying process, is mainly used for system protection in any abnormal power failure during the electrifying and normal work of the power supply, and particularly avoids the abnormal read-write operation of the EEPROM under the abnormal condition of the power supply.

Drawings

Fig. 1 is a schematic block diagram of a power-on long-delay protection circuit of the present invention.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings, but not limited thereto, and any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the protection scope of the present invention.

The invention provides an upper long-time delay protection circuit, which comprises a reference voltage generation circuit, a comparator, a resistor R1, a resistor R2, a resistor R3, a MOS transistor MN1/MN2/MP, a capacitor C, a reference current source, a current mirror, a Schmitt trigger and other modules as shown in figure 1. Wherein:

the reference voltage generating circuit is connected with a power supply VDD, and an output end Vr is connected with one input end Vip of the comparator;

the other input end Vin of the comparator is respectively connected with one end of a resistor R1 and one end of a resistor R2, and the output end of the comparator is connected with the grid electrode of an MOS transistor MN 1;

the other end of the resistor R1 is connected with a power supply VDD;

the other end of the resistor R2 is respectively connected with one end of a resistor R3 and the drain electrode of the MOS transistor MN 2;

the other end of the resistor R3 is grounded;

the source electrode of the MOS transistor MN1 is grounded, and the drain electrode is respectively connected with one end of the capacitor C, the drain electrode of the MOS transistor MP and the input end of the Schmitt trigger;

the other end of the capacitor C is grounded;

the source electrode of the MOS tube MP is connected with a power supply VDD, and the grid electrode of the MOS tube MP is connected with the output end of the current mirror;

the input end of the current mirror is connected with the output end of the reference current source;

the output end EN of the Schmitt trigger is connected with the grid electrode of the MOS tube MN 2.

In the invention, the reference voltage generating circuit consists of a band gap reference and a voltage dividing circuit.

In the invention, the comparator is generally an open-loop operational amplifier or a dynamic latch comparator.

In the present invention, the reference current source is generally a current generated by a self-biased current source or a bandgap reference.

In the invention, the Schmitt trigger is generally composed of MOS tubes.

The working principle of the circuit is described below with reference to specific examples:

for example, in a radar system, the power supply voltage VDD is slowly powered up, the resistors R1, R2, and R3 divide the power supply voltage VDD, the comparator output is pulled high until the divided voltage Vin rises to the reference voltage Vr, the bleeder circuit MN1 is turned on, and the schmitt trigger input/output is pulled low. After the power-on is finished, the MOS tube MN1 is closed, the current mirror scales and copies the current of the reference current source, and the MOS tube MP charges the capacitor C. After the charging reaches a certain time, the voltage on the capacitor C reaches the overturning voltage of the Schmitt trigger, and the output EN is pulled high. When the power supply is suddenly powered off in normal work, the output of the comparator is pulled high to enable the MOS transistor MN1 to be conducted, and due to the fact that the size of the MOS transistor MN1 is large, the charge on the capacitor C is rapidly discharged, and the output EN of the Schmitt trigger is rapidly pulled low. The system performs read and write operations only when the output level EN of the Schmitt trigger is high, and stops operating when EN is low.

The threshold voltage of the power-on read-write operation is determined by the reference voltage Vr and the resistors R1 and R2 (the value of the resistor R3 is small and can be ignored). If Vr is 1.2V, the final voltage of the power supply VDD is 5V, and R1/R2 is designed to be m: n, then the threshold voltage of the power-on read-write operation is 1.2 x (m + n)/n. The comparator output is pulled high all the time when the power supply remains below the threshold voltage. After the power-on is completed, the capacitor C starts to be charged, and if the reference current is Ip, the scaling of the current mirror is n, and the flipping threshold voltage of the schmitt trigger is Vt, the waiting time t of the delay protection level EN is about n × C × Vt/Ip. The latency t can be significantly increased by increasing the scaling factor n, the charging capacitance C.

The invention can be applied to a typical radar power supply management unit, independent management is carried out by monitoring and controlling the voltage of different modules, and the system health management is facilitated.