Boost generation circuit and related circuit, chip and wearing equipment
阅读说明:本技术 升压产生电路以及相关电路、芯片以及穿戴设备 (Boost generation circuit and related circuit, chip and wearing equipment ) 是由 王文祺 于 2019-10-08 设计创作,主要内容包括:本申请公开了一种升压产生电路(10)以及相关电路、芯片以及穿戴设备。所述升压产生电路,具有输出端(OUT),所述输出端提供输出电压(V<Sub>OUT</Sub>)及负载电流(I<Sub>LOAD</Sub>)。所述升压产生电路包括:第一电荷泵(100),提供第一偏置电流(IB1);第二电荷泵(102),提供所述负载电流;输出电压锁定电路(110),从所述第一电荷泵抽取所述第一偏置电流至所述输出端,其中所述输出电压锁定电路藉由锁定所述第一偏置电流来锁定所述第一电荷泵的第一电荷泵电压(V<Sub>PUMP1</Sub>),并进一步基于被锁定的所述第一电荷泵电压来锁定所述输出电压;以及负载电流产生电路(120),基于所述第二电荷泵的第二电荷泵电压(V<Sub>PUMP2</Sub>)从所述第二电荷泵抽取所述负载电流至所述输出端。(The application discloses boost generation circuit (10) and relevant circuit, chip and wearing equipment. The boost generation circuit has an output terminal (OUT) providing an output voltage (V) OUT ) And load current (I) LOAD ). The boost generation circuit includes: a first charge pump (100) providing a first bias current (IB 1); a second charge pump (102) providing the load current; an output voltage locking circuit (110) that latches a first charge pump voltage (Vpump) of the first charge pump by latching the first bias current to the output terminal PUMP1 ) And further locking the output voltage based on the first charge pump voltage being locked; and a load current generating circuit (120) based on a second charge pump voltage (V) of the second charge pump PUMP2 ) Drawing the load current from the second charge pump to the output.)
1. A boost generation circuit having an output for providing an output voltage and a load current to a high voltage circuit external to the boost generation circuit, the boost generation circuit comprising:
a first charge pump for providing a first bias current;
a second charge pump to provide the load current;
an output voltage locking circuit coupled between the first charge pump and the output terminal of the boost generation circuit for pumping the first bias current from the first charge pump to the output terminal of the boost generation circuit, wherein the output voltage locking circuit locks a first charge pump voltage of the first charge pump by locking the first bias current and further locks the output voltage of the output terminal of the boost generation circuit based on the locked first charge pump voltage; and
a load current generating circuit coupled between the second charge pump and the output of the boost generating circuit for drawing the load current from the second charge pump to the output of the boost generating circuit based on a second charge pump voltage of the second charge pump.
2. The boost generation circuit of claim 1, wherein the output voltage locking circuit comprises:
a first current source is coupled to the first charge pump for drawing the first bias current of a fixed magnitude from the first charge pump.
3. The boost generation circuit of claim 2, wherein the output voltage locking circuit further comprises:
an input stage transistor coupled to the first current source, wherein a gate-source voltage of the input stage transistor is locked based on the first bias current of a fixed magnitude.
4. The boost generation circuit of claim 3, wherein the input stage transistor is coupled in series between the first current source and the output of the boost generation circuit, and a gate of the input stage transistor is coupled to the first charge pump.
5. The boost generation circuit of claim 4, wherein the output voltage of the output of the boost generation circuit is a voltage difference between the first charge pump voltage and the gate-source voltage of the input stage transistor.
6. The boost generation circuit of claim 1, wherein the load current generation circuit comprises:
and the output stage transistor is connected between the second charge pump and the output end of the boosting generation circuit in series.
7. The boost generation circuit of claim 6, wherein a gate voltage of the output stage transistor is locked based at least on the first bias current.
8. The boost generation circuit of claim 1, wherein the boost generation circuit further comprises:
the control circuit is coupled between the output voltage locking circuit and the load current generating circuit and used for controlling the load current generating circuit based on the output voltage so as to adjust the magnitude of the load current.
9. The boost generation circuit of claim 8, wherein the control circuit further comprises:
a second current source to draw a second bias current of a fixed magnitude from the first charge pump.
10. The boost generation circuit of claim 9, wherein the control circuit comprises:
a control transistor, wherein a gate-source voltage of the control transistor is locked based on the second bias current of a fixed magnitude.
11. The boost generation circuit of claim 10, wherein a gate of the control transistor is coupled to the output voltage locking circuit, and the control transistor is connected in series between the first charge pump and the load current generation circuit.
12. The boost generation circuit of claim 1, further comprising:
and the low-pass filter is coupled between the first charge pump and the output voltage locking circuit and is used for filtering the first charge pump voltage.
13. The boost generation circuit of claim 1, wherein the first bias current is less than the load current.
14. A circuit, characterized in that the circuit comprises:
the boost generation circuit of any one of claims 1-13; and
the high-voltage circuit.
15. The circuit of claim 14, wherein the high voltage circuit comprises a rail-to-rail input amplifier.
16. A chip, wherein the chip comprises:
a circuit as claimed in any one of claims 14 to 15.
17. A wearable device, characterized in that the wearable device comprises:
the chip of claim 16.
Technical Field
The present application relates to a power supply technology, and in particular, to a boost generation circuit, a related circuit, a chip, and a wearable device.
Background
With the development and progress of science and technology, mobile electronic devices such as mobile phones, digital cameras, tablet computers, notebook computers and the like have become indispensable tools in people's lives. These electronic devices are usually supplied with a supply voltage by a battery of the electronic device or an external power source of the electronic device. In some applications, the internal circuitry of the electronic device requires an operating voltage higher than the supply voltage. Therefore, the supply voltage needs to be boosted by a boosting circuit. The characteristics of the voltage output by the conventional boost circuit are not good, thereby affecting the performance of the internal circuit. In order to make the internal circuit perform its intended function, it is an important task to improve the characteristics of the voltage output from the boost circuit.
Disclosure of Invention
An objective of the present application is to disclose a power supply technology, and in particular, to a boost generation circuit, a related circuit, a chip and a wearable device, so as to solve the above problems.
An embodiment of the present application discloses a boost generation circuit. The boost generation circuit is provided with an output end which is used for providing output voltage and load current to a high-voltage circuit outside the boost generation circuit. The boost generation circuit includes: a first charge pump for providing a first bias current; a second charge pump to provide the load current; an output voltage locking circuit coupled between the first charge pump and the output terminal of the boost generation circuit for pumping the first bias current from the first charge pump to the output terminal of the boost generation circuit, wherein the output voltage locking circuit locks a first charge pump voltage of the first charge pump by locking the first bias current and further locks the output voltage of the output terminal of the boost generation circuit based on the locked first charge pump voltage; and a load current generating circuit coupled between the second charge pump and the output of the boost generating circuit for drawing the load current from the second charge pump to the output of the boost generating circuit based on a second charge pump voltage of the second charge pump.
An embodiment of the present application discloses a circuit. The circuit comprises: the aforementioned boost generation circuit; and the high voltage circuit.
An embodiment of the present application discloses a chip. The chip includes: the foregoing circuit.
An embodiment of the application discloses a wearable device. The wearing apparatus includes: the chip described above.
The boost generation circuit disclosed by the application comprises two charge pumps, a first charge pump and a second charge pump. The two charge pumps are respectively responsible for the output voltage and the load current. In short, the output voltage and the load current are not provided by the same charge pump, so the output voltage is not interfered by the load current, and the characteristics of the output voltage are better.
Drawings
Fig. 1 is a circuit diagram of a first embodiment of a boost generation circuit of the present application.
Fig. 2 is a circuit diagram of an embodiment of a charge pump of the present application.
Fig. 3 is a circuit diagram of a second embodiment of the boost generation circuit of the present application.
Fig. 4 is a circuit diagram of a third embodiment of the boost generation circuit of the present application.
Fig. 5 is a waveform diagram of the related voltages of the boost generation circuit of fig. 4.
Fig. 6 is a schematic diagram of an embodiment of a wearable device to which a chip including the boost generation circuit of the present application is applied.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "the same" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "the same" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are "the same" unless otherwise specifically indicated or indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
The magnitude of the output voltage of the charge pump and the magnitude of the ripple voltage of the output voltage are both influenced by the magnitude of the output current (i.e., the load current) of the charge pump. Generally, the load current causes the output voltage of the charge pump to become small and the ripple voltage of the output voltage to become large, especially when the load current is larger, the smaller the output voltage of the charge pump and the larger the ripple voltage of the output voltage. The boost generation circuit disclosed in the present application includes two charge pumps, which are respectively responsible for outputting voltage and load current. That is, the output voltage and the load current are not provided by the same charge pump, so the magnitude of the output voltage and the magnitude of the ripple voltage of the output voltage are not affected by the magnitude of the load current, and the details thereof are described below.
Fig. 1 is a circuit diagram of a first embodiment of a boost
The
The second charge pump 102 is coupled to the supply voltage VDD2And based on the supply voltage VDD2Providing a second charge pump voltage VPUMP2. In addition, the second charge pump 102 provides a load current ILOAD. In other words, the second charge pump voltage VPUMP2Is the output voltage of the second charge pump 102, and the load current ILOADIs the output current of the second charge pump 102. Load current ILOADIs much larger than the output current of the
The output
In the present disclosure, since the output current of the
In addition, the
A load
The load
Embodiments of the output
The output
VOUT=VG-VGS(1)
Wherein VGRepresenting the input stage transistor MINIs (i.e., the first charge pump voltage V)PUMP1) And V isGSRepresenting the input stage transistor MINThe gate-source voltage of. In short, the output voltage V of the output terminal OUT of the
The
In summary, the input stage transistor MINGate voltage V ofG(i.e., the first charge pump voltage VPUMP1) Has been locked by the first current source I1 of the output
The load
Output stage transistor MOUTIs locked based on the first bias current IB1 and the second bias
FIG. 2 is a circuit of an embodiment of the
When the
When operated, switch SW0And SW1On, the switch SW2And SW3And is not conductive. Capacitor CFCharging to a supply voltage VDD. In detail, the capacitor CFHaving an electrode VFDAnd VFU. Electrode VFDVoltage ratio electrode VFUIs small and the voltage difference is the supply voltage VDD. Then, switch SW0And SW1Non-conductive, switch SW2And SW3And conducting. Electrode VFDFrom a level of zero to a level of the supply voltage VDDAccording to this electrode VFUIs a supply voltage VDDSupply voltage V pulsed to twice the levelDD. Charge pump voltage V at
VPUMP=2×VDD(2)
in the comparative embodiment, the load current and the charge pump voltage V are provided by directly using the
wherein Fs represents a switch SW0、SW1、SW2And SW3The switching frequency of (c); and, IORepresenting the load current.
By comparing equations (2) and (3), it is clear that there is a load current IOIn the case of (2), the charge pump voltage V at the
Furthermore, the charge pump voltage V at the
wherein VrippleRepresenting the ripple voltage.
As can be seen from equation (4), when a load current I is presentOWill generate ripple voltage Vripple. Furthermore, by combining equations (3) and (4), the load current IOWill influence the charge pump voltage V simultaneouslyPUMPAnd ripple voltage Vripple. When the load current IOThe larger the charge pump voltage VPUMPSmaller and smaller ripple voltage VrippleThe larger it is, the more it represents the charge pump voltage V of the
Referring back to fig. 1, in the embodiment of fig. 1, the
Fig. 3 is a circuit diagram of a second embodiment of the boost generation circuit 40 of the present application. Referring to fig. 3, the boost generation circuit 40 is similar to the
Fig. 4 is a circuit diagram of a third embodiment of the boost
Transistors M1 and M2 form a current mirror to provide a bias current I3 in series with transistor M1BIASThe copying is performed so that the transistor M2 outputs the bias current IBIAS(i.e., the first bias current IB1 is the bias current IBIAS). Similarly, transistors M1 and M4 form a current mirror to provide a bias current I to a current source I3 in series with transistor M1BIASThe copying is performed so that the transistor M4 outputs the bias current IBIAS. In addition, transistors M3 and M5 form a current mirror to mirror the bias current I output by transistor M2BIASThe copying is performed so that the transistor M5 outputs the bias current IBIAS(i.e., the second bias current IB2 is the bias current IBIAS)。
Fig. 5 is a waveform diagram of the related voltages of the
In addition, after being filtered by the low pass filter 400, the filtered first charge pump voltage VRIs less than the first charge pump voltage VPUMP1So that the output voltage V isOUTIs less than the second charge pump voltage VPUMP2Wherein the second charge pump voltage VPUMP2Is the load current ILOADAnd the result is that.
In some embodiments, a circuit includes the
Fig. 6 is a schematic diagram of an embodiment of a wearable device 60 to which the chip 62 including the
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
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