阅读说明：本技术 形成半导体器件的方法 (Method of forming semiconductor device ) 是由 I·瑞姆 R·马杜罗维 于 2019-06-28 设计创作，主要内容包括：本发明题为“形成半导体器件的方法”。在一个实施方案中,形成半导体器件的方法可包括使晶体管的栅极导体延伸以覆盖其中形成了所述晶体管的阱区的边界。所述栅极导体可延伸以与形成在所述阱区外部的第二晶体管的栅极导体进行电接触。可施加接触导体以电接触和物理接触所述第一栅极导体和所述第二栅极导体并且还覆盖所述阱区的所述边界。(The invention provides a method for forming a semiconductor device. In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to cover a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a second transistor formed outside the well region. A contact conductor may be applied to electrically and physically contact the first and second gate conductors and also cover the boundary of the well region.)

1. A semiconductor device, comprising:

a semiconductor substrate having a first conductivity type;

a first doped region of a second conductivity type formed on a surface of the semiconductor substrate, the first doped region having a perimeter abutting the semiconductor substrate at a boundary of the first doped region;

a first transistor formed in the first doped region, the first transistor having a first doped polysilicon gate conductor extending to cover the boundary, the first doped polysilicon gate conductor having the first conductivity type;

a second transistor formed in the semiconductor substrate, the second transistor having a second doped polysilicon gate conductor extending to intersect the first doped polysilicon gate conductor, the second doped polysilicon gate conductor having the second conductivity type; and

a gate contact having a contact conductor formed on a first portion of the first doped polysilicon gate conductor and a first portion of the second doped polysilicon gate conductor and covering the boundary.

2. The semiconductor device of claim 1, wherein the first length of the contact conductor is greater than the first width of the contact conductor.

3. The semiconductor device of claim 2, wherein the first transistor comprises a source contact having a source contact conductor having a second width and a second length, wherein the first length is greater than the second length and is also greater than the second width.

4. The semiconductor device of claim 1, wherein said first doped polysilicon gate conductor and said second doped polysilicon gate conductor comprise substantially no silicide or salicide material.

5. The semiconductor device of claim 1, further comprising a third transistor formed in the first doped region, the third transistor having a third doped polysilicon gate conductor of the first conductivity type.

6. The semiconductor device of claim 5, further comprising a fourth transistor formed in the semiconductor substrate and outside the first doped region, the fourth transistor having a fourth doped polysilicon gate conductor of the second conductivity type extending to intersect the third doped polysilicon gate conductor.

7. A method of forming a semiconductor device, comprising:

forming a first doped region of a first conductivity type on a surface of a semiconductor substrate of a second conductivity type;

forming a first active region of a first transistor in the first doped region, the first active region having a first gate conductor overlying a first channel region of the first transistor;

forming a second active region of a second transistor in the semiconductor substrate and outside the first doped region, the second active region having a second gate conductor overlying a second channel region of the second transistor;

extending the first gate conductor and the second gate conductor, wherein one of the first gate conductor or the second gate conductor extends to cover an interface between the semiconductor substrate and a perimeter of the first doped region; and

forming a gate contact conductor on the first gate conductor, on the second gate conductor and overlying the interface between the semiconductor substrate and the perimeter of the first doped region.

8. The method of claim 7, wherein forming the gate contact conductor comprises: forming an insulator on a portion of the first gate conductor overlying the first channel region and on a portion of the second gate conductor overlying the second channel region;

forming an opening in the insulator, wherein the opening covers the interface; and

forming a metal conductor within the opening, wherein the metal conductor physically and electrically contacts both the first gate conductor and the second gate conductor.

9. The method of claim 7, further comprising: forming a third transistor in the first doped region, the third transistor having a source region in common with the first transistor; and forming a fourth transistor in the semiconductor substrate and outside the first doped region, wherein the fourth transistor has a source region in common with the second transistor.

10. The method of claim 7, further comprising: applying a voltage to the first gate conductor and to the second gate conductor, wherein the voltage is greater than a supply voltage applied to a source of the first transistor or a drain of the second transistor.

Background

The present invention relates generally to electronic devices and, more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices.

In the past, the semiconductor industry utilized various methods and structures to form Static Random Access Memory (SRAM). One common type of SRAM cell utilizes six interconnected transistors and is commonly referred to as a 6T SRAM cell. In some cases, the gate connection of one of the transistors of the 6T SRAM cell may be disconnected and the disconnection may not be detected during normal and initial testing of the memory including the defective cell. This type of defect is typically only detected after a long period of memory usage. Such defects often result in time consuming and expensive product returns and replacements.

Accordingly, it is desirable to have SRAM cells that minimize such defects.

Drawings

FIG. 1 schematically illustrates a portion of an embodiment of a 6T SRAM circuit according to the present invention;

FIG. 2 shows an enlarged plan view of a portion of an example of an embodiment of a semiconductor device including at least a portion of the circuit of FIG. 1 in accordance with the present invention;

FIG. 3 illustrates an enlarged cross-sectional view of a portion of the semiconductor device of FIG. 2 in accordance with the present invention;

FIG. 4 illustrates various other circuits that may utilize the structure of the devices of FIGS. 1-3 in accordance with the present invention; and is

Fig. 5 schematically shows an example of a portion of an embodiment of an electrical circuit according to the present invention that may be formed due to a missing portion of the insulator.

Elements in the figures are not necessarily to scale, some elements may be exaggerated for illustrative purposes and, unless otherwise specified, like reference numerals in different figures denote like elements. Moreover, descriptions and details of well-known steps and elements may be omitted for simplicity of the description. As used herein, current carrying element or current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, while a control element or control electrode means an element of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. In addition, one current carrying member may carry current through the device in one direction, such as carrying current into the device, while a second current carrying member may carry current through the device in the opposite direction, such as carrying current out of the device. Although the devices may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, one of ordinary skill in the art will appreciate that complementary devices according to the present invention are also possible. It is understood by those of ordinary skill in the art that conductivity type refers to the mechanism by which conduction occurs, such as through holes or electrons, and thus, conductivity type does not refer to the doping concentration but to the doping type, such as P-type or N-type. It will be understood by those skilled in the art that the terms "during … …", "at … … simultaneously", and "when … …" as used herein in relation to circuit operation do not mean exactly that an action is said to occur immediately after the action is initiated, but that there may be some minor but reasonable delay, such as various propagation delays, between the reactions initiated by the initial action. Additionally, the term "simultaneously at … …" means that some action occurs at least for a period of time during the duration of the trigger action. Use of the word "approximately" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent a value or position from being exactly the stated value or position. It is recognized in the art that deviations of up to at least ten percent (10%) (and up to twenty percent (20%) for some components including semiconductor dopant concentrations) are reasonable deviations from the ideal target exactly as described. When used with respect to signal states, the term "active" means an active state of a signal, and the term "inactive" means an inactive state of a signal. The actual voltage value or logic state of a signal (such as a "1" or "0") depends on whether positive or negative logic is used. Thus, if positive logic is used, high voltage or high logic may be in effect, and if negative logic is used, low voltage or low logic may be in effect; whereas a low voltage or low state may fail if positive logic is used, and a high voltage or high logic may fail if negative logic is used. In this context, a positive logic convention is used, but those skilled in the art will appreciate that a negative logic convention may also be used. The terms "first," "second," "third," and the like in the claims and/or in the detailed description, as used in portions of the names of elements, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order, spatial order, hierarchical order, or any other order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. Reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment, but in some instances may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art. For clarity of illustration, the doped regions of the device structure are shown as having substantially straight edges and precisely angled corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of the doped regions may not typically be straight lines and the corners may not be precisely angled.

In addition, this specification shows a honeycomb design (in which the body region is a plurality of honeycomb regions) instead of a cell design (in which the body region is composed of a single region formed in an elongated pattern, typically in a serpentine pattern). However, the present description is intended to apply to both honeycomb implementations and single substrate implementations.

The embodiments illustrated and described as appropriate below may lack any elements not specifically disclosed herein and/or may be practiced in the absence of any element not specifically disclosed herein.

Detailed Description

Fig. 1 schematically illustrates a portion of an embodiment of a 6T SRAM circuit 10 that facilitates reducing failures. For example, a fault caused by an open connection to the gate of one of the transistors of circuit 10. The circuit 10 includes storage nodes 21 and 23 for storing values assigned to the circuit 10. P-channel transistor 11 and N-channel transistor 12 each have a drain connected to node 21. P-channel transistor 13 and N-channel transistor 14 of circuit 10 each have a drain connected to node 23. N-channel access transistor 17 has a source connected to node 21, and N-channel access transistor 18 has a source connected to node 23. The drain of transistor 17 is connected to a Bit Line (BL) conductor 16 at node 15, and the drain of transistor 18 is connected to a Bit Line Bar (BLB) conductor 19 at node 20. Those skilled in the art will appreciate that to store a bit of information within circuit 10, Bit Line (BL) conductor 16 and Bit Line Bar (BLB) conductor 19 are driven to opposite states, and transistors 17 and 18 are enabled via Word Line (WL) conductor 25 such that nodes 21 and 23 are driven to opposite states. Transistors 17 and 18 are then disabled and the state stored on nodes 21 and 23 is maintained by the corresponding transistor pairs 11-12 and 13-14. To help maintain the memory state, the gate of transistor 11 is typically connected to the gate of transistor 12 and to node 23. In addition, the gate of transistor 13 is typically connected to the gate of transistor 14 and to node 21. Those skilled in the art will appreciate that the sources and drains of the transistors (including transistors 17 and 18) may be inverted depending on which receives the high and low voltages. Therefore, for clarity of explanation, the sources of transistors 17 and 18 are referred to herein as electrodes connected to respective nodes 21 and 23.

After information or data is stored in circuit 10, one of nodes 21 or 23 will be in a valid logic state and the other will be in a disabled logic state. For one of nodes 21 and 23, which has been written to a state represented by a higher voltage than the other of nodes 21 and 23, the corresponding one of transistors 11 or 13 maintains the higher voltage, while the opposite one of transistors 12 and 14 maintains the opposite one of nodes 21 and 23 at a lower voltage. For example, it may be assumed that node 21 is written to a state requiring a higher voltage, and thus transistor 11 maintains the voltage at node 21 after transistor 17 is disabled.

In previous SRAM cells, one possible method for reading the cell was to precharge the bit line conductors to a high level, then monitor the conductors and determine which conductor has dropped in voltage. In performing such a read operation, if the connection to the gate of the P-channel transistor is lost, the storage node to which a higher voltage has been written may be maintained at the higher voltage for a certain period of time even if the P-channel transistor gate is turned off. In most cases, such a condition results in the P-channel transistor being turned off. During testing of such a previous SRAM cell, the cell may not appear defective because the voltage stored at the storage node may take a longer period of time to decrease to a value less than the stored value. Therefore, during testing, it is difficult to detect such defects in the previous SRAM cells. Those skilled in the art will appreciate that if conductors 16 and 19 are precharged using a low voltage rather than a high voltage, such may occur with N-channel transistors.

However, the structure of circuit 10 reduces the likelihood of an open circuit of the gate of either of transistors 11 or 13, as will be seen further below.

Fig. 2 shows an enlarged plan view of a portion of an example of an embodiment of a semiconductor device 35. An example of at least a portion of an embodiment of circuit 10 is formed on device 35.

Fig. 3 shows an enlarged cross-sectional view of a portion of device 35 taken along cross-sectional line 3-3 shown in fig. 2. The description refers to fig. 1 to 3.

Embodiments of device 35 may be formed on a semiconductor substrate 100. The substrate 100 may have an implementation in which the substrate 100 is a silicon semiconductor substrate. The substrate 100 may have an implementation that may be formed as a P-type substrate. Another embodiment may include that the substrate 100 may be formed to include an underlying bulk silicon substrate having doped regions formed therein as the substrate 100. Doped regions of opposite conductivity type may be formed on substrate 100 to form well regions or doped regions 66. Region 66 may be used to form P- type transistors 11 and 13. In one embodiment, region 66 may be N-type. The periphery of region 66 abuts an adjacent portion of substrate 100 along a boundary 85 of region 66. For clarity of description and as used herein, boundary 85 is a portion of an edge of the periphery of region 66 that extends from a surface of substrate 100 into substrate 100 and abuts substrate 100 along a portion of region 66 underlying portions of transistors 11 and 13. Embodiments of the boundary 85 extend into the substrate 100 at an angle between substantially eighty degrees and substantially one hundred and ten degrees from the surface of the substrate 100.

Implementations of transistors 12, 14, and 17-18 may be formed in a portion of substrate 100 outside of region 66. In some embodiments, doped regions 39, 47, and 53 are formed in substrate 100 to form active regions for transistors 12 and 14. The active region may also include a channel region. Doped regions 39, 47, and 53 may have an embodiment that may have the same conductivity type as substrate 100, but a different doping concentration, such as, for example, a higher doping concentration. Region 39 may have an embodiment that forms the source of transistors 12 and 14. Regions 47 and 53 may have an embodiment that may be formed as the drains of respective transistors 12 and 14. Embodiments of regions 47 and 53 may also form the sources of respective transistors 17 and 18. Gate structures 43 and 52 may be formed overlying a portion of substrate 100 between respective regions 39 and 47, and between regions 39 and 53. The channel regions of transistors 12 and 14 may be partially formed from the portion of substrate 100. Those skilled in the art will appreciate that a small portion of doped regions 39, 47, and 53 may underlie the outside edges of the gate structure, as shown by the dashed portions of regions 39, 47, and 53. Contact via structures 40 may be formed in region 39. Structure 40 may be formed to be electrically connected to region 39 to provide an electrical connection to the sources of transistors 12 and 14.

Structure 40 is connected to terminal 28 by a conductor interconnect not shown in fig. 2. Contact via structures 46 and 55 may be formed in respective regions 47 and 53 to electrically connect thereto and provide electrical connection to the drains of respective transistors 12 and 14.

Doped regions 49 and 59 may also be formed in substrate 100 and outside of region 66 to serve as drain regions for respective transistors 17 and 18. Doped regions 49 may be formed adjacent to regions 47 but spaced apart a distance sufficient to form the channel region of transistor 17. Similarly, doped regions 59 may be formed adjacent to region 53, but spaced apart a distance sufficient to form a channel region of transistor 18. The gate structures of transistors 17-18 may be formed overlying a portion of substrate 100 between respective regions 47 and 49 and between regions 53 and 59. Gate structure 48 of transistor 17 may be formed to cover a portion of substrate 100 between regions 47 and 49 such that a portion of substrate 100 becomes the channel of transistor 17. Similarly, gate structure 58 of transistor 18 may be formed overlying a portion of substrate 100 between regions 53 and 59. Those skilled in the art will appreciate that a small portion of doped regions 47, 49, 53, and 59 may underlie the outside edges of structures 48 and 58, as shown by the dashed portions of regions 47, 49, 53, and 59. Gate structures 48 and 58 may be interconnected together. Structures 48 and 58 may also be electrically connected to Word Line (WL)25 by conductors not shown in fig. 2. Connector via structures 50 and 60 may be formed in respective regions 49 and 59 to facilitate forming electrical connections with the drains of respective transistors 17 and 18. Structures 50 and 60 may be electrically connected to respective BL and BLB by electrical conductors not shown in fig. 2.

Transistors 11 and 13 may have an implementation that may be formed in region 66. Doped regions 67-68 and 72 may be formed in region 66 having a conductivity type opposite that of region 66 to form the sources and drains of transistors 11 and 13. In an embodiment, doped regions 67 and 72 may be formed as P-type doped regions within region 66 to form the drains of respective transistors 13 and 11, and doped region 68 may be formed as P-type doped regions to form the sources of transistors 11 and 13. Embodiments of regions 67-68 and 72 may form a portion of the active regions of transistors 11 and 13. Since portions of region 68 may serve as sources for both transistors 11 and 13, region 68 forms a connection between the sources of transistors 11 and 13. Other embodiments of transistors 11 and 13 may have separate source regions. Embodiments of region 68 may be formed to extend to intersect contact via structure 90, which may be connected to terminal 27 by a conductor interconnect not shown in fig. 2-3. Structure 90 may include a source contact conductor within structure 90. Contact via structures 77 and 78 may be formed in respective regions 72 and 67 to electrically connect thereto and provide electrical connection to the drains of respective transistors 11 and 13. Structures 77 and 78 may also be electrically connected to respective nodes 21 and 23 and to the drains of respective transistors 12 and 14, such as, for example, to respective structures 46 and 55, by conductor interconnects not shown in fig. 2.

The gate structures of transistors 11 and 13 may be formed as part of footprint 66. Embodiments of a gate structure may be formed to cover a portion of region 66 that is positioned between regions 67-68 and between regions 68 and 72. Those skilled in the art will appreciate that a small portion of doped regions 67-68 and 72 may underlie the outside edges of the gate structure, as shown by the dashed portions of regions 67-68 and 72. Gate structure 69 of transistor 13 may be formed to cover a portion of region 66 between regions 67-68 such that a portion of region 68 becomes the drain of transistor 13 and a portion of region 67 becomes the source of transistor 13. Similarly, gate structure 71 of transistor 11 may be formed to cover a portion of region 66 between regions 68 and 72, such that a portion of region 68 becomes the drain of transistor 11 and a portion of region 72 becomes the source of transistor 11.

Gate structures 69 and 71 may be formed to extend to intersect with respective gate structures 52 and 43 to form an electrical connection between the gate conductors of gate structures 71 and 43 and to form an electrical connection between the gate conductors of gate structures 69 and 52. Formation of transistors 11-14 (and, in some embodiments, transistors 17-18) may include forming insulator 102 (fig. 3) to insulate semiconductor regions, such as, for example, active and inactive regions of transistors 11-14, from conductor and semiconductor material that may be formed to cover a surface of substrate 100. In some embodiments, insulator 102 may be referred to as a field oxide. Embodiments may include the insulator 102 being formed as a Shallow Trench Isolation (STI) formed by methods well known to those skilled in the art. In other embodiments, insulator 102 may be formed by other techniques, such as, for example, by LOCOS or other well-known methods. Insulator 102 may be formed of silicon dioxide or silicon nitride or silicon oxynitride or other well-known insulator materials. Gate structure 69 may include a gate insulator 103 (fig. 3) that covers the channel region of transistor 13 disposed between regions 67 and 68. The insulator 103 may be formed of silicon dioxide or silicon nitride or other well known insulator materials suitable for forming a gate insulator. Formation of structure 69 may also include forming gate conductor 104 to overlie the channel region. The conductor 104 may have an embodiment, which may be formed on the insulator 103. Those skilled in the art will appreciate that the material of conductor 104 may also extend as conductor 105 to cover the portion of insulator 102 adjacent the channel region. In some embodiments, these adjacent portions of insulator 102 may also be part of gate structure 69. Embodiments of conductors 104 and 105 are formed as P-type polysilicon. In a preferred embodiment, conductors 104 and 105 do not substantially include any silicide (silicide) or salicide (salicide) material and are substantially only doped polysilicon. Embodiments of conductor 105 (or alternatively conductor 104) extend laterally (e.g., substantially perpendicular to a current flow direction of transistor 13) toward gate structure 52. The channel region of transistor 13 may be formed in a portion of region 66 under conductor 104.

The gate structure 52 of transistor 14 may be formed to include a gate insulator 113 and a gate conductor 114. The channel region of transistor 14 may be formed in a portion of substrate 100 underlying conductor 114. Insulator 113 may be formed to cover the channel region of transistor 14 disposed between regions 39 and 53. The insulator 113 may be formed of the same material as the insulator 103. Embodiments of insulators 103 and 113 are about one to two orders of magnitude thinner than insulator 102. Some embodiments of insulators 103 and 113 may have a thickness of about ten to about thirty angstroms (10-30), and insulator 102 may have a thickness of about three thousand angstroms or more (3000). The gate conductor 114 of structure 52 may also be formed overlying the channel region. Embodiments of the conductor 114 may be formed on the insulator 113. It should be noted that only portions of the insulators 103 and 113 and conductors 104 and 114 are shown in fig. 3 due to the angle of cross-sectional line 3-3. Those skilled in the art will appreciate that the material of conductor 114 may extend as conductor 115 to also cover the portion of insulator 102 adjacent the channel region. In some embodiments, these adjacent portions of insulator 102 may also be part of structure 52. Embodiments of conductors 114 and 115 are formed as N-type polysilicon. In a preferred embodiment, conductors 114 and 115 do not include any silicide or salicide material and are substantially only doped polysilicon. Embodiments of the conductor 115 (or alternatively, the conductor 114) extend laterally toward the structure 69. The embodiments may extend laterally (such as, for example, substantially perpendicular to the direction of current flow of transistor 14). The conductor 115 (or alternatively, the conductor 114) can have an embodiment that extends over the insulator 102 to abut and form an electrical connection with the conductor 105 (or alternatively, the conductor 104). In an embodiment, the electrical connection may be a direct electrical connection. Conductor 115 (or alternatively conductor 105) may have an embodiment that may extend to substantially cover boundary 85. In another exemplary embodiment, conductor 115 (or alternatively, conductor 105) may extend through boundary 85 and abut and form an electrical connection with conductor 105 (or alternatively, conductor 104). In another exemplary embodiment, conductor 105 (or alternatively, conductor 104) may extend through boundary 85 and abut and form an electrical connection with conductor 115 (or alternatively, conductor 105). Another embodiment may include that conductor 105 (or alternatively conductor 104) may be formed to extend to cover but not extend past boundary 85, and conductor 115 (or alternatively conductor 114) may be formed to extend to cover but not extend past boundary 85 and abut and form an electrical connection between conductors 105 and 115 (or alternatively, between conductors 104 and 114). Those skilled in the art will appreciate that the method of forming transistors 11-14 may include forming conductors 104-105 and 114-115 by: forming a polysilicon layer over insulators 102, 103 and 113; patterning the polysilicon; the first portion of P-type is then doped to form conductor 104-105 and the second portion of N-type is doped to form conductor 114-115. Thus, the interface or connection between conductors 105 and 115 may be anywhere near the zone indicated by arrow 118. Those skilled in the art understand that a P-N junction is formed at the interface of conductors 105 and 115.

Embodiments of gate structures 52 and 69 may include contact via structure 65. Structure 65 may have embodiments that may be formed in both structures 52 and 69. For example, insulator 106 may be formed to cover region 66, as well as other portions of transistors 11-14. Embodiments of forming insulator 106 can include forming insulator 106 over portions of insulator 102, conductors 104-105, and conductors 114-115. An opening may be formed in insulator 106 such that the opening covers portions of conductors 105 and 115 and extends across boundary 85. A conductor material may be formed in the opening to form a gate contact conductor 110 within the opening to form an electrical connection to both conductors 105 and 115, and thus to conductors 104 and 114. Those skilled in the art will appreciate that the material of the conductor 110 may be a composite of conductor materials, such as, for example, a composite of titanium, nickel, and tungsten. The material of the conductor 110 may then be substantially planarized, such as by CMP or other planarization methods, to remove portions of the material extending above the surface of the insulator 106, such as the material shown by the dashed lines of the conductor 110. The conductor 110 and the resulting opening of the conductor 110 are formed to cover the boundary 85 and make direct physical contact and make electrical connection with the conductors 105 and 115, and thus with the conductors 104 and 114. The dimensions of structure 65 are greater than the dimensions of structures 77, 78, 46 and 55. For example, the length of conductor 110 in the direction between transistors 13 and 14 is greater than the width or length of any of structures 77, 78, 46, and 55. In an embodiment, the length of the conductor 110 is longer than the width of the conductor 110. In an embodiment, the length of conductor 110 at which it extends toward conductors 104 and 114 is about three to four (3-4) times the width of conductor 110, and is also about three to four (3-4) times the width or length of any of structures 40, 46, 55, 78, 77, or 90. The increased length of conductor 110 also helps to provide an electrical connection between conductors 104 and 114, which helps to reduce the likelihood of an open circuit to the gate of transistor 11, and a similar configuration of structure 74 and the conductors associated with the structure.

Those skilled in the art will appreciate that structures 43 and 71 and structure 74 may be formed similarly to corresponding structures 52 and 69 and structure 65.

It has been found that forming conductors 105 and 115 to extend between and electrically connect the two conductors helps to reduce the likelihood of an open circuit to the gate of transistor 11, and a similar configuration of structures 43 and 71 provides the same improvement in transistor 13. In addition, forming conductor 110 to cover boundary 85 and form an electrical connection to both conductors 105 and 115 provides additional electrical connection to the gate of transistor 13 and also helps to reduce the likelihood of opening the gate of transistor 13. Forming conductor 110 to contact conductors 105 and 115 at the interface of conductors 105 and 115 forms a short across the P-N junction that allows current to flow through conductors 105 and 115 in both directions. Similar configurations of structure 74 and its associated conductors provide the same improvements to transistor 11.

In the past, it was thought that extending the gate conductor to cover the boundary between the doped region and the substrate would result in the formation of additional P-N junctions, which could cause incorrect operation of the transistor.

However, structures such as, for example, forming conductor 110 on portions of conductors 105 and 115 overlying boundary 85 form a short across any such diode and provide proper operation of the transistor, which provides the unexpected result of providing proper operation even if the conductors are doped. Those skilled in the art will appreciate that even with a small amount of silicide included in conductors 105 and 115, conductor 110 still provides the advantages explained herein as long as conductor 110 is still in direct contact with the P-N junction formed by the material of conductors 105 and 115 at its interface.

Those skilled in the art will appreciate that the structure of transistors 13 and 14 and/or transistors 11 and 12 may be used in other devices besides SRAM cells. In addition, one skilled in the art will appreciate that the 6T SRAM cell can have other layout configurations as long as conductor 110 directly contacts conductors 105 and 115 and contacts the P-N junction formed at the interface of conductors 105 and 115. Embodiments may also include that the conductor 110 covers the boundary 85.

Fig. 4 shows various other circuits that may utilize the structure of transistors 13 and 14. Cross-coupled latch 130 utilizes inverters 131 and 132 and a cross-coupled configuration including output 133. Fig. 4 also shows transistors 136 and 137, which may have an embodiment that may be an alternative embodiment to transistors 13 and 14. Transistors 136 and 137 are either of inverters 131 or 132.

Nand gate 140 shown in fig. 4 also has an output structure that may utilize transistors 136 and 137 to form output 141. In an embodiment, transistors 136 and 137 serve as the output structure for gate 140, where output 133 of transistors 136 and 137 would be the same as output 141. In addition, a D flip-flop 145. The Q output is formed using transistors 136 and 137, where the output 133 of transistors 136, 137 would be the Q output of flip-flop 145.

Fig. 5 schematically illustrates an example of a portion of an embodiment of a circuit 150 that may be formed due to a missing portion of an insulator. Portions of some of the insulator may be removed during the process of fabricating device 35. For example, during a CMP operation, portions of the insulator 106 may be inadvertently removed, such that in some regions, the thickness of the insulator may be reduced. Such missing portions of the insulator may result in lower insulator quality, which may reduce the reliability of devices including such insulators. It has been found that an unexpected result of contact structures 65 and 74 is that the structures provide redundant electrical connections between the gate conductors of the transistors, which provides a mechanism for detecting insulator problems.

In some embodiments, the loss of insulator may result in a poor connection to the gate conductor of the transistor. Such poor connection may result in capacitive coupling with the gate conductor, such as shown, for example, by capacitors 151 and 152. However, due to the redundant connection to the gate formed by conductor 110, a voltage may still be applied to the gate of transistor 12 and bypass the capacitive coupling of capacitors 151 and 152. Thus, if a high voltage is applied to the gates of transistors 11 and 12, such as at node 23 for example, the high voltage causes breakdown of the insulator, which can be detected. In an embodiment, the voltage applied to the gates of transistors 11 and 12 is no less than the supply voltage applied to terminal 27. Thus, another advantage of contact structures 65 and 74 is that defects that may form in the insulator are easily detected.

From all of the foregoing, it will be appreciated by those skilled in the art that examples of one embodiment of a semiconductor device may include:

a semiconductor substrate (such as substrate 100) having a first conductivity type (such as, for example, P-type);

a first doped region (such as, for example, region 66) of a second conductivity type (such as, for example, N-type) formed on a surface of the semiconductor substrate, a perimeter of the first doped region abutting the semiconductor substrate at a boundary (85) of the first doped region;

a first transistor (such as, for example, transistor 13) formed in a first doped region, the first transistor having a first doped polysilicon gate conductor (such as, for example, conductor 104) extending to overlie a boundary (such as, for example, boundary 85), the first doped polysilicon gate conductor having a first conductivity type;

a second transistor (such as, for example, transistor 14) formed in the semiconductor substrate, the second transistor having a second doped polysilicon gate conductor (such as, for example, conductor 114) extending to intersect the first doped polysilicon gate conductor, the second doped polysilicon gate conductor having a second conductivity type; and

a gate contact having a contact conductor (such as, for example, conductor 110) formed on a first portion of the first doped polysilicon gate conductor and on a first portion of the second doped polysilicon gate conductor and overlying the boundary.

Another embodiment may include the contact conductor having a first length greater than a first width of the contact conductor.

In another embodiment, the first transistor may include a source contact having a source contact conductor (such as, for example, conductor 90) having a second width and a second length, wherein the first length is greater than the second length and also greater than the second width.

Another embodiment may further include an insulator that: covering a second portion of a first doped polysilicon gate conductor, the first doped polysilicon gate conductor covering a channel region of the first transistor; and covering a second portion of a second doped polysilicon gate conductor covering the channel region of the second transistor, the insulator having an opening covering the first portion of the first doped polysilicon gate conductor, covering the first portion of the second doped polysilicon gate conductor, and covering the boundary.

In an embodiment, the first doped polysilicon gate conductor and the second doped polysilicon gate conductor may extend to cover the insulator and intersect each other, thereby covering the insulator.