阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 松浦修武 岩崎太一 稻塚卓也 于 2019-03-04 设计创作，主要内容包括：实施方式涉及半导体装置及其制造方法。实施方式的半导体装置包含N型阱区、第一栅极电极、第一半导体、以及第一接触件。N型阱区包含两个P型杂质扩散区域。第一栅极电极(52)隔着栅极绝缘膜(50)设于两个P型杂质扩散区域间的N型阱区的上方。第一半导体是在P型杂质扩散区域上设为柱状的单晶的半导体。第一接触件设于第一半导体上,且包含含有P型杂质的多晶的第二半导体。(Embodiments relate to a semiconductor device and a method of manufacturing the same. The semiconductor device of an embodiment includes an N-well region, a first gate electrode, a first semiconductor, and a first contact. The N-type well region includes two P-type impurity diffusion regions. A first gate electrode (52) is provided above the N-type well region between the two P-type impurity diffusion regions with a gate insulating film (50) therebetween. The first semiconductor is a single crystal semiconductor having a columnar shape in the P-type impurity diffusion region. The first contact is provided on the first semiconductor and includes a polycrystalline second semiconductor containing P-type impurities.)

1. A semiconductor device includes:

the N-type well region comprises two P-type impurity diffusion regions;

a first gate electrode provided above the N-type well region between the two P-type impurity diffusion regions and facing the N-type well region with a gate insulating film interposed therebetween;

a monocrystalline first semiconductor disposed in a columnar shape on the P-type impurity diffusion region; and

and a first contact provided on the first semiconductor and including a polycrystalline second semiconductor containing a P-type impurity.

2. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

the first contact also includes a first electrical conductor,

the side surface of the first conductor and the bottom surface of the first conductor are covered with the second semiconductor,

the upper surface of the first conductor is flush with the upper surface of the second semiconductor.

3. The semiconductor device as set forth in claim 2,

the first electrical conductor is a metal.

4. The semiconductor device as set forth in claim 2,

further comprising a second contact on the first gate electrode,

the upper surface of the second contact, the upper surface of the first conductor, and the upper surface of the second semiconductor are flush.

5. The semiconductor device according to claim 4, wherein the first and second semiconductor layers are stacked,

the second contact member comprises a second electrical conductor,

the first electrical conductor and the second electrical conductor comprise the same conductive material.

6. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

the first contact also includes a first electrical conductor,

the first conductor is provided on the second semiconductor,

the side surface of the first conductor and the side surface of the second semiconductor are provided continuously.

7. The semiconductor device as set forth in claim 6,

the first electrical conductor is a metal.

8. The semiconductor device as set forth in claim 6,

further comprising a second contact on the first gate electrode,

the upper surface of the second contact is flush with the upper surface of the first conductor.

9. The semiconductor device as set forth in claim 8,

the second contact member comprises a second electrical conductor,

the first electrical conductor and the second electrical conductor comprise the same conductive material.

10. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

further comprising a second contact on the first gate electrode,

an upper surface of the second contact is flush with an upper surface of the second semiconductor.

11. The semiconductor device as set forth in claim 10,

the second semiconductor is provided in a columnar shape.

12. The semiconductor device as set forth in claim 10,

the second contact includes a metal.

13. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

the second semiconductor contains boron as the P-type impurity,

the boron concentration in the second semiconductor is 10¹⁹(atoms/cm³) The above.

14. The semiconductor device according to claim 1, wherein the first and second electrodes are formed on a substrate,

the second semiconductor further comprises carbon,

the second semiconductor has a carbon concentration of 10¹⁹(atoms/cm³) The above.

15. The semiconductor device according to claim 1, further comprising:

the P-type well region comprises two N-type impurity diffusion regions;

a second gate electrode provided above the P-type well region between the two N-type impurity diffusion regions, and facing the P-type well region with a gate insulating film interposed therebetween; and

and a third contact provided on the N-type impurity diffusion region, the third contact having no columnar single crystal semiconductor between the third contact and the N-type impurity diffusion region.

16. The semiconductor device according to claim 1, further comprising:

a stacked body provided on an upper layer of the upper surface of the second semiconductor, the stacked body including insulating layers and conductive layers which are alternately stacked; and

a plurality of columns which penetrate the laminated body,

the intersections of the pillars and the conductive layer function as memory cells, respectively.

17. A method for manufacturing a semiconductor device includes the steps of:

forming an N-type well region in a substrate;

forming a grid electrode above the N-type well region;

forming two P-type impurity diffusion regions so as to sandwich the gate electrode in a plan view;

forming a contact hole so as to expose a surface of the P-type impurity diffusion region;

forming a monocrystalline first semiconductor on the P-type impurity diffusion region exposed at the bottom of the contact hole; and

after the first semiconductor is formed, a polycrystalline second semiconductor doped with P-type impurities is formed on the side surface of the contact hole and the first semiconductor.

18. The method for manufacturing a semiconductor device according to claim 17,

in forming the second semiconductor, the second semiconductor is further doped with carbon.

19. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of:

forming a conductor in the contact hole after forming the second semiconductor; and

after the conductive body is formed, the second semiconductor formed outside the contact hole is removed.

20. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of:

removing a portion of the second semiconductor formed outside the contact hole and the second semiconductor formed at the side of the contact hole after forming the second semiconductor; and

after a portion of the second semiconductor is removed, a conductive body is formed in the contact hole.

Technical Field

Background

A NAND flash memory capable of storing data in a nonvolatile manner is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment.

Fig. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor device according to the first embodiment.

Fig. 3 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor device according to the first embodiment.

Fig. 4 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array provided in the semiconductor device according to the first embodiment.

Fig. 5 is a cross-sectional view showing an example of a cross-sectional structure of a memory pillar in the semiconductor device according to the first embodiment.

Fig. 6 is a cross-sectional view showing an example of a cross-sectional structure of an NMOS transistor provided under a memory cell array in the semiconductor device according to the first embodiment.

Fig. 7 is a cross-sectional view showing an example of a cross-sectional structure of a PMOS transistor provided below a memory cell array in the semiconductor device according to the first embodiment.

Fig. 8 is a flowchart showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 9 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 10 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 11 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 12 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 13 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 14 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

Fig. 15 is a cross-sectional view showing an example of a cross-sectional structure of a PMOS transistor provided below a memory cell array in the semiconductor device according to the second embodiment.

Fig. 16 is a flowchart showing an example of a manufacturing process of the semiconductor device according to the second embodiment.

Fig. 17 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the second embodiment.

Fig. 18 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the second embodiment.

Fig. 19 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the second embodiment.

Fig. 20 is a cross-sectional view of an NMOS transistor and a PMOS transistor showing an example of a manufacturing process of the semiconductor device according to the second embodiment.

Fig. 21 is a cross-sectional view showing an example of a cross-sectional structure of an NMOS transistor and a PMOS transistor provided below a memory cell array in a semiconductor device according to a modification of the second embodiment.

Embodiments relate to a semiconductor device and a method of manufacturing the same.