Fail-safe circuit, integrated circuit device, and method of controlling node of circuit
阅读说明:本技术 故障安全电路、集成电路器件及控制电路的节点的方法 (Fail-safe circuit, integrated circuit device, and method of controlling node of circuit ) 是由 唐振 马亚琪 潘磊 于 2018-09-10 设计创作,主要内容包括:本公开涉及故障安全电路、集成电路器件及控制电路的节点的方法。电路包括:参考节点,被配置为承载参考电压电平;第一节点,被配置为承载具有第一电压电平的信号和参考电压电平;第二节点,被配置为承载在通电模式中具有电源电压电平并且在断电模式中具有参考电压电平的电源电压;以及多个晶体管,串联耦合在第一节点和参考节点之间。该多个晶体管中的每个晶体管接收多个控制信号中的相应控制信号,并且每个控制信号在通电模式中具有基于电源电压的第一值并且在断电模式中具有基于信号的第二值。(The disclosure relates to a fail-safe circuit, an integrated circuit device and a method of controlling a node of a circuit. The circuit comprises: a reference node configured to carry a reference voltage level; a first node configured to carry a signal having a first voltage level and a reference voltage level; a second node configured to carry a supply voltage having a supply voltage level in a power-on mode and a reference voltage level in a power-off mode; and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a respective control signal of a plurality of control signals, and each control signal has a first value based on the supply voltage in the power-on mode and a second value based on the signal in the power-off mode.)
1. A fail safe circuit comprising:
a reference node configured to carry a reference voltage level;
a first node configured to carry a signal having a first voltage level and the reference voltage level;
a second node configured to carry a supply voltage having a supply voltage level in a power-on mode and the reference voltage level in a power-off mode; and
a plurality of transistors coupled in series between the first node and the reference node, each transistor of the plurality of transistors configured to receive a respective control signal of a plurality of control signals,
wherein each of the plurality of control signals has a first value based on the supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
2. The circuit of claim 1, wherein a control signal of the plurality of control signals has a third value based on the signal in the power-on mode.
3. The circuit of claim 1, further comprising:
a voltage regulator coupled between the first node and the reference node, the voltage regulator configured to output a gate signal based on the signal; and
a gate control circuit configured to output the plurality of control signals further based on the gate signal.
4. The circuit of claim 3, wherein the voltage regulator is configured to output a gate signal having a value substantially equal to half of the first voltage level.
5. The circuit of claim 3, wherein,
the voltage regulator is configured to output the gate signal as one of a plurality of gate signals having the number of gate signals, and
the plurality of gate signals have a plurality of values substantially equal to a multiple of the first voltage level divided by the number of gate signals plus 1.
6. The circuit of claim 3, wherein the voltage regulator comprises a source follower.
7. The circuit of claim 3, wherein the gate control circuit is configured to output each of the plurality of control signals having the supply voltage level as the first value.
8. The circuit of claim 3, wherein,
the plurality of transistors includes a first transistor and a second transistor, the first transistor being coupled between the first node and the second transistor, and
the gate control circuit is configured to output the signal or the power supply voltage level as a first control signal of a plurality of control signals to a first transistor of the plurality of transistors.
9. An Integrated Circuit (IC) device comprising:
an input pad configured to receive an input signal;
a conductor configured to carry a supply voltage;
a gate control circuit configured to generate a first control signal and a second control signal, each of the first control signal and the second control signal based on the supply voltage in a power-on mode and based on the input signal in a power-off mode;
a first transistor coupled with the input pad, the first transistor including a gate configured to receive the first control signal; and
a second transistor coupled in series with the first transistor, the second transistor including a gate configured to receive the second control signal.
10. A method of controlling a node of a circuit, the method comprising:
receiving a signal at the node;
in response to a power supply of the circuit having a supply voltage level, using the supply voltage to control coupling the node to a pull-down driver; and is
The signal is used to control coupling the node to the pull-down driver in response to a power supply of the circuit having a reference voltage level.
Technical Field
The disclosure relates to a fail-safe circuit, an integrated circuit device and a method of controlling a node of a circuit.
Background
Communication between electronic circuits involves various scenarios that must be considered when designing the circuits. In some cases, circuits that rely on one power source must be designed to interface with signals based on another power source. The two power supplies may not have the same voltage level and one of the two power supplies may be powered on while the other is powered off.
Disclosure of Invention
An embodiment of the present disclosure provides a fail-safe circuit, including: a reference node configured to carry a reference voltage level; a first node configured to carry a signal having a first voltage level and the reference voltage level; a second node configured to carry a supply voltage having a supply voltage level in a power-on mode and the reference voltage level in a power-off mode; and a plurality of transistors coupled in series between the first node and the reference node, each transistor of the plurality of transistors configured to receive a respective control signal of a plurality of control signals, wherein each control signal of the plurality of control signals has a first value based on the supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
Embodiments of the present disclosure also provide an Integrated Circuit (IC) device, including: an input pad configured to receive an input signal; a conductor configured to carry a supply voltage; a gate control circuit configured to generate a first control signal and a second control signal, each of the first control signal and the second control signal based on the supply voltage in a power-on mode and based on the input signal in a power-off mode; a first transistor coupled with the input pad, the first transistor including a gate configured to receive the first control signal; and a second transistor coupled in series with the first transistor, the second transistor including a gate configured to receive the second control signal.
Embodiments of the present disclosure also provide a method of controlling a node of a circuit, the method including: receiving a signal at the node; in response to a power supply of the circuit having a supply voltage level, using the supply voltage to control coupling the node to a pull-down driver; and using the signal to control coupling the node to the pull-down driver in response to a power supply of the circuit having a reference voltage level.
Drawings
Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a diagram of a circuit according to some embodiments.
Fig. 2A is an illustration of a pull-down circuit according to some embodiments.
Fig. 2B is a depiction of a top view of an IC layout of a pull-down circuit in accordance with some embodiments.
Fig. 3A is an illustration of a voltage regulator according to some embodiments.
Fig. 3B is a depiction of a top view of an IC layout of a voltage regulator in accordance with some embodiments.
Fig. 4A is a diagram of a gate control circuit according to some embodiments.
Fig. 4B is a depiction of a top view of an IC layout of a gate control circuit in accordance with some embodiments.
Fig. 4C is a diagram of a gate control circuit according to some embodiments.
Fig. 4D is a depiction of a top view of an IC layout of a gate control circuit in accordance with some embodiments.
Fig. 5 is a flow diagram of a method of controlling a node of a circuit according to some embodiments.
Fig. 6 is a depiction of an IC manufacturing system and IC manufacturing flow associated therewith, in accordance with some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In various embodiments, the circuit includes a series of switching devices coupled between a node and a reference node and responsive to a plurality of control signals. The signal on the node is divided (divide) to generate one or more gate voltages that are received by the gate control circuit. The gate control circuit also receives the signal and the supply voltage of the circuit. In the power-on mode, the gate control circuit outputs each control signal having at least one value based on the power supply voltage. In the power down mode, the gate control circuit outputs each control signal having at least one signal-based value.
Thus, in applications where the signal has a voltage level greater than or equal to the power supply voltage level, the circuit is able to transmit the signal in the power-on mode and prevent leakage current from flowing in the power-off mode. The circuit is also capable of transmitting a signal and preventing leakage using a switching device having a maximum operating voltage less than a voltage level of the signal by limiting a voltage across the switching device to a magnitude equal to or lower than the maximum operating voltage of the switching device.
Fig. 1 is a diagram of a
Two or more circuit elements are considered to be electrically coupled based on a direct electrical connection, a resistive or reactive electrical connection, or an electrical connection that includes one or more additional circuit elements, and thus can be controlled, e.g., made resistive or open, by a transistor or other switching device.
In the embodiment depicted in fig. 1, each of the pull-
Node VDDIO1 is a circuit node configured to carry a supply voltage having a supply voltage level VDDIO. In some embodiments, supply voltage level VDDIO is the supply voltage level of an IC chip that includes
Reference node VSSN is a circuit node configured to carry a reference voltage having a reference voltage level VSS. In some embodiments, the reference voltage level VSS is a ground voltage level.
Node VDDIO1 has a supply voltage level VDDIO when
In various embodiments, the
In various embodiments, the power supply is configured to transfer power to node VDDIO1 directly or through one or more intermediate circuits (e.g., control or boost or buck circuits) configured to output a supply voltage level VDDIO and/or a reference voltage level VSS.
In addition to
In some embodiments,
In some embodiments, the IIC BUS includes a node BUS configured to carry a BUS voltage having a BUS voltage level VBUS, and a node PAD configured to carry a signal VPAD having the BUS voltage level VBUS or a reference voltage level VSS. In various embodiments, node PAD is configured to carry signal VPAD having a voltage level less than, substantially equal to, or greater than power supply voltage level VDDIO.
In the embodiment depicted in fig. 1, the pull-
The pull-
In some embodiments, instead of including N gate signals VPADX1-VPADXN,
To control the node PAD, the pull-
In various embodiments, the
The
In the power-on mode, each of the control signals VTRACK and VMID or VMID1-VMIDN has at least one value based on the power supply voltage on node VDDIO1, as discussed below with respect to
In the power down mode, each of the control signals VTRACK and VMID or VMID1-VMIDN has at least one value based on the signal VPAD, as discussed below with respect to the
The signal NGATE received by the pull-down
The pull-down
In a power-on mode, the pull-
In the power down mode, the pull-
With the configuration discussed above, in applications where the bus voltage level VBUS is less than, greater than, or substantially equal to the power supply level VDDIO, the pull-
In various embodiments,
The
In the embodiment depicted in FIG. 1,
The
The
In the power-on mode, each
In the power down mode, each
In power on mode,
In the power-off mode, the
With the configuration discussed above, the
With the configuration discussed above, in applications where the bus voltage level VBUS is less than, greater than, or substantially equal to the power supply level VDDIO, the
By limiting the voltage across the
By using switching devices having a maximum operating voltage less than the bus voltage level, a circuit (e.g., an IC) including
Fig. 2A is an illustration of a pull-
The pull-
In the embodiment depicted in fig. 2A, the pull-
In various embodiments, the pull-
Fig. 2B is a depiction of a top view of an IC layout of the
The IC layout diagram of the
The transistor N21 includes a conductive region M1 configured to couple the signal VPAD with the corresponding active region AR and a gate region PO configured to receive a control signal VTRACK; transistor N22 includes a gate region PO configured to receive a control signal VMID or VMID 1; transistor N23 includes a gate region PO configured to receive control signal VMIDN; and transistor N24 includes a gate region PO configured to receive signal NGATE and a conductive region M1 configured to couple a reference voltage level VSS with a corresponding active region AR.
The conductive region M1 is configured to electrically connect the active region AR of the transistor N21 to the active region AR of the transistor N22; the conductive region M1 is configured to electrically connect the active region AR of the transistor N22 to the active region AR of the transistor N23; and the conductive region M1 is configured to electrically connect the active region AR of the transistor N23 to the active region AR of the transistor N23.
In some embodiments, the IC layout of the pull-
With the configuration and layout discussed above, the pull-
Fig. 3A is an illustration of a
With the configuration depicted in FIG. 3A, resistors R31, R32, and R33, in operation, divide the signal VPAD on node PAD, generating a voltage level VPADR1-VPADRN or VPADR, as discussed above with reference to FIG. 1.
The transistors N32 and N33 are configured as source followers that, in operation, receive the voltage levels VPADR1 and VPADR2 at respective gates and output the voltage levels at respective source terminals as respective gate signals VPADX1 and VPADXN. Transistor N31 is configured as a diode having a gate electrically connected to the drain terminal. In operation, transistor N31 and resistor R34 regulate the current through transistors N32 and N33.
In the embodiment depicted in fig. 3,
In some embodiments, the
Fig. 3B is a depiction of a top view of an IC layout of a portion of
The IC layout of the portion of
Transistor N31 includes a conductive region M1 configured to couple signal VPAD with a respective active region AR, and a gate region PO; transistor N32 includes a gate region PO configured to receive a voltage level VPADR or VPADR 1; transistor N33 includes a gate region PO configured to receive a voltage level VPADRN; and resistor R34 includes a resistance region RH.
The conductive region M1 is configured to electrically connect the active region AR of the transistor N32 to the active region AR of the transistor N33, and output the gate signal VPADX or VPADX 1; the conductive region M1 is configured to electrically connect the active region AR of the transistor N33 to the resistance region RH and output the gate signal VPADXN; and the conductive region M1 is configured to couple the reference voltage level VSS with the resistive region RH.
In some embodiments, the IC layout of the portion of the
With the configuration and layout discussed above, the
Fig. 4A is an illustration of a
The
The source terminals of the transistors P4a1 and N4a1 are electrically connected to each other and to the gate of the transistor P4a2, and the source terminal of the transistor P4a2 is configured to receive the supply voltage on the node VDDIO 1.
The gate of transistor P4A3 is configured to receive the supply voltage on node VDDIO1, and the source terminal of transistor P4A3 is configured to receive the same one of signals VPADX1-VPADXN or VPADX received at the source terminal of transistor P4a 1.
The drain terminals of the transistors P4a2 and P4A3 are electrically connected to each other and are configured to output one of the control signals VMID1-VMIDX or VMID corresponding to one of the signals VPADX1-VPADXN or VPADX received at the source terminals of the transistors P4a1 and P4 A3.
With the configuration discussed above, the
Fig. 4B is a depiction of a top view of an IC layout of
The IC layout diagram of the
Transistor P4a1 includes a conductive region M1 configured to couple a signal (e.g., signal VPADX) with a respective active region AR and a gate region PO configured to receive a supply voltage on node VDDIO 1; transistor N4a1 includes a gate region PO configured to receive a supply voltage on node VDDIO1 and a conductive region M1 configured to receive a reference voltage VSS; transistor P4a2 includes a conductive region M1 configured to receive the supply voltage on node VDDIO 1; and transistor P4a3 includes a gate region PO configured to receive the supply voltage on node VDDIO1 and a conductive region M1 configured to couple signals with a respective active region AR.
The conductive region M1 is configured to electrically connect the gate region PO of the transistor P4a1 to the gate region PO of the transistor N4a 1; the conductive region M1 is configured to electrically connect the active regions AR of the transistors P4a1 and N4a1 to the gate region PO of the transistor P4a 2; and the conductive region M1 is configured to electrically connect the active regions AR of the transistors P4a2 and P4A3 to each other and output a control signal, for example, a control signal VMID.
In some embodiments, the IC layout of the
With the configuration and layout discussed above, the
Fig. 4C is an illustration of a
The
The drain terminals of transistors P4C1 and P4C2 are electrically connected to each other and are configured to output a control signal VTRACK.
With the configuration discussed above,
Fig. 4D is a depiction of a top view of an IC layout of a
The IC layout diagram of the
The transistor P4C1 includes a conductive region M1 configured to couple the signal VPAD with the corresponding active region AR and a gate region PO configured to receive the control signal VMID1 or VMID; and transistor P4C2 includes a gate region PO configured to receive signal VPAD.
The conductive region M1 is configured to electrically connect the gate region PO of the transistor P4C1 to the active region AR of the transistor P4C2 and receive the control signal VMID1 or VMID; and the conductive region M1 is configured to electrically connect the active regions AR of the transistors P4C1 and P4C2 to each other and output a control signal VTRACK.
In some embodiments, the IC layout of the
With the configuration and layout discussed above, the
FIG. 5 is a flow diagram of a
The order in which the operations of
At
In some embodiments, receiving the signal includes receiving signal VPAD at node PAD of
Receiving the signal includes receiving a signal having a logic high voltage level or a logic low voltage level. In various embodiments, the logic high voltage level is less than, substantially equal to, or greater than a supply voltage level of a supply voltage used to power the circuit, and receiving the signal includes receiving a signal having a voltage level less than, substantially equal to, or greater than the supply voltage level.
At
In some embodiments, using the supply voltage to control coupling the node to the pull-down driver includes controlling the plurality of transistors with a plurality of control signals. In some embodiments, controlling the plurality of transistors with the plurality of control signals includes generating the plurality of control signals based at least in part on a supply voltage.
In some embodiments, controlling the plurality of transistors with the plurality of control signals based at least in part on the supply voltage includes controlling the pull-
In some embodiments, controlling the plurality of transistors with the plurality of control signals based at least in part on the supply voltage includes controlling a voltage across each transistor of the plurality of transistors to be less than or substantially equal to a maximum operating voltage of the plurality of transistors.
At
In some embodiments, using the signal to control coupling the node to the pull-down driver includes controlling a plurality of transistors with a plurality of control signals. In some embodiments, controlling the plurality of transistors with the plurality of control signals includes generating the plurality of control signals based at least in part on the signals.
In some embodiments, controlling the plurality of transistors with the plurality of control signals based at least in part on the signals includes controlling the pull-
In some embodiments, controlling the plurality of transistors with the plurality of control signals based at least in part on the signal includes controlling a voltage across each transistor of the plurality of transistors to be less than or substantially equal to a maximum operating voltage of the plurality of transistors.
By performing the operations of
Fig. 6 is a block diagram of an Integrated Circuit (IC)
In fig. 6,
A design room (or design team) 620 generates an
In some embodiments,
In some embodiments,
In some embodiments,
It should be appreciated that the above description of
After
The
The
Details regarding Integrated Circuit (IC) manufacturing systems (e.g.,
In some embodiments, the circuit comprises: a reference node configured to carry a reference voltage level; a first node configured to carry a signal having a first voltage level and a reference voltage level; a second node configured to carry a supply voltage having a supply voltage level in a power-on mode and a reference voltage level in a power-off mode; and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors is configured to receive a respective control signal of a plurality of control signals, and each control signal of the plurality of control signals has a first value based on the supply voltage in the power-on mode and a second value based on the signal in the power-off mode. In some embodiments, a control signal of the plurality of control signals has a third value based on the signal in the power-on mode. In some embodiments, the circuit further includes a voltage regulator coupled between the first node and the reference node, the voltage regulator configured to output a gate signal based on the signal, and a gate control circuit configured to output a plurality of control signals also based on the gate signal. In some embodiments, the voltage regulator is configured to output a gate signal having a value substantially equal to half of the first voltage level. In some embodiments, the voltage regulator is configured to output the gate signal as one of a plurality of gate signals having a number of gate signals, and the plurality of gate signals have a plurality of values substantially equal to a multiple of the first voltage level divided by the number of gate signals plus 1. In some embodiments, the voltage regulator includes a source follower. In some embodiments, the gate control circuit is configured to output each of a plurality of control signals having the power supply voltage level as the first value. In some embodiments, the plurality of transistors includes a first transistor and a second transistor, the first transistor is coupled between the first node and the second transistor, and the gate control circuit is configured to output the signal or the power supply voltage level as a first control signal of a plurality of control signals to the first transistor of the plurality of transistors. In some embodiments, the gate control circuit is configured to output a first control signal of the plurality of control signals having a first voltage level when the signal has the first voltage level. In some embodiments, the gate control circuit is configured to output the gate signal to a second transistor of the plurality of transistors in a power-down mode. In some embodiments, the circuit further comprises a pull-down driver coupled between the plurality of transistors and the reference node.
In some embodiments, an IC device includes: an input pad (pad) configured to receive an input signal; a conductor configured to carry a supply voltage; a gate control circuit configured to generate a first control signal and a second control signal, each of the first control signal and the second control signal based on a power supply voltage in a power-on mode and based on an input signal in a power-off mode; a first transistor coupled with the input pad, the first transistor including a gate configured to receive a first control signal; and a second transistor coupled in series with the first transistor, the second transistor including a gate configured to receive a second control signal. In some embodiments, the IC device further includes a voltage regulator including a voltage divider configured to divide the input signal, and a third transistor configured to receive the divided input signal and output a gate signal having a value of the divided input signal. In some embodiments, the gate control circuit includes a fourth transistor configured to output the gate signal as the second control signal in the power-down mode. In some embodiments, the gate control circuit includes a third transistor configured to output the power supply voltage as the second control signal in the power-on mode. In some embodiments, the gate control circuit includes a cross-coupled transistor pair configured to output the input signal or the second control signal as the first control signal.
In some embodiments, a method of controlling a node of a circuit comprises: the method includes receiving a signal at a node, controlling coupling of the node to the pull-down driver using a supply voltage in response to the supply of the circuit having a supply voltage level, and controlling coupling of the node to the pull-down driver using the signal in response to the supply of the circuit having a reference voltage level. In some embodiments, receiving the signal includes receiving a signal having a voltage level greater than a power supply voltage level. In some embodiments, using the supply voltage to control coupling the node to the pull-down driver and using the signal to control coupling the node to the pull-down driver each includes controlling the plurality of transistors with a plurality of control signals. In some embodiments, controlling the plurality of transistors with the plurality of control signals includes controlling a voltage across each transistor of the plurality of transistors to be less than or substantially equal to a maximum operating voltage of the plurality of transistors.
The foregoing has outlined features of some embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1 is a fail-safe circuit, comprising: a reference node configured to carry a reference voltage level; a first node configured to carry a signal having a first voltage level and the reference voltage level; a second node configured to carry a supply voltage having a supply voltage level in a power-on mode and the reference voltage level in a power-off mode; and a plurality of transistors coupled in series between the first node and the reference node, each transistor of the plurality of transistors configured to receive a respective control signal of a plurality of control signals, wherein each control signal of the plurality of control signals has a first value based on the supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
Example 2 includes the circuit of example 1, wherein a control signal of the plurality of control signals has a third value based on the signal in the power-on mode.
Example 3 includes the circuit of example 1, further comprising: a voltage regulator coupled between the first node and the reference node, the voltage regulator configured to output a gate signal based on the signal; and a gate control circuit configured to output the plurality of control signals also based on the gate signal.
Example 4 includes the circuit of example 3, wherein the voltage regulator is configured to output a gate signal having a value substantially equal to half of the first voltage level.
Example 5 includes the circuit of example 3, wherein the voltage regulator is configured to output the gate signal as one of a plurality of gate signals having a number of gate signals, and the plurality of gate signals have a plurality of values substantially equal to a multiple of the first voltage level divided by the number of gate signals plus 1.
Example 6 includes the circuit of example 3, wherein the voltage regulator includes a source follower.
Example 7 includes the circuit of example 3, wherein the gate control circuit is configured to output each of the plurality of control signals having the power supply voltage level as the first value.
Example 8 includes the circuit of example 3, wherein the plurality of transistors includes a first transistor and a second transistor, the first transistor is coupled between the first node and the second transistor, and the gate control circuit is configured to output the signal or the supply voltage level as a first control signal of a plurality of control signals to a first transistor of the plurality of transistors.
Example 9 includes the circuit of example 8, wherein the gate control circuit is configured to output a first control signal of the plurality of control signals having the first voltage level when the signal has the first voltage level.
Example 10 includes the circuit of example 8, wherein the gate control circuit is configured to output the gate signal to a second transistor of the plurality of transistors in the power-down mode.
Example 11 includes the circuit of example 1, further comprising a pull-down driver coupled between the plurality of transistors and the reference node.
Example 12 is an Integrated Circuit (IC) device, comprising: an input pad configured to receive an input signal; a conductor configured to carry a supply voltage; a gate control circuit configured to generate a first control signal and a second control signal, each of the first control signal and the second control signal based on the supply voltage in a power-on mode and based on the input signal in a power-off mode; a first transistor coupled with the input pad, the first transistor including a gate configured to receive the first control signal; and a second transistor coupled in series with the first transistor, the second transistor including a gate configured to receive the second control signal.
Example 13 includes the IC device of example 12, further including a voltage regulator, the voltage regulator including: a voltage divider configured to divide the input signal; and a third transistor configured to receive the divided input signal and output a gate signal having a value of the divided input signal.
Example 14 includes the IC device of example 13, wherein the gate control circuit includes a fourth transistor configured to output the gate signal as the second control signal in the power-down mode.
Example 15 includes the IC device of example 12, wherein the gate control circuit includes a third transistor configured to output the power supply voltage as the second control signal in the power-on mode.
Example 16 includes the IC device of example 12, wherein the gate control circuit includes a cross-coupled transistor pair configured to output the input signal or the second control signal as the first control signal.
Example 17 is a method of controlling a node of a circuit, the method comprising: receiving a signal at the node; in response to a power supply of the circuit having a supply voltage level, using the supply voltage to control coupling the node to a pull-down driver; and using the signal to control coupling the node to the pull-down driver in response to a power supply of the circuit having a reference voltage level.
Example 18 includes the method of example 17, wherein the receiving the signal includes receiving a signal having a voltage level greater than the power supply voltage level.
Example 19 includes the method of example 17, wherein the using the supply voltage to control coupling the node to the pull-down driver and the using the signal to control coupling the node to each of the pull-down drivers includes controlling a plurality of transistors with a plurality of control signals.
Example 20 includes the method of example 19, wherein the controlling the plurality of transistors with the plurality of control signals includes controlling a voltage across each transistor of the plurality of transistors to be less than or substantially equal to a maximum operating voltage of the plurality of transistors.
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