阅读说明：本技术 运算器算术电路设计方法在制造芯片中的应用 (Application of arithmetic circuit design method of arithmetic unit in manufacturing chip ) 是由 王全军 于 2019-11-11 设计创作，主要内容包括：本发明涉及运算器算术电路设计方法在制造芯片中的应用,可有效解决提高计算机运算速度的问题。把神算逻码编码解码及加减乘除倒数的算术电路设计方法替代二进制算法应用于芯片,不再发生进位或借位,运算结果再解码成二进制码,本发明电路级数少,把二进制数操作数送入运算电路到二进制运算结果从电路中输出,加减运算的电路级数小于10级,乘法运算与倒数运算的电路级数小于25级,除法运算的电路级数小于45级。所用的电子元件少,运算速度高,不仅能集成到计算机的芯片里,还能集成到单片机的芯片里,开拓了芯片制造的新途径,提高了计算机的工作效率,经济和社会效益巨大。(The invention relates to an application of arithmetic circuit design method of arithmetic unit in manufacturing chip, which can effectively solve the problem of increasing the operation speed of computer. The invention discloses a method for designing an arithmetic circuit for encoding and decoding magic logical codes and adding, subtracting, multiplying and dividing reciprocal, which is applied to a chip instead of a binary algorithm, no carry or borrow occurs any more, and an operation result is decoded into a binary code. The electronic elements used are few, the operation speed is high, the method can be integrated into a chip of a computer and a chip of a single chip microcomputer, a new way for manufacturing the chip is developed, the working efficiency of the computer is improved, and the economic and social benefits are huge.)

1. An arithmetic circuit design method of an arithmetic unit is applied to manufacturing a chip, and is characterized in that a mental arithmetic logic code coding and decoding and an arithmetic circuit design method of addition, subtraction, multiplication and division reciprocal are applied to the chip instead of a binary algorithm, carry or borrow does not occur any more, and an operation result is decoded into a binary code, and the method specifically comprises the following steps:

(1) when the computer carries out arithmetic operation, the high level is 1 code, and the low level is 0 code; the mental logical code expresses a code 0 by a virtual knot, expresses a code 1 by a real knot, and expresses data by combining the real knot and the virtual knot; the knot number of one digital rope is the sum of the real knot number and the virtual knot number, and the numerical value expressed by one digital rope is equal to the sum of all the real knot numbers in the digital rope; the solid knots and the virtual knots in the digital rope can be combined and arranged at will, the solid knots are arranged from one end of the digital rope, all the digital ropes with the adjacent solid knots are standard digital ropes, and the numerical values are expressed by the standard digital ropes; the solid knot starting end of the standard digital rope is the head end of the digital rope, and the other end of the standard digital rope is the tail end of the digital rope; when the real knot or the real knot section in the digital rope does not take the head end of the digital rope as the starting end or possibly does not take the head end of the digital rope as the starting end, the real knot or the real knot section is translated to the head end of the digital rope; when two digital ropes are connected into a standard digital rope, the two digital ropes are translated into the standard digital rope through a solid knot or a solid knot section, the two standard digital ropes are connected into the digital rope, and then the standard digital rope is formed through translation of the solid knot or the solid knot section; when the real knots or the real knot sections and the virtual knots or the virtual knot sections of the digital ropes are mutually staggered, the digital ropes are regarded as a plurality of digital ropes, every four digital ropes are divided into a group and translated into one digital rope, and finally the digital ropes are combined into one standard digital rope; when a plurality of digital ropes are connected into one digital rope, every four digital ropes are divided into one group, each group becomes one digital rope after translation, then the four digital ropes are used as one group for translation, and after the digital ropes are translated into one digital rope, the last digital rope is translated into a standard digital rope; the mental arithmetic logical code coding is to convert the binary code into a standard mental arithmetic logical code through a circuit; the coding method 1 is to use two phase phases and circuit phase-by-layer phase phases to respectively calculate all decimal values, add the calculated numbers to corresponding number knots, and fill any one of the knots into a knotIs a standard digital rope; the coding method 2 is to use the multi-channel AND circuit to respectively calculate the decimal value, add the calculated number to the corresponding number rope knot, and fill all knots below the knot into a real knot as a standard number rope; the coding method 3 is to make each bit into a digital rope circuit, N digital ropes are provided as N binary numbers, the N digital ropes are connected into one digital rope, the N digital ropes are subjected to grouping translation real knot or real knot section, and finally a standard digital rope is obtained; replacing the real knot of the digital rope with a virtual knot from the head end, and only reserving the uppermost real knot, wherein the real knot is the buoy code of the digital rope, and the digital rope with the buoy code is the buoy digital rope; the digital rope decoding is to convert the buoy digital rope into binary code, and the method comprises the following steps: on the buoy digital rope, from the head end, connecting the 1 st knot to the 0 bit of the binary system, connecting the 2 nd knot to the 1 bit of the binary code, connecting the 3 rd knot to the 0 bit and the 1 bit of the binary code, connecting the 1 st knot to the 3 bit of the binary code, connecting the 5 th knot to the 0 bit and the 3 bit of the binary code, and so on until all knots and the binary codes are connected, and then isolating to ensure that each knot and other knots are in an isolated state; the digital rope addition operation is to connect two or more digital ropes into a new digital rope, the new digital rope is made into a standard digital rope, and the total number of real knots in the standard digital rope is the sum of the addition; in the arithmetic operation circuit, a port is led out from the 1 st knot of a standard digital rope converted from an operand, and the numerical value of the operand can be expressed to be 0 or not 0; the digital rope subtraction operation is to align the head ends of two standard digital ropes for comparison, and make the real knot difference value of the two digital ropes into a new standard digital rope by comparison, wherein the digital rope comparison has two methods, and the two methods can lead out a symbol mark port; one number can be expressed by one digital rope and also can be expressed by a group of digital ropes; when the number is expressed by the digital rope group, the digital ropes in the digital rope group form a stage, when the stage of the digital rope group is m, the numerical value expressed by each real knot in the first digital rope is 1, the numerical value expressed by each real knot in the second digital rope is m, and the numerical value expressed by each real knot in the third digital rope is m²The value expressed by each real knot in the jth digital rope is mj-¹(ii) a In the digital rope group, when the knot number of any one digital rope is not less than the series number of the group, the digital rope group is a digital rope group with saturated knots, and when the knot number of each digital rope is less than the series number of the group, the digital rope group is a digital rope group with unsaturated knots; the knotted unsaturated digital rope group can decode each digital rope into binary codes respectively, and the decoding results of each digital rope are combined after decoding to restore the binary codes; the knot saturated digital rope group decoding method comprises the steps of firstly converting m-grade digital rope groups into one digital rope with each real knot expression numerical value of 1, then decoding, or carrying out grade skipping or decoding through circuit operation to carry out grade skipping and knot reduction to enable the number of knots of each digital rope in the digital rope groups to be equal to the grade, then reducing the number of knots through parallel grade skipping of a plurality of digital ropes or reducing the number of knots through serial grade skipping of one digital rope by one digital rope to enable the saturated digital rope groups to be converted into unsaturated digital rope groups, and decoding by the unsaturated digital rope groups; the addition operation of the digital rope group is to convert two or more added operands into standard digital rope groups with the same level, combine two or more standard digital ropes with the same level into a new saturated standard digital rope group, combine two or more digital ropes with the same expression value in the digital rope group into a new standard saturated digital rope, enable each digital rope in the digital rope group to be an unsaturated digital rope through the skipping reduction combination of the digital rope group, and decode the unsaturated digital group to complete the addition operation; when two binary operands A minus B and the result is a binary number C, the two operands are made into two digital rope groups, the operation of the two digital rope groups A and B consists of three parallel circuits, the first parallel circuit is that the A digital rope group is subtracted by the false code digital rope group and then the addition operation is carried out with the B digital rope group, the second parallel circuit is that the B digital rope group is subtracted by the false code digital rope group and then the addition operation is carried out with the A digital rope group, the third parallel circuit is that the two subtraction binary operands are compared, the comparison result is used as a symbol mark of the subtraction operation, the two symbol marks control two AND gate switch groups, the AND gate switch group switches on the second circuit when A is larger than B, and switches on the first circuit when A is smaller than BThe circuit obtains the subtraction of the digital rope group behind the AND gate switch group; the whole process of the subtraction operation of the number 7 rope groups is as follows: a, B two binary numbers are made into two digital rope groups with the number of m;

(2) the circuit 1 performs the operation of subtracting the B groups of digital ropes from the false codes, and the circuit 2 performs the operation of subtracting the A groups from the false codes;

(3) the circuit 1 performs addition operation by using a digital rope group A and a result digital rope group of a false code minus digital rope group B, and the circuit 2 performs addition operation by using a digital rope B and a result digital rope of the false code minus digital rope A;

(4) the addition operation results of the circuit 1 and the circuit 2 respectively pass through the skipping code elimination of the digital rope group to enable the result digital rope group to be a saturated digital rope group with the same level number and knot number, then respectively pass through the small string skipping code elimination or the parallel skipping code elimination to enable the digital rope group to be an unsaturated digital rope group, the two unsaturated digital rope knots are respectively decoded to obtain two binary result codes, the carry in the result codes is omitted, two subtraction operation results are obtained, one result is a correct result, and the other result is an incorrect result;

(5) when the circuit 1 and the circuit 2 are operated, the binary numbers A and B are compared at the same time, the two binary numbers are used as two 2-level digital rope groups in the comparison process, two digital ropes with symbol bow marks are obtained by comparing the two digital rope groups, two symbol marks a and symbol marks B of A minus B are obtained by comparing the two digital ropes, the symbol mark a is used for controlling one group of AND gate switch groups of the connecting circuit 1, and the symbol mark B is used for controlling one group of AND gate switch groups of the connecting circuit 2;

(6) the output ports of the two AND gate switch groups are connected in parallel to obtain a subtraction result, and meanwhile, in a comparison circuit of binary numbers A and B, a subtracted number 0 and a subtracted number non-0 mark and a subtracted number 0 and a subtracted number non-0 mark are obtained through the circuit; the subtraction result data, the symbol mark, the subtracted number, the 0 and non-0 mark of the subtracted number form the subtraction operation together; the multiplication operation of the digital rope group is to make two multiplied operands into two 2-level digital rope groups, carry out factorization, add the factors of the same bit into one digital rope, form the N-by-N bit multiplication operation into 2N-1 digital ropes to form one 2-level digital rope group,making each digital rope into a standard digital rope, then making the digital rope into an unsaturated digital rope group through skipping and knot eliminating, and then decoding the unsaturated digital rope group into a binary code, wherein each digital rope in the digital rope group has two methods for making the standard digital, the method 1 is that each node in each digital rope in the C digital rope group is used as a digital rope, the real knot translation of the digital ropes at the same level is carried out, and the digital ropes are made into a standard digital rope through multiple translation real knots or real knot sections; the method 2 is that each digital rope in the digital rope group is made into a standard digital rope in a parallel number finding mode; the reciprocal operation of the digital rope is that the digital rope B is taken as the reciprocal of the digital rope A, A, B is taken as a 2-level digital rope group when the reciprocal A of an N-bit binary number B is solved, and the condition that A times B is equal to 2 is assumed²ⁿEstablishing a digital rope group A of reciprocal operation by the inverse operation of multiplication operation, converting each digital rope in the digital rope group A of reciprocal operation from addition and subtraction mixed operation into addition operation, enabling each digital rope in the digital rope group of reciprocal operation to be a standard digital rope by the addition operation, enabling the saturated digital rope group of reciprocal operation to be an unsaturated standard digital rope by a skip reduction knot, and then decoding the rope into a binary code; the division operation of the digital rope group is to make dividend and divisor into two digital rope groups with 2 stages, firstly carry out reciprocal operation on the divisor, and then carry out multiplication operation on the result of the reciprocal operation and the dividend; the arithmetic operation circuit of the digital rope or the digital rope group carries out unsigned integer operation, only the front end of the unsigned integer arithmetic operation circuit is added with an input interface to carry out arithmetic operation on fixed point numbers, floating point numbers and symbolic numbers, and only the output interface is added after the arithmetic operation is carried out on the fixed point numbers, the floating point numbers and the symbolic numbers to ensure that a CPU obtains the operation result of the required integer numbers, fixed point numbers, floating point numbers or symbolic numbers; the interface circuit of the addition, subtraction, multiplication, reciprocal and division operation is an unsigned operation interface or a charpy operation interface; the input interface of an arithmetic operation circuit consists of parallel integer interfaces, fixed point number interfaces and floating point number interfaces, the three input interfaces are simultaneously connected to the input port of the arithmetic operation circuit through an AND gate switch group, and one of the interfaces is controlled by an operation instruction of a CPU to be switched on and operand is input from the interface; fixed point countingThe interface of floating point number, there is a data conversion circuit in the interface, convert the fixed point number, floating point number into the integer meeting the arithmetic operation circuit requirement through the data conversion circuit: the signed arithmetic operation realizes the selection of an operation mode and the sign of output data in the input connection U and the output connection U through a sign operation circuit; the output end of the arithmetic operation circuit is connected with three output interfaces of integer, fixed point and floating point in parallel, the data output by the three output interfaces have different systems but the same numerical value, and the CPU can select any one output interface to fetch the data; in the interface circuit of arithmetic operation, the input interface circuit of addition, subtraction, multiplication, reciprocal, division operation circuit is three, the addition of output interface circuit, subtraction, multiplication circuit is three, the output interface circuit of reciprocal operation and division operation circuit is two; the input interface of the division operation circuit consists of a dividend input interface and a divisor input interface, the dividend input interface is the same as the input interface of the multiplication circuit, the input interface of the divisor is the same as the input interface of the reciprocal circuit, and the output interface of the division is the same as the output interface of the reciprocal circuit.

2. The application of arithmetic circuit design method of arithmetic unit as claimed in claim 1 in manufacturing chips, wherein when the real knot or real knot section in the digital rope is not started from the head end of the digital rope or may not be started from the head end of the digital rope, the real knot or real knot section is translated to the head end of the digital rope by setting a number of digital knots as m, which are 1,2,3,4,5. Carrying out isolation translation on the 1,2,3,4,5.. i.. m knot by using a one-way conduction element, and connecting to the 1,2,3.. i.. m-1 knot of the digital rope after translation; the 2 knots are isolated and then translated to the head end of the digital rope, and the 2 knots are respectively connected with the 3,4,5,. i.m knots and then are respectively connected to the 2,3,4.. i.m-2 knots of the translated digital rope; the 3 knots are isolated and then translated to the head end of the digital rope, and the 3 knots are respectively connected with the 4,5,6. Sequentially performing phase comparison until the mth knot is isolated and then translating to the head end of the digital rope;

the two standard digital ropes are connectedConnecting the two digital ropes to form a digital rope, then translating the solid knot or solid knot section to form a standard digital rope, namely connecting the head ends of the two digital ropes to form a new non-standard digital rope, and then translating the solid knot or solid knot section in the digital rope to form the standard digital rope; the head end of a standard digital rope can be connected with the tail end of another standard digital rope to form a new digital rope, one solid knot or solid knot section is arranged at one end of the digital rope, the head end of the digital rope is the head end of the digital rope, and the standard digital rope is formed by translating the solid knot or solid knot section in the rope: the number of one standard digital rope knot is m, and the standard digital rope knot is a from the head end₁,a₂,a₃,a₄...a_i..a_mThe knot number of the other standard digital rope is n and is b from the head end₁,b₂,b₃,b₄...b_i...b_nA knot is connected in a manner of b₁Terminal is connected to a_mA terminal; the translation method comprises the following steps: a is_1，a₂,a₃，a₄...a_i..a_mAfter isolation is c₁,c_2，c₃,c₄...c_i...c_m,b_1；b₂,b₃,b₄...b_i...b_nAfter isolation are respectively connected to c₁,c_2，c₃,c₄...c_i..c_mKnotting; with a₁Respectively and b_1,b₂,b₃,b₄...b_i...b_nAnd then are connected to c₂,c₃,c₄...c_i..c_mThe phase result at the very end of the knot is c_m+iKnot formation; with a₂Knot of each and b_1；b₂,b₃,b₄...b_i...b_nPhase and back are respectively connected to c_2，c₃,c₄...c_i..c_m,c_m+iThe phase at the extreme end of the junction is c_m+2Knot formation; with a₃Knot of each and b₁,b₂,b₃,b₄...b_i...b_nPhase and back are respectively connected to c₄...c_i..c_m，c_m+i,c_m+2The phase at the extreme end of the junction is c_m+3Knot formation; sequentially performing phase reaction until m junction is respectively subjected to phase reaction with b₁,b₂,b₃,b₄...b_i...b_nAnd then ending;

every four digital ropes divide into a group and translate into a digital rope: when four digital ropes are connected into one digital rope, each digital rope is made into a standard digital rope, the head ends of the two middle digital ropes are connected to form one digital rope, the two digital ropes outside the digital rope are subjected to solid knot or solid knot section translation to form one digital rope, and then the digital rope is formed into the standard digital rope through the solid knot or solid knot section translation.

3. The application of the arithmetic circuit design method of an arithmetic unit as claimed in claim 1 in chip manufacturing, wherein the digital rope coding method has three kinds, respectively:

A. the method 1 comprises the following steps: performing phase-by-phase operation on the two paths of phases and the circuit layer by layer, and arranging the coded binary system from the lowest position to the upper position as a 0 th position and a1 st position. The 0 th bit is the 1 st knot of the digital rope after being isolated by the circuit, the 1 st bit is the 2 nd knot after being isolated by the circuit, the 3 rd bit is the 8 th knot after being isolated by the circuit, the 1 st bit is the 2 nd knot after being isolated by the circuitⁱKnot formation; taking the phase of 0 and 1 as the 3 rd junction, the phase of 0 and 2 as the 5 th junction, and the phase of 0 and 1 as the 2 nd junctionⁱ+1 junction; taking the phase of 1 and 2 as the 6 th junction, the phase of 1 and 3 as the 10 th junction, and the phase of 1 and i as the 2 nd junctionⁱ+2 junctions; taking the phase of the i-1 bit and the i bit as a first layer, performing phase comparison of a second layer and a third layer until all numerical values are completely calculated and expressed by the digital knots, and filling all knots after any solid knot in the digital rope into the solid knots;

B. the method 2 comprises the following steps: the numerical values expressed by all digital knots are calculated by a first-stage circuit by using a multi-path phase-inversion method, a second-stage circuit fills all knots behind any one real knot into the real knot, and a four-digit binary number is coded into a mental logical code, wherein the 0 bit is 1 knot, the 1 bit is 2 knot, the 0 bit and the 1 bit are 3 knots, the 2 bit is 4 knot, the 0 bit and the 2 bit are 5 knots, the 1 bit and the 2 bit are 6 knots, the 0 bit, the 1 bit and the 2 bit are 7 knots, the 3 bit is 8 knots, the 0 bit and the 3 bit are 9 knots, the 1 bit and the 3 bit are 10 knots, the 0 bit, the 1 bit and the 3 bit are 11 knots, the 2 bit and the 3 bit are 12 knots, the 0 bit, the 2 bit and the 3 bit are 13 knots, the 1 bit, the 2 bit and the 3 bit are 14 knots, and the 0 bit, the 1 bit, the 2 bit and the 3 bit are four-phase inverses and 15 knots;

C. the method 3 comprises the following steps: each bit of the binary code is made into a standard digital rope, when each bit of the 2-bit binary code is made into a standard digital rope, each standard digital rope is either all virtual knots or all real knots, the knot number of each 1 digital rope is the numerical value of the digit number of the standard digital rope, the knot number of the 0-bit digital rope is 1, the knot number of the 1-bit digital rope is 2, the knot number of the 2-bit digital rope is 4, and the knot number of the i-bit digital rope is 2ⁱ(ii) a And (3) translating, combining and numbering the digital ropes, combining every four digital ropes into one digital rope by using a primary circuit, making the combined digital rope into a standard digital rope, combining every four standard digital ropes into one digital rope again, and ending the steps until the digital ropes are combined into one standard digital rope.

4. The application of the arithmetic circuit design method of an arithmetic unit as claimed in claim 1 in the manufacture of chips, wherein the real knot of the floating digital rope is replaced with the virtual knot from the head end, the floating digital rope is established by replacing the real knot of the standard digital rope with the virtual knot, only the uppermost one of the real knots is reserved, the circuit is that the ith knot is compared with the (i +1) th knot, the ith knot is converted into the virtual knot when the (i +1) th knot is the real knot, and the virtual knot of the ith knot is reserved only when the (i +1) th knot is the real knot; the i +1 th junction and the ith junction can be used for phase comparison, and the phase comparison result can be inverted by a NOT gate and then be phase compared with the ith junction, or the i +1 th junction can be inverted by the NOT gate and then be phase compared with the ith junction.

5. The application of arithmetic circuit design method of arithmetic unit as claimed in claim 1 in chip manufacture, wherein there are two methods of digital string subtraction, method 1 is: knot of two subtracted standard digital ropes from head endSerial numbers are respectively a_1，a₂,a₃，a₄...a_i..a_mAnd b₁,b₂,b₃,b₄...b_i...b_nThe number of the difference digital rope is c₁,c_2，c₃,c₄...c_i...c_mA handle₁In the same way as b₁Performing NAND operation, and respectively obtaining the same result as a_1，And b₁And obtaining two operation results by phase inversion or obtaining the node c of the digital rope_i(ii) a Making the digital rope C into a standard digital rope, then making the standard digital rope into a buoy digital rope, decoding the buoy digital rope to obtain a binary code, and leading out a symbol mark port from the arithmetic circuit;

the method 2 comprises the following steps: a is₁After being turned over by NOT gate, the leaf and the leaf are connected with each other₁And a result obtained, b₁After turning over by NOT gate, the same as a₁Phase-and-joining to obtain one result, and then re-phase the two results or obtaining the node c of the digital rope₁Making the digital rope C into a standard digital rope and then into a buoy digital rope, decoding the buoy digital rope to obtain a binary code, and leading out a symbol mark port from the arithmetic circuit;

the subtraction is also treated as sign operation, and a sign flag port is drawn from the subtraction circuit, in the circuit of the subtraction method 1, in a₁In the same way as b₁Performing NAND operation, and the operation result is identical to a₁The result of the AND operation is led out of port A at a₁In the same way as b₁Performing NAND operation, and repeating the operation result with b₁Leading out the port B after the phase comparison result is obtained, and isolating the led-out port; method 2 is to subtract in the circuit of method 2 from a₁After being turned over by NOT gate, the leaf and the leaf are connected with each other₁The result of the AND is led out of port B, from B₁After turning over by NOT gate, the same as a₁Leading out the port A after the result of the phase comparison; when A is 1, B must be 0 until the symbol; when B is 1, a must be 0 and the sign is negative, when A, B is 0 at the same time, the two subtracted operands are equal.

6. The arithmetic circuit design method of claim 1 inThe application in manufacturing the chip is characterized in that the skipping is carried out through circuit operation, so that the knot number of each digital rope in the digital rope group is equal to the number of the knot number, the method is that each digital rope in the digital rope group is a standard digital rope, the number of the knot numbers of at least one digital rope in the digital rope group is m and more than 1, and the knot number of the digital rope group is more than m; at the moment, (1) each digital rope in the digital rope group is made into a standard digital rope, in the ith digital rope, the mth knot jumps up to the (i +1) th digital rope, and the mth knot jumps up to the (m +1) th digital rope²The knot jumps up to the (i + 2) th digital rope, the m th³Jump the knot up to the (i + 3) th digital rope^jThe knot jumps up to the (i + j) th digital rope; (2) comparing whether the skip level junction is a solid junction or not, when the mth junction is the solid junction^jWhen the knot is a real knot, all knots smaller than j are arranged into a virtual knot, and skip points smaller than j are also arranged into virtual knots; the number of knots without skipping before skipping knot is reserved, when x skipping points are arranged in one digital rope, y skipping knots are arranged, the y skipping knot is a solid knot, all knots after the y skipping knot are skipped, a knot above the y +1 knot is a virtual knot, the knots from the y +1 knot to the y knot can be solid knots without skipping, and the knots from the y +1 knot to the y knot are reserved; when all the skip level junctions are dummy junctions, the junctions after the first skip level junction are reserved; the reserved knots and the knots on the skipping level are made into a standard digital rope by moving solid knots or solid knot sections; when the knot number of the digital rope is m, the maximum skipping number is h, n-h>m is, m of the digital rope^hPerforming parallel stage skipping on the parts above the junction; when the remained junctions can still jump after the parallel jump, the parallel jump is carried out again until no remained junctions can jump; (3) repeating the steps until the knot number of each digital rope in the digital rope group is equal to the number of stages;

the knot number is reduced by skipping the knot number through decoding, so that the knot number of each digital rope in the digital rope group is equal to the number of the steps, and the method comprises the following steps: (1) decoding each digital rope in the digital rope group into a binary code, and determining a grade skipping point according to the grade number of the digital rope group; when the number of a digit group is 2, after decoding the ith digit rope into binary code, the 0 th digitThe method comprises the steps of not skipping, skipping from the ith position to the (i + i) th digital rope, skipping from the 2 nd position to the (i + 2) th digital rope, skipping from the 3 rd position to the (i ≠ 1) th digital rope, and skipping from the jth position to the (i + j) th digital rope; when the number of stages of the digital rope group is 4, after the ith digital rope is decoded into a binary code, the 0 th bit and the 1 st bit do not skip stage, the 3 rd bit skips stage to the 1 st digital rope, the 4 th bit skips stage to the i ≠ 1 digital rope with 2 nodes, the 5 th bit skips stage to the i ≠ 2 digital rope, the 6 th bit skips stage to the i +2 th digital rope with 2 nodes, and the 7 th bit skips stage to the i +3 th digital rope; when the number of the digital rope group is m and m is a multiple of 2, after each i digital ropes are decoded into binary codes, the bits smaller than m are reserved, the bits equal to m jump to the i ≠ 1 digital ropes, the bits equal to A × m, A is larger than 1, and A × m is smaller than m²From A nodes to the (i +1) th digital rope, equal to m²Is stepped into the (i + 2) th digital rope and is equal to Axm²A is greater than 1 and A x m is less than m³From A nodes to the i +2 th digital rope, and so on, equal to m^jIs stepped to the ith number rope not equal to j, and is equal to Axm^jA is greater than 1 and A x m^jLess than m^j+1Using A nodes to the ith is not equal to j digital ropes; (2) after the grade skipping, the retained binary code and the mental logical code on the grade skipping are reserved in the ith digital rope, the retained binary code is decoded into the mental logical code to form a digital rope, and the digital rope is made into a standard digital rope and then is made into a buoy digital rope; when the number of the digital rope group is 2, the reserved 0 th binary code is also a digital rope, and the digital rope is directly made into a standard digital rope without decoding and then is made into a buoy digital rope; (3) repeating the steps until each digital rope in the digital rope group is reduced to the stage number equal to the knot number;

and then the digital rope group with the same number of stages and knots is subjected to parallel skipping by a plurality of digital ropes, so that the saturated digital rope group is converted into an unsaturated digital rope group: when each digital rope in the m-level digital rope group is m knots, each digital rope is made into a buoy digital rope, the mth knot of each digital rope is an upward skipping-stage knot, the parallel skipping stage is the mth knot of each digital rope is upward parallel skipping stage, and the mth knot of the ith digital rope for performing the parallel skipping stage skips stages to the (i +1) th digital rope and all the digital ropes above the ith digital rope at the same time; after parallel grade skipping, each digital rope in the digital rope group keeps all knots below a skip-in knot, an m-2 knot and an m-2 knot, the number of the reserved knots is smaller than the grade number of the digital rope group, and the method for skipping grades to the (i +1) th digital rope and all digital ropes above the (i +1) th digital rope by the m knot of the ith digital rope is as follows: the m-th knot of the ith digital rope and the m-1 th knot of the ith digital rope which is not equal to 1 form a1 st phase and circuit, the m-th knot of the ith digital rope and the m-i knot of the ith digital rope which is not equal to 1 and i +2 th digital rope form a2 nd phase and circuit, the m-th knot of the ith digital rope and the i +1, i +2 and i +3 th digital rope form a3 rd phase and circuit, and so on, when n digital ropes exist in the digital rope group, the n-i phases and circuits are formed; in the n-1 phase AND circuit, the result of the j +1 phase AND circuit is inverted by an NOT gate and then is subjected to phase addition again with the result of the j phase AND circuit, and then is subjected to phase addition and post-skipping to an i +2 digital rope; the method for skipping from the level to the (i +1) th digital rope is characterized in that the result of the phase 1 and the circuit is respectively ANDed with the m knot of the ith digital rope and the m-1 knot of the (i ≠ 1) th digital rope after being inverted by a NOT gate; the phase of the (n-1) th phase and the circuit is the phase of a new digital rope in the digital rope group, and the phase is directly and mutually matched with the last digital rope in the original digital rope group.

7. The application of the arithmetic circuit design method of the arithmetic unit according to claim 1 in manufacturing chips, wherein the number of the digital rope sets with the same number of stages and knots is reduced by the parallel skipping of a plurality of digital ropes or the serial skipping of digital ropes one by one, and when the number of the knots of each digital rope of the digital rope set with the number of stages m is equal to m and n digital ropes are in total in the digital rope set, the method for converting the serial skipping of digital ropes one by one into the unsaturated digital rope set is as follows: each digital rope in the digital rope group is made into a standard digital rope; (1) jumping the m knots of the first digital rope into the 2 nd digital rope, and when the m knots are real knots, setting all the knots of the first digital rope as virtual knots, and decoding the virtual knots into binary codes; when the m knot is a virtual knot, the m-1 knot and knots below the m-1 knot are reserved, and the reserved knots are made into the number of buoysA word string is decoded into a binary code; (2) the m knots of the 2 nd digital rope and the i knots jumped into the first digital rope are made into a standard digital rope with m ≠ i knots, and the m knots of the second digital rope are jumped into the third digital rope; when the m-junction is a solid junction, only the first one is reserved_m+1 knot, decoding the remained one knot into binary code; when the m knots are virtual knots, the m-1 knots and knots below the m-1 knots are reserved, the reserved knots are made into a buoy digital rope, and then a binary code is decoded; similarly, the m knots of the ith digital rope and the 1 knot into which the (i-1) th digital rope jumps are made into a standard digital rope with m + l knots, and the m knots of the ith digital rope jump into the (i +1) th digital rope; when the m knot is a real knot, only reserving the m ≠ 1 knot, and decoding one reserved knot into a binary code; when the m knots are virtual knots, the m-1 knots and the knots below the m-1 knots are reserved, the reserved knots are made into a buoy digital rope, and then the buoy digital rope is decoded into a binary code.

8. The application of the arithmetic circuit design method of claim 1 in chip fabrication, wherein when two binary operands A minus B, the first parallel circuit is a pseudocode digit string minus A digit string, the second parallel circuit is a pseudocode digit string minus B digit string, and the method using the pseudocode is: a, B, comparing two operands, when A is larger than B, the operation of subtracting B from A is converted into the operation of subtracting B from the carry bit of the operation circuit, the result is added with A, when B is larger than A, the operation of subtracting A from the carry bit of the operation circuit, the result is added with B, when A is equal to B, the subtraction result is set as 0, and the operation is not performed, the mathematical expression is:

a > B and a-B = C, a-B = a + (X-B) = X + C; b > A and A-B = C, A-B = - [ B + (X-A) ] = - (X + C)

The method used by the pseudocode is as follows: the number of stages of the two digital rope groups is m, and the arrangement sequence of the digital ropes in the A, B two digital rope groups is a_1，a₂,a₃，a₄...，a_i...,a_nAnd b₁,b₂,b₃,b₄...b_i...b_nWhen A is greater than B, the mathematical expression after adding the carry bit of the false code is that the first result numberThe word rope is a₁+（m-1-b₁) The second result number string is a₂+(m-1-b₂) The ith result number rope is a_i+(m-1-b_i) The nth result number string is a_n+(m-l-b_n) (ii) a Assuming that A is smaller than B, the mathematical expression after adding the carry bit of the pseudocode is that the first resulting digital string is- [ B [ ]₁+(m-l-a₁)]The second resulting digital string is- [ b [ ]₂+(m-1-a₂)]The ith result number string is- [ b [ ]_i+(m-1-a_i)]The nth result number string is [ b ]_n+(m-1-a_n)]；

When two binary numbers A and B are compared, A, B two binary numbers are directly used as two 2-level digital rope groups, A minus B operation and B minus A operation are respectively carried out on digital ropes with equivalent knot number expression values in the two digital rope groups A and B to obtain a digital rope consisting of A symbol marks and a digital rope consisting of B symbol marks, the two digital ropes consisting of the two symbol marks are respectively formed into two standard digital ropes through filling and real knot, and then subtraction operation is carried out on the standard digital ropes consisting of the two symbol marks to obtain a symbol mark a and a symbol mark B; the symbol mark a and the symbol mark b only have one symbol as 1, and the two symbol marks can be 0 but cannot be 1 at the same time; when a is 1, A is larger than B; when B is 1, B is larger than A; when a and B are both 0, A is equal to B;

the multiplication operation of the digital string group is to make two multiplied operands into two 2-level digital string groups: when an number of knots are arranged in one digital rope, aj knots in the an knots are solid knots; carrying out the common and operation on the an knots through a circuit, wherein the result of the common and operation is 1 when aj is equal to an, the result of the common and operation is 0 when aj is smaller than an, and the result of the common and operation is used as a bn knot of the standard digital rope; taking an-l' f completely same junctions from the an junctions to perform parallel and operation through a circuit, connecting the results of the parallel and operation in parallel, wherein the result of the parallel and operation is 1 when aj is greater than or equal to an-1, the result of the parallel and operation is 0 when aj is less than an-1, and the result of the parallel and operation is used as a bn-i junction of the standard digital rope; ai nodes which are not identical are taken from an nodes and are subjected to parallel and operation through a circuit, the results of the parallel and operation are connected together in parallel, the result of the and operation is 1 when the sentence is larger than or equal to ai, the result of the and operation is 0 when aj is smaller than ai, and the result of the parallel and operation is used as a second node of the standard digital rope, wherein n > i > 1; when i =1, carrying out the common OR operation on the an junctions through the circuit, wherein when all the an junctions are virtual junctions, the common OR operation result is 0, as long as the common OR operation result of one real junction in the an junctions is 1, and the Regenation result is taken as the 1 st junction of the standard digital rope;

the method for establishing the digital rope group A by the inverse operation of the multiplication operation comprises the following steps: deducing by the inverse operation that the A digital rope group multiplied by the B digital rope group is equal to the C digital rope group, wherein the mathematical model is integer operation, when the binary number expressed by the B digital rope is N bits, the A digital rope group is the reciprocal of the B digital rope group, the number of bits expressed by the B digital rope group is also N bits, and the C digital rope group is 2 expressed by 2N-l digital ropes²ⁿNumerical value and mathematical relation of A =2²ⁿB, the operation result is shifted to the right by 2n bits; because the reciprocal mathematical model is established in the C digital rope group to express 2²ⁿNumerically, the number expressed by the nth digital rope of the 2-level digital rope group B is 1, that is, the nth bit of the binary operand must be 1; if the N bit of the binary operand is not 1, the binary operand is left shifted to 1, and the reciprocal operation is mathematically related to A = (2) assuming that the operand is left shifted by m bits²ⁿ/B）*2^mThe integer result of the reciprocal operation should be multiplied by 2^m-2n；

Each digital rope in the digital rope group A with reciprocal operation is converted into addition operation by addition and subtraction mixing operation, and the conversion method comprises the following steps: (1) the expression jumps: all 2 x a in the expression_ib_iEliminating the code of this stage together with the symbol jumping up one stage, and eliminating all 4A in the expression_ib_iJumping up 2 levels together with the symbol to eliminate the code of the level, so that the coefficient in each digital rope is 1; (2) converting the negative sign to a not-gate sign: all the a with negative sign in each digital rope_i，b_i，aibj to (1-a)_i），（1-b_i) (1-aibj) is made positive, and a signed real junction due to conversion is added to the expression(ii) a (3) And (3) solid junction jump stage: when the real knot in each digital rope group is larger than 1, jumping up the grade together with the symbol, so that the absolute value of the real knot number in each digital rope group is maximum 1; (4) elimination of negative numbers with a pseudocode: make a set of values equal to 2²ⁿThe first digital rope in the digital rope group is two real knots, and negative sign real knots in each digital rope group are eliminated by the digital rope group with the reciprocal digital rope group; (5) and (3) solid junction jump stage: and when the number of the solid knots in each digital rope is more than 1, skipping the grade again, so that the maximum number of the solid knots in each digital rope is 1.

9. The application of the arithmetic circuit design method of an arithmetic unit as claimed in claim 1 in chip manufacture, wherein the interface circuit for addition, subtraction, multiplication, reciprocal and division is an unsigned operation interface or a signed operation interface, and when the addition and subtraction operations are signed operations, the input interface circuit is: the signed addition operation needs to have a subtraction operation circuit at the same time, the signed subtraction operation needs to have an addition operation circuit at the same time, the addition and subtraction operation circuits are respectively composed of double N-bit operation circuits, the first N bits are integer parts, the second N bits are decimal parts, and the two input interface circuits with the signed operation are the same; the signed addition and subtraction input end interface circuit consists of a double-operand inlet, a fixed point number conversion circuit, a floating point number conversion circuit, an integer sign operation and control circuit, a fixed point number sign operation and control circuit, an integer instruction control circuit, a fixed point number instruction control circuit, a floating point number instruction control circuit and twelve and gate switch groups, wherein the double-operand inlet is in the form of an integer, a fixed point number and a floating point number; the work flow of the input end n-connection circuit is as follows: the operand form entering the n-connection circuit is selected by a CPU instruction, when one form of an integer, a fixed point number and a floating point number is selected, an and gate switch group controlled by the instruction control circuit is communicated, and the CPU inputs two corresponding operands according to the selected form; the fixed point number conversion circuit and the floating point number conversion circuit convert data into an integer part and a decimal part; the sign operation and control circuit performs sign operation and is connected with the addition operation circuit or the subtraction operation circuit;

the selection of the operand form entering the interface circuit by the CPU instruction is as follows: three input interfaces of the addition and subtraction operation are all connected to the input end of the operation circuit by three groups of AND gate switch groups, and the opening and closing of the AND gate switch groups are controlled by the operation instruction of the CPU; when the operation instruction is integer operation, the AND gate switch group connected with the integer input interface is turned on; when the operation instruction is fixed point number operation, the fixed point number input is connected with n and is opened; when the operation instruction is a floating point number, the floating point number input is connected with the AND gate switch group connected with the u and is switched on;

the fixed point number conversion circuit converts data into an integer part and a decimal part, and the fixed point number conversion circuit refers to the following steps: a fixed point number is that the size of the number is expressed by an n-bit numerical value before a decimal point is fixed at the highest position; or after fixing the decimal point at the lowest bit, expressing the size of the number by using a-n-bit numerical value; the data conversion of the fixed point number is to shift the binary code of N-digit value to the left by N bits and to shift the binary code of-N-digit value to the right by N bits, the shifted binary code is composed of an integer and a decimal, the integer part is sent to the front N-bit operation circuit, and the decimal part is sent to the back N-bit operation circuit; the left shift or the right shift is as follows: limiting the number N of bits of the most artificial arithmetic unit of the value of N, making a binary code which expresses N and is sent from an input operand inlet into a buoy digital rope with the number N of knots, using each knot of the buoy digital rope as a common input end of a group of AND gate switch groups, sequentially connecting one bit of the fixed point number operand with the other input end of each AND gate in the gate group, and connecting the output end of the gate group with the input end of the arithmetic circuit; when the value of N is positive, the highest bit of the output end of the AND gate group is connected to the input port of the first N-bit arithmetic circuit, and the serial number of the highest bit in the first N bits is the same as the serial number of the buoy digital rope knot from the head end; when N is a negative value, the lowest position of the output end of the AND gate group is connected to the input port of the back N-position operation circuit, and the serial number of the lowest position in the front N position is the same as the serial number of the buoy digital rope knot extending from the tail end to the head end; when the N value is equal to m and is a positive value, the mth knot in the buoy digital rope is a real knot, the highest bit of the fixed point number operand enters the mth bit of the input end of the front N-bit operation circuit, the digits after the highest bit of the fixed point number operand sequentially enter the m bits of the front N-bit operation circuit and sequentially enter the rear N-bit operation circuit, when the N value is equal to m and is a negative value, the mth knot from the tail end in the buoy digital rope is a real knot, the lowest bit of the fixed point number operand enters the N-m bit of the input end of the rear N-bit operation circuit, and the fixed point operand sequentially enters the m bits of the rear N-bit operation circuit from the lowest bit and sequentially enters the front N-bit operation circuit;

the floating-point number conversion circuit converts data into an integer part and a decimal part, and the floating-point number conversion circuit is characterized in that: limiting the absolute value of the floating-point number order code to be N at most, wherein the floating-point number is composed of a sign, a mantissa, an order symbol and an order code, the data conversion of the floating-point number interface is to convert the floating-point number into an integer and a decimal, the integer is sent to the front N-bit addition and subtraction operation circuit, and the decimal is sent to the rear N-bit addition and subtraction operation circuit; the operation process of the floating-point circuit conversion is as follows: (1) aligning the most significant bit of the mantissa with the top of the next N-bit arithmetic circuit; (2) making the step code into a buoy digital rope; (3) each knot of the buoy digital rope and the step symbol jointly control a group of AND gate switch groups to perform parallel translation on the mantissas, the translation method is the same as that of the fixed point number, when the step code is a positive value, the mantissas translate towards the front N-bit operation circuit, and when the step code is a negative value, the mantissas translate backwards in the rear N-bit operation circuit;

the sign operation and control circuit is as follows: in the three interface circuits of addition and subtraction, each interface circuit is connected to the input end of the addition operation circuit and the input end of the subtraction operation circuit when M is detected, and the two AND gate switch group connection circuits are controlled by the sign operation circuit; when the signs of the two operands of the addition circuit are different, the sign operation circuit sends the two added operands to the subtraction circuit by controlling the AND gate switch group, the sign of the first operand is reserved, and the operation result of the subtraction circuit is subjected to sign operation to be used as the sign of the result number; when the signs are the same, the sign arithmetic circuit sends the two added operands into the addition arithmetic circuit by controlling the AND gate switch group, and the same signs are reserved as the signs in the output interface circuit; when the signs of the two operands in the subtraction are different, the sign arithmetic circuit sends the two operands into the addition arithmetic circuit by controlling the AND gate switch group, the sign of the first operand is reserved, and the arithmetic result of the addition circuit carries out sign 3 operation as the sign of the result number; when the signs are the same, the sign arithmetic circuit controls the AND gate switch group to send the two operands into the subtraction arithmetic circuit, the same signs are reserved, and sign arithmetic is carried out in the output result of the subtraction circuit to be used as the signs in the output interface circuit;

the addition or subtraction circuit for unsigned arithmetic is a single addition or subtraction circuit, and is different from the signed arithmetic circuit in that the interface circuit has fewer signed arithmetic circuits.

10. The application of the arithmetic circuit design method of an arithmetic unit as claimed in claim 1 in chip manufacturing, wherein the interface circuit for addition, subtraction, multiplication, reciprocal and division is an unsigned operation interface or a signed operation interface, and when the gas addition or subtraction operation is a signed operation, the output interface circuit is: because the addition operation and the subtraction operation are operations with signed operands, two addition operands may enter a subtraction operation circuit when being operated, two subtraction operands may enter an addition circuit when being operated, and the results of the addition operation and the subtraction operation can only be combined to the same output port;

(1) combining the output ports of the addition circuit and the subtraction circuit, wherein three sign operation circuits are arranged at three input ports of the addition and the subtraction, and two groups of AND gate switch groups are respectively controlled to be connected with the addition circuit or the subtraction circuit, so that the signal output ends of the addition circuit and the subtraction circuit controlled by the operation circuit of one addition operand input port are combined into 2 control signals by an OR gate, and the 2 control signals respectively control 2 AND gate switch groups of the output ports; the signal output ends of the arithmetic circuit control addition circuit and the subtraction circuit of the three subtraction operand input ports are combined into 2 control signals by an OR gate, and the 2 control signals 0 respectively control 2 AND gate switch groups of the output ports; in this way, the result of the addition and subtraction circuit operation is combined into an operation result through 4 and gate switch groups, and the combined operation result is a correct operation result no matter whether two addition operands or two subtraction operands are input by the input port or whether the addition operation circuit or the subtraction operation circuit is input; the port of the operation result of the addition circuit and the subtraction circuit after being combined by 4 AND gate switches is a combined port of an addition and subtraction operation output interface;

(2) the sign operation circuit of the output interface, the data that is outputted from the adder circuit to the merging port is unsigned data, the data that is outputted from the subtractor circuit to the merging port is signed data, therefore, the data of the merging port is a signed data, carry on the operation through the circuit again the sign of the first operand that the input port sign operation circuit keeps and the sign of the merging port, get the sign of the final result data;

(3) carry bit flag, the addition operation and signed subtraction operation have carry bit flag, the data output by the output interface must have carry bit flag;

(4) the data of the merging port is double N-bit data, the first N bits are an integer part, the second N bits are a decimal part, the double N-bit data are all output to be used as the integer and decimal output interface, and the CPU point needs what data to obtain;

(5) the fixed point number output interface converts the double N-bit data of the merging port into fixed point data, and the conversion method is as follows: firstly, taking a binary code with double N bits as a mental logical code, filling the knots to form a standard digital rope, then making 2N knots, wherein the number of the knots is N, subtracting the second standard digital rope from the first standard digital rope to obtain a buoy digital rope, and decoding the buoy digital rope to obtain the binary code which is the digit N of the fixed point number; when the operation is carried out, the back N bit is taken as a reverse digital rope, the reverse filling knot is made into a standard digital rope, and the standard digital rope is made into a buoy digital rope; when the operation result is positive, each knot of the buoy digital rope controls a group of AND gate switch groups to carry out data translation rightward, and after the translation, the highest numerical bit of the binary code is translated to the highest position of the last N positions, so that the fixed point number is formed by fixing the decimal point to the position before the highest numerical bit; when the subtraction operation result of the digital rope is negative, each knot of the buoy digital rope is used for controlling one group of AND gate switch groups to perform data translation, and the most numerical positions of the binary code after translation are translated to the highest positions of the last N positions, so that the fixed point number of the decimal point fixed to the most numerical position is formed; when the operation result of the digital rope is negative, each node of the buoy digital rope made of the last N bits controls one group of AND gate switch groups, the binary code of the last N bits is shifted to the left in parallel, the sign of the binary code decoded by the buoy digital rope of the last N bits is negative, and the number m of the binary code is the number of fixed points, so that the fixed points after the decimal point is fixed to the lowest value are formed;

(6) the floating point number output interface converts the double N bit data of the merging port into floating point data, and the conversion method is as follows: taking double N bits as a first digital rope, making the first digital rope into a standard digital rope by a method of filling real knots, making the standard digital rope into a buoy digital rope, simultaneously making a second standard digital rope with the number of 2N and the number of the real knots being N, subtracting the second standard digital rope from the first standard digital rope, and decoding the subtraction result to obtain a binary code as an order code, wherein the symbol is an order symbol; respectively controlling 2N groups of AND gate switch groups to move left in parallel by using 2N knots of a first buoy digital rope, moving the highest bit of binary data in a merging port to the highest bit of 2N bits by using the AND gate switch groups controlled by the real knots of the buoy digital rope, and forming the shifted double N-bit data into the mantissa of a floating point number;

the output interface circuit of the multiplication is an unsigned operation interface or an unsigned operation interface, which means that when the multiplication is unsigned operation, the input interface circuit is as follows: the multiplication operation has no requirement on the position of the operand decimal point, and can reserve the position of left shift or right shift of the binary code; in order to reduce the loss of calculation precision, binary codes are input into a multiplication circuit as much as possible, and an input interface is used for carrying out pin connection on operands or carrying out circuit conversion on the operands and then sending the operands into the multiplication circuit; when the operands are integers, the integer operands are fed directly into the multiplication circuit; when the operand is a floating point number, the mantissa of the floating point number is shifted to the left to be an integer, and the number of bits shifted to the left is subtracted from the order code to be reserved as the order code; the method for shifting the mantissa of the floating-point number to the left is as follows: putting the mantissa into a first digital rope with the knot number of N, manufacturing a standard digital rope by filling the knots, and manufacturing the standard digital rope into a buoy digital rope; making the step code into a second standard digital rope with the knot number of N through coding; when the order symbol of the floating point number is positive, the binary code decoded by the operation result of subtracting the second standard digital rope from the first standard digital rope is the order code, and the sign is the order symbol; when the order symbol of the floating point number is negative, the binary code decoded by the operation result of the first standard digital rope and the second standard digital rope is the order code, and the order symbol is negative; reserving the order code and the order symbol;

when the multiplication operation is signed operation, the input interface circuit of the signed operation is added with a sign operation circuit on the basis of the input interface circuit of unsigned operation, the added sign operation circuit compares the signs of two operands, the positive sign is taken when the signs are the same, and the negative sign is taken when the signs are different;

the multiplication output interface circuit is: an N-bit multiplication circuit, wherein the maximum number of bits of the output binary code is a 2N-bit integer; the output interface is provided with two output interfaces, wherein the first output interface is an integer output interface, the second output interface is a fixed point number output interface, and the third output interface is a floating point number output interface; when two operands input by the CPU from the input end through the integer multiplication instruction are integers, the result is fetched from the integer output interface; the integer output interface is directly communicated with the output interface of the multiplication circuit; when the fixed point number is input by the input port, outputting data from the fixed point number output port; the fixed point output port is used for making an integer binary code of a multiplication result into a fixed point through a circuit, adding a bit value reserved by a fixed point input interface of the multiplication input interface and a result bit value into a code number of a Tting symbol, and performing operation by using a magic logical code during the addition; when the input port inputs a floating point number, outputting data from the output port of the floating point number; the floating point number output port is used for making the binary integer into a floating point number, adding the order code of the floating point number and the order code and the order symbol reserved by the input port by a signed number, and operating by using a magic logical code during the addition; the operation flow of the multiplication output port is the inverse process of the operation flow of the multiplication input port;

when the multiplication operation is signed operation, the sign operation is carried out in the input interface circuit, and the sign flag bit is added to the output circuit interface;

the interface circuit of reciprocal operation is an unsigned operation interface or an unsigned operation interface, which means that when reciprocal operation is unsigned operation, the input interface circuit is as follows: setting the digit number of the reciprocal circuit as N digits, and when the reciprocal of the A number is required, the reciprocal circuit requires that the A number is an integer with N digits when entering an input port of the reciprocal circuit; the input interface circuit shifts the A number to become an integer with N digits and multiplies the integer by an inverse shift value; when the number a is an integer, assuming that the number a is further shifted by m bits with the number of bits N, the expression of a is: (Ax 2)^m)×2-^mThe method for inputting the integer at the input interface of the reciprocal circuit is to shift A left by m bits and then send the A bits into the reciprocal circuit, and reserve m; when the A number is a fixed point number with a decimal point fixed at the minimum bit of the numerical value, and the bit value is that the numerical value part is shifted left by m bits to make the numerical value part become an integer with N bits, and the integer is sent to a reciprocal circuit to reserve-N-m; when the number A is a fixed point number which is a decimal point and is fixed before the maximum bit of the numerical value, and the digit is N, the numerical value part is shifted to the left by m bits to enable the numerical value part to become an integer with the digit being N bits, and the integer is sent to a reciprocal circuit, and N-m is reserved; when the person is a floating point number, the order code with the symbol is d, the mantissa part is shifted to the left by N bits to enable the mantissa to become an integer with the number of bits being N, and the integer is sent to a reciprocal circuit, and d-N is reserved;

the output interface circuit of reciprocal operation is: the reciprocal operation is a × B =2^2NWith the proviso that when a is an integer and the number of bits is N, the final result of the reciprocal B of a number is: b = (1/A) × 2-^2N(ii) a When A is expressed as A = X2^yAnd X is an integer with a number of digits N, the final result of the reciprocal B of the number A is: b = (1/X). times.2-^2N-y(ii) a Obviously, y is A with three input interfaces reservedThe output binary integer value is multiplied by 2-^2N-yIs the actual value of the reciprocal circuit; the reciprocal circuit can be provided with two output interfaces, one is a fixed point number output interface with a decimal point fixed after a minimum numerical digit, and the other is a floating point number output interface; the fixed point number output interface after the decimal point is fixed at the minimum numerical digit is an integer value for directly outputting the operation result of the reciprocal circuit, and then subtracting the digit value reserved by the input port by-2 n to be used as the digit of the fixed point number; the floating point number output interface shifts the integer output from the output port of the reciprocal circuit to the left again, the highest bit shifted to the output integer is aligned with the highest bit of the output port, when the left shift digit is h, the floating point number is the order code of the floating point number by subtracting the value of the digit reserved by the input port from-2 n plus h, and the symbol generated in the operation of the order code is the order symbol.

Technical Field

The invention relates to an electronic device, in particular to an application of an arithmetic circuit design method of an arithmetic unit in manufacturing a chip.

Background

When the digital circuit is used for data processing, the high level is taken as 1, the low level is taken as 0, 1 or 0 is coded into binary codes, and arithmetic operation or logic operation is carried out through three basic logic relations of an AND gate, an OR gate and a NOT gate. In arithmetic operation, binary code addition operation is performed bit by bit, when two binary numbers of N bits are added, each bit operation must generate continuous carry upwards for many times, the total operation layer number is 0.5 XNx (N +1), and assuming that each operation layer needs 3 stages of circuits, the total circuit number of the addition operation is 1.5 XNx (N +1), 128-bit addition operation is performed, and the circuit number reaches twenty-five thousand stages. The multiplication of binary codes is essentially an addition, and the circuit number of the 128-bit multiplication is equivalent to the sum of N-bit addition circuit numbers, and the circuit number is about 300 or more than ten thousand. The division operation of the binary code is essentially a subtraction operation, and the circuit level number of N/N bits is larger than the circuit level number of multiplication operation of NxN bits. Obviously, if a computer uses a binary code hardware arithmetic operation circuit, the number of bits thereof must be large enough that arithmetic operation of all data can be performed by the hardware arithmetic circuit. When the number of bits of the hardware arithmetic circuit is sufficiently large, even 1+1 operation can be performed by a hardware arithmetic circuit having a large number of circuit stages. Therefore, the arithmetic operation of the computer is carried out by simulating or managing hardware by software, the binary data processing of human digit is lower than the arithmetic efficiency of a hardware arithmetic circuit by software simulation, but the arithmetic operation of different digits is integrated for statistics, and the arithmetic operation of software simulation is higher than the arithmetic efficiency of hardware. However, as long as the arithmetic operation is performed by using binary codes, carry and borrow must be generated, and the carry and borrow inevitably reduce the operation speed of the computer. At present, the huge computer with the highest operation speed in the world can only complete 5000 ten thousand floating point number arithmetic operation results with 64 bits per second.

Disclosure of Invention

In view of the above, the present invention provides an arithmetic circuit design method for an arithmetic unit, which can be applied to a chip for manufacturing the arithmetic circuit, and can effectively solve the problem of increasing the operation speed of a computer.

The purpose is as follows:

1. the method comprises the steps of establishing a rule of the multi-level mental arithmetic logic code, establishing a method for encoding and decoding the multi-level mental arithmetic logic code, establishing a method for translating a digital rope code into a real knot or a real knot section, establishing a standard digital rope and a buoy digital rope, establishing a digital rope group of the multi-level mental arithmetic logic code, establishing a skipping method of the multi-level digital rope group from a saturated digital rope to an unsaturated digital rope, and establishing a method for decoding the unsaturated digital rope. The schematic circuit diagram of the operational circuit is built by three basic logic elements of an AND gate, a NOT gate and an OR gate.

2. A method and a principle circuit for arithmetic operation of addition and subtraction of a mental logical code are established.

3. And establishing a digital rope group to carry out an operation method and a principle circuit of addition, subtraction, multiplication, reciprocal and division. Using the pseudocode to convert the subtraction of the magic logic code into an addition; the multiplication operation is changed into the addition operation of the digital rope code by a factorization method; the reciprocal operation is converted into an addition operation of a magic logic code by using a false code, and the division operation is converted into an addition operation of the magic logic code by multiplying the reciprocal of a divisor by a dividend.

4. The method comprises the steps of establishing an input interface and an output interface of an arithmetic circuit for addition, subtraction, multiplication, reciprocal and division, sending an integer, a fixed point number and a floating point number into operation through the corresponding input interfaces, and directly outputting an operation result in the integer, the fixed point number and the floating point number through an integer, the fixed point number and a floating point number output interface. The arithmetic operation is performed by selecting the corresponding interface input data and selecting the corresponding interface output data.

Accordingly, the technical scheme of the invention is that the arithmetic circuit design method of an arithmetic unit is applied to manufacturing a chip, and the arithmetic circuit design method of encoding and decoding a mental arithmetic logical code and adding, subtracting, multiplying and dividing reciprocal is applied to the chip instead of a binary algorithm, no carry or borrow occurs any more, and an operation result is decoded into a binary code, and the method specifically comprises the following steps:

(1) when the computer carries out arithmetic operation, the high level is 1 code, and the low level is 0 code; the mental logical code expresses a code 0 by a virtual knot, expresses a code 1 by a real knot, and expresses data by combining the real knot and the virtual knot; the knot number of one digital rope is the sum of the real knot number and the virtual knot number, and the numerical value expressed by one digital rope is equal to the sum of all the real knot numbers in the digital rope; the solid knots and the virtual knots in the digital rope can be combined and arranged at will, the solid knots are arranged from one end of the digital rope, all the digital ropes with the adjacent solid knots are standard digital ropes, and the numerical values are expressed by the standard digital ropes; the solid knot starting end of the standard digital rope is the head end of the digital rope, and the other end of the standard digital rope is the tail end of the digital rope; when the real knot or the real knot section in the digital rope does not take the head end of the digital rope as the starting end or possibly does not take the head end of the digital rope as the starting end, the real knot or the real knot section is translated to the head end of the digital rope; when two digital ropes are connected into a wholeWhen the standard digital rope is formed, firstly, two digital ropes are translated into the standard digital rope through a solid knot or a solid knot section, the two standard digital ropes are connected to form the digital rope, and then the standard digital rope is formed through translation of the solid knot or the solid knot section; when the real knots or the real knot sections and the virtual knots or the virtual knot sections of the digital ropes are mutually staggered, the digital ropes are regarded as a plurality of digital ropes, every four digital ropes are divided into a group and translated into one digital rope, and finally the digital ropes are combined into one standard digital rope; when a plurality of digital ropes are connected into one digital rope, every four digital ropes are divided into one group, each group becomes one digital rope after translation, then the four digital ropes are used as one group for translation, and after the digital ropes are translated into one digital rope, the last digital rope is translated into a standard digital rope; the mental arithmetic logical code coding is to convert the binary code into a standard mental arithmetic logical code through a circuit; the coding has three coding methods, the coding method 1 is to use two paths of phase and circuit phase by phase, respectively calculate all decimal numerical values, add the calculated number to the corresponding number rope knot, in the number rope, any one solid knot is filled into a solid knot to form a standard number rope; the coding method 2 is to use the multi-channel AND circuit to respectively calculate the decimal value, add the calculated number to the corresponding number rope knot, and fill all knots below the knot into a real knot as a standard number rope; the coding method 3 is to make each bit into a digital rope circuit, N digital ropes are provided as N binary numbers, the N digital ropes are connected into one digital rope, the N digital ropes are subjected to grouping translation real knot or real knot section, and finally a standard digital rope is obtained; replacing the real knot of the digital rope with a virtual knot from the head end, and only reserving the uppermost real knot, wherein the real knot is the buoy code of the digital rope, and the digital rope with the buoy code is the buoy digital rope; the digital rope decoding is to convert the buoy digital rope into binary code, and the method comprises the following steps: on the buoy digital rope, from the head end, the 1 st knot is connected to the binary 0 bit, the 2 nd knot is connected to the binary 1 bit, the 3 rd knot is connected to the binary 0 bit and the binary 1 bit, the 1 st knot is connected to the binary 3 bit, the 5 th knot is connected to the binary 0 bit and the binary 3 bit, and so on until all knots and binary are connected, then the isolation is carried out, so that each knot and each binary are isolatedOther nodes are in an isolated state; the digital rope addition operation is to connect two or more digital ropes into a new digital rope, the new digital rope is made into a standard digital rope, and the total number of real knots in the standard digital rope is the sum of the addition; in the arithmetic operation circuit, a port is led out from the 1 st knot of a standard digital rope converted from an operand, and the numerical value of the operand can be expressed to be 0 or not 0; the digital rope subtraction operation is to align the head ends of two standard digital ropes for comparison, and make the real knot difference value of the two digital ropes into a new standard digital rope by comparison, wherein the digital rope comparison has two methods, and the two methods can lead out a symbol mark port; one number can be expressed by one digital rope and also can be expressed by a group of digital ropes; when the number is expressed by the digital rope group, the digital ropes in the digital rope group form a stage, when the stage of the digital rope group is m, the numerical value expressed by each real knot in the first digital rope is 1, the numerical value expressed by each real knot in the second digital rope is m, and the numerical value expressed by each real knot in the third digital rope is m²The value expressed by each real knot in the jth digital rope is mj-¹(ii) a In the digital rope group, when the knot number of any one digital rope is not less than the series number of the group, the digital rope group is a digital rope group with saturated knots, and when the knot number of each digital rope is less than the series number of the group, the digital rope group is a digital rope group with unsaturated knots; the knotted unsaturated digital rope group can decode each digital rope into binary codes respectively, and the decoding results of each digital rope are combined after decoding to restore the binary codes; the knot saturated digital rope group decoding method comprises the steps of firstly converting m-grade digital rope groups into one digital rope with each real knot expression numerical value of 1, then decoding, or carrying out grade skipping or decoding through circuit operation to carry out grade skipping and knot reduction to enable the number of knots of each digital rope in the digital rope groups to be equal to the grade, then reducing the number of knots through parallel grade skipping of a plurality of digital ropes or reducing the number of knots through serial grade skipping of one digital rope by one digital rope to enable the saturated digital rope groups to be converted into unsaturated digital rope groups, and decoding by the unsaturated digital rope groups; the addition operation of the digital string is to convert two or more added operands into standard digital strings with the same number of stages and to convert two or more added operands into standard digital stringsCombining the standard digital ropes with the same number of stages into a new saturated standard digital rope group, combining two or more digital ropes with the same expression value in the digital rope group into a new standard saturated digital rope, enabling each digital rope in the digital rope group to be an unsaturated digital rope through the skipping reduction knot of the digital rope group, and decoding the unsaturated digital group to finish addition operation; when two binary operands A minus B and the result is a binary number C, the two operands are made into two digital rope groups, the operation of the two digital rope groups A and B consists of three parallel circuits, the first parallel circuit is that a digital rope group with a false code is used for subtracting the digital rope group with A and then is subjected to addition operation with the digital rope group with B, the second parallel circuit is that a digital rope group with a false code is used for subtracting the digital rope group with B and then is subjected to addition operation with the digital rope group with A, the third parallel circuit is used for comparing the two binary operands with the subtraction, the comparison result is used as a symbol mark of the subtraction operation, the two symbol marks control two AND gate switch groups, the AND gate switch group switches on the second circuit when A is larger than B, the first circuit is switched on when A is smaller than B, and the digital rope group obtained behind the AND gate switch group is subtracted; the whole process of the subtraction operation of the number 7 rope groups is as follows: a, B two binary numbers are made into two digital rope groups with the number of m;

(2) the circuit 1 performs the operation of subtracting the B groups of digital ropes from the false codes, and the circuit 2 performs the operation of subtracting the A groups from the false codes;

(3) the circuit 1 performs addition operation by using a digital rope group A and a result digital rope group of a false code minus digital rope group B, and the circuit 2 performs addition operation by using a digital rope B and a result digital rope of the false code minus digital rope A;

(4) the addition operation results of the circuit 1 and the circuit 2 respectively pass through the skipping code elimination of the digital rope group to enable the result digital rope group to be a saturated digital rope group with the same level number and knot number, then respectively pass through the small string skipping code elimination or the parallel skipping code elimination to enable the digital rope group to be an unsaturated digital rope group, the two unsaturated digital rope knots are respectively decoded to obtain two binary result codes, the carry in the result codes is omitted, two subtraction operation results are obtained, one result is a correct result, and the other result is an incorrect result;

(5) when the circuit 1 and the circuit 2 are operated, the binary numbers A and B are compared at the same time, the two binary numbers are used as two 2-level digital rope groups in the comparison process, two digital ropes with symbol bow marks are obtained by comparing the two digital rope groups, two symbol marks a and symbol marks B of A minus B are obtained by comparing the two digital ropes, the symbol mark a is used for controlling one group of AND gate switch groups of the connecting circuit 1, and the symbol mark B is used for controlling one group of AND gate switch groups of the connecting circuit 2;

(6) the output ports of the two AND gate switch groups are connected in parallel to obtain a subtraction result, and meanwhile, in a comparison circuit of binary numbers A and B, a subtracted number 0 and a subtracted number non-0 mark and a subtracted number 0 and a subtracted number non-0 mark are obtained through the circuit; the subtraction result data, the symbol mark, the subtracted number, the 0 and non-0 mark of the subtracted number form the subtraction operation together; the multiplication operation of the digital rope group is to make two multiplied operands into two 2-level digital rope groups, carry out factorization, add the factors of the same position into a digital rope, the multiplication operation of N times N bits has 2N-1 digital ropes to form a 2-level digital rope group, make each digital rope into a standard digital rope first, then make the digital rope group into an unsaturated digital rope group through skipping knot eliminating, then decode into binary code, wherein, there are two methods for making each digital rope in the digital rope group into a standard number, method 1 is to make each node in each digital rope in the C digital rope group as a digital rope, carry out real knot translation of the digital rope of the same level, and become a standard digital rope through multiple translation real knots or real knot sections; the method 2 is that each digital rope in the digital rope group is made into a standard digital rope in a parallel number finding mode; the reciprocal operation of the digital rope is that the digital rope B is taken as the reciprocal of the digital rope A, A, B is taken as a 2-level digital rope group when the reciprocal A of an N-bit binary number B is solved, and the condition that A times B is equal to 2 is assumed²ⁿEstablishing a digital rope group A for reciprocal operation by the inverse operation of multiplication operation, converting each digital rope in the digital rope group A for reciprocal operation from addition and subtraction mixed operation to addition operation, enabling each digital rope in the digital rope group for reciprocal operation to be a standard digital rope by the addition operation, enabling the saturated digital rope group for reciprocal operation to be an unsaturated standard digital rope by a skip reduction knot,then decoding into binary codes; the division operation of the digital rope group is to make dividend and divisor into two digital rope groups with 2 stages, firstly carry out reciprocal operation on the divisor, and then carry out multiplication operation on the result of the reciprocal operation and the dividend; the arithmetic operation circuit of the digital rope or the digital rope group carries out unsigned integer operation, only the front end of the unsigned integer arithmetic operation circuit is added with an input interface to carry out arithmetic operation on fixed point numbers, floating point numbers and symbolic numbers, and only the output interface is added after the arithmetic operation is carried out on the fixed point numbers, the floating point numbers and the symbolic numbers to ensure that a CPU obtains the operation result of the required integer numbers, fixed point numbers, floating point numbers or symbolic numbers; the interface circuit of the addition, subtraction, multiplication, reciprocal and division operation is an unsigned operation interface or a charpy operation interface; the input interface of an arithmetic operation circuit consists of parallel integer interfaces, fixed point number interfaces and floating point number interfaces, the three input interfaces are simultaneously connected to the input port of the arithmetic operation circuit through an AND gate switch group, and one of the interfaces is controlled by an operation instruction of a CPU to be switched on and operand is input from the interface; the fixed point number interface and the floating point number interface are provided with data conversion circuits, and the fixed point number and the floating point number are converted into integers meeting the requirements of the arithmetic operation circuit through the data conversion circuits: the signed arithmetic operation realizes the selection of an operation mode and the sign of output data in the input connection U and the output connection U through a sign operation circuit; the output end of the arithmetic operation circuit is connected with three output interfaces of integer, fixed point and floating point in parallel, the data output by the three output interfaces have different systems but the same numerical value, and the CPU can select any one output interface to fetch the data; in the interface circuit of arithmetic operation, the input interface circuit of addition, subtraction, multiplication, reciprocal, division operation circuit is three, the addition of output interface circuit, subtraction, multiplication circuit is three, the output interface circuit of reciprocal operation and division operation circuit is two; the input interface of the division operation circuit consists of a dividend input interface and a divisor input interface, the dividend input interface is the same as the input interface of the multiplication circuit, the divisor input interface is the same as the input interface of the reciprocal circuit, and the division output interface is the same as the output interface of the reciprocal circuitThe same is true.

The invention has few circuit stages, binary operands (integers, fixed point numbers and floating point numbers) are sent to an arithmetic circuit, binary operation results are output from the circuit, the circuit stages of addition and subtraction are less than 10 stages, the circuit stages of multiplication and reciprocal operation are less than 25 stages, and the circuit stages of division operation are less than 45 stages. The electronic elements used are few, the operation speed is high, the method can be integrated into a chip of a computer and a chip of a single chip microcomputer, a new way for manufacturing the chip is developed, the working efficiency of the computer is improved, and the economic and social benefits are huge.

Drawings

FIG. 1 is a flow diagram of the input interface of the add and subtract circuit of the present invention.

Detailed Description

The following detailed description of the embodiments of the present invention refers to the accompanying drawings.

In the specific implementation of the invention, the arithmetic circuit design method of the arithmetic device is applied to manufacturing chips, and when a computer carries out arithmetic operation, the high level is 1 code, and the low level is 0 code. The mental logical code expresses a code 0 by a virtual knot, expresses a code 1 by a real knot, and expresses data by combining the real knot and the virtual knot; the knot number of one digital rope is the sum of the real knot number and the virtual knot number, and the numerical value expressed by one digital rope is equal to the sum of all the real knot numbers in the digital rope; the knot number of the digital rope can be defined arbitrarily, and one digital rope can express a binary number and also can express one or more digits in the binary number; when a binary number is expressed by a digital rope, the data expressed by the digital rope is the sum of all real knots, the numerical value of each real knot is 1, and the number of the digital rope is 1; when a single number is expressed by a group of digital ropes, each digital rope in the group of digital ropes is used for respectively expressing one or more digits of the binary number ; when each digital rope in the digital rope group expresses one bit, the knot number in each digital rope can be defined at will, each digital rope from 0 bit is a first digital rope and a second digital rope in sequence till the ith digital rope, the numerical value of each real knot in the first digital rope is 1,the numerical value of each solid knot in the second digital rope is 2, the numerical value of each solid knot in the third digital rope is 4, and the numerical value of each solid knot in the ith digital rope is 2^m(i-1)The number of the digital rope is 2^mWhen each digital rope in the digital rope group expresses m bits respectively, the knot number in each digital rope can be defined at will, a first digital rope is arranged from 0 bit to m bits, a second digital rope is arranged from m bits to 2m bits, and the like are carried out until the ith digital rope, the numerical value of each real knot in the first digital rope is 1, and the numerical value of each real knot in the second digital rope is 2^mAnd each solid knot in the third digital rope is 2^2mThe value of each solid knot in the ith digital rope is 2^m(M)The number of the digital rope is 2^mThe real knots and the virtual knots in the digital rope can be randomly combined and arranged, the real knots are arranged from one end of the digital rope, all the digital ropes adjacent to the real knots are standard digital ropes, the starting ends of the real knots of the standard digital ropes are the head ends of the digital ropes, and the other ends of the real knots are the tail ends of the digital ropes; when the real knot or the real knot section in the digital rope does not take the head end of the digital rope as the starting end or possibly does not take the head end of the digital rope as the starting end, the real knot or the real knot section is translated to the head end of the digital rope; when a plurality of digital ropes at the same level are connected into a digital rope, firstly translating the solid knot or solid knot section in each digital rope into a solid knot section, and then translating the solid knot section of each digital rope into a standard digital rope taking the head end as the starting end; replacing the real knot of the digital rope with a virtual knot from the head end, and only reserving the rightmost real knot, wherein the real knot is the buoy code of the digital rope, and the digital rope with the buoy code is the buoy digital rope; encoding the mental arithmetic logic code is to encode a binary code into a standard mental arithmetic logic code; the digital rope decoding is to convert the buoy digital rope into binary code. The digital rope addition operation is to connect two or more digital ropes of the same level into a new digital rope, the new digital rope is made into a standard digital rope, and the total number of real knots in the standard digital rope is the sum of the addition; the digital rope subtraction operation is to make two standard digital ropes into a new standard digital rope, and the number of real knots in the new standard digital rope is the difference value of the number of the real knots in the two digital ropes. The digital rope can be used for adding and subtracting two source operands and a knotIf a 0 or non-0 flag is made, the addition circuit must have a carry flag and the subtraction circuit must have a sign flag. The addition operation of the digital rope group is to combine two or more standard digital ropes with the same level number into a new saturated standard digital rope group, the combination process is to combine two or more digital ropes with the same expression value in the digital rope group into a new standard saturated digital rope, and then each digital rope in the digital rope group becomes an unsaturated digital rope through the skipping reduction knot of the digital rope group; when the two digital rope groups A and B are subtracted, the subtraction operation consists of three parallel circuits, the first parallel circuit subtracts the A digital rope group from the false code digital rope group and then performs addition operation with the B digital rope group, the second parallel circuit subtracts the B digital rope group from the false code digital rope group and then performs addition operation with the A digital rope group, the second parallel circuit compares two subtraction binary operands, the comparison result is used as a symbol mark of the subtraction operation, two AND gate switch groups are controlled by the two symbol marks, the AND gate switch group switches on the second circuit when A is larger than B, the first circuit is switched on when A is smaller than B, and the subtraction result of the digital rope groups is obtained behind the AND gate switch group; the multiplication operation of the digital rope group is to convert the multiplication operation into addition operation by factorization; the reciprocal operation of the digital rope is that the digital rope B is regarded as the reciprocal of the digital rope A, and the result of multiplying A by B is equal to 2^2mEstablishing a multiplication relation, wherein 2n is a basic shift value of the reciprocal, solving the reciprocal B according to the inverse relation of the multiplication relation, obtaining a binary code by decoding after obtaining a reciprocal digital rope, and correcting the bit value of the basic shift bit and the A-number shift bit of the resulting binary code; the division operation of the digital rope is to firstly perform reciprocal operation on a divisor, multiply the result value of the reciprocal operation and the dividend, and perform basic shift correction on the multiplication result. The operands of the addition, subtraction, multiplication, reciprocal and division operations of the digital rope or the digital rope group are integers, and the front end of the arithmetic operation circuit is connected with an integer input interface, a fixed point input interface and a floating point input interface, so that the arithmetic operation can carry out the integer, fixed point and floating point operations, and simultaneously, the interface circuit can directly carry out the signed number operation; the rear end of the arithmetic operation circuit is connected with an output interfaceReceiving and outputting binary integers, fixed point numbers and floating point numbers; wherein the input interface of the addition and subtraction operation is; the input interface of the addition and subtraction operation is; the input interface of the multiplication operation is; the output interface of the multiplication operation is; the input interface of reciprocal operation is; the output interface of reciprocal operation is; the input interface of the division operation is; the output interface of the division operation is.

One, mental logical code and standard digital rope

The mental logical code is not a physical rope tied up as a code, but a logical relationship. The knot of the digital rope expresses that the point on the circuit is regarded as a knot, the point on the circuit is a virtual knot when a low level appears, the point on the circuit is a real knot when a high level appears, the low level is 0 code, the high level is 1 code, and the relation of a plurality of circuit points forms a logical digital rope relation. The digital ropes formed by points on the circuit reflect mathematical logic relations on the circuit, and conversely, the circuit can be formed by the mathematical logic relations of the digital ropes.

The mental logical code is only counted by real knots, and the numerical value expressed by one digital rope is the sum of the number of the real knots on the rope. The counting of the mental arithmetic logical code is started from one end, the real knots are continuous, the virtual knots cannot exist between the real knots, and the digital rope capable of counting is a standard digital rope. The standard magic logic code is that all the solid knots in the digital rope are adjacent to form a continuous solid knot section. The initial end of the solid knot section is the head end of the digital rope, and the other end of the solid knot section is the tail end of the digital rope.

A standard digital rope can only have one solid knot or solid knot section at most, and the starting end of the solid knot or solid knot section is necessarily at the head end. When the solid knots or the solid knot sections of the digital ropes are mutually staggered with the virtual knots or the virtual knot sections, only one solid knot or solid knot section exists in one digital rope by translating the solid knots or the solid knot sections; when the solid knot or the solid knot section in the digital rope may not take the head end as the starting end, the solid knot or the solid knot section is translated to the head end of the digital rope; when a plurality of digital ropes are connected into a digital rope, solid knots or solid knot sections in the digital ropes are translated into a solid knot section, and then the solid knot section is translated to one port of the digital rope to form the standard digital rope.

(II) translation of solid knots or solid knot segments on digital ropes

The encoding and decoding and arithmetic operation of the magic logic code must be a standard digital rope, and when the digital rope cannot be determined to be the standard digital rope, the real knot or the real knot section which may exist on the digital rope must be translated, so that the starting position of the real knot or the real knot section of the digital rope is at the head end of the digital rope.

Only one solid knot or solid knot section can be arranged in one digital rope, and when only one solid knot or solid knot section cannot be determined in one digital rope, the digital rope is regarded as a plurality of digital ropes to be subjected to solid knot or solid knot section combination, so that the digital rope is formed. The start end of the solid knot or solid knot section in the standard digital rope must be at the head end of the digital rope, and if the solid knot or solid knot section in one digital rope cannot be determined to be at the head end of the digital rope, the solid knot or solid knot section in the digital rope needs to be translated to the head end of the digital rope.

If two digital ropes are connected to form a digital rope, two solid knots or solid knot sections are possible in the digital rope, and if one solid knot or solid knot section can be determined to be at the head end of the digital rope, the other solid knot or solid knot section can be translated to form one solid knot section. If one solid knot or solid knot section cannot be determined to be at the head end of the digital rope, one digital rope can be made into a standard digital rope, and then the other solid knot section is translated; it is also possible to merge two solid knots or solid knot sections into one solid knot or solid knot section and then translate the solid knot or solid knot section to the head end of the digital rope.

When a plurality of digital ropes are connected to form a digital rope, the plurality of digital ropes are divided into groups, each group of digital ropes is translated into one digital rope through real knots or real knot sections, and then the real knots or the real knot sections of each group of digital ropes are translated until all the real knots or the real knot sections in the digital ropes are translated together to form a standard digital rope.

(1) A method of translating a solid knot or solid knot segment in a digital rope to the head end of the digital rope.

The number of the digital rope knots is set to be m, and the digital rope knots are 1,2,3,4 and 5. The translation method comprises the following steps: carrying out isolation translation on the 1,2,3,4,5.. i.. m knot by using a one-way conduction element, and connecting to the 1,2,3.. i.. m-1 knot of the digital rope after translation; the 2 knots are isolated and then translated to the head end of the digital rope, and the 2 knots are respectively connected with the 3,4,5,. i.m knots and then are respectively connected to the 2,3,4.. i.m-2 knots of the translated digital rope; the 3 knots are isolated and then translated to the head end of the digital rope, and the 3 knots are respectively connected with the 4,5,6. And performing phase comparison in sequence until the mth knot is isolated and then translating to the head end of the digital rope. Setting: m = 8.

(2) Method for connecting two standard digital ropes into one standard digital rope

The first method is to connect the head ends of two digital ropes to form a new non-standard digital rope, and then to make it into a standard digital rope by the translation of the internal knot or solid knot section of one digital rope.

The second method is to connect the head end of one standard digital rope with the tail end of another standard digital rope to form a new digital rope, wherein one solid knot or solid knot section is arranged at one end of the digital rope, the end is the head end of the digital rope, and the standard digital rope is formed by translating the solid knot or solid knot section in the rope. Setting: the number of one standard digital rope knot is m, and the standard digital rope knot is a from the head end₁,a₂,a₃,a₄...a_i..a_mThe knot number of the other standard digital rope is n and is b from the head end₁,b₂,b₃,b₄...b_i...b_nA knot is connected in a manner of b₁Terminal is connected to a_mAnd (4) an end. The translation method comprises the following steps: a is_1，a₂,a₃，a₄...a_i..a_mAfter isolation is c₁,c_2，c₃,c₄...c_i...c_m,b_1；b₂,b₃,b₄...b_i...b_nAfter isolation are respectively connected to c₁,c_2，c₃,c₄...c_i..c_mKnotting; with a₁Respectively and b_1；b₂,b₃,b₄...b_i...b_nAnd then are connected to c₂,c₃,c₄...c_i..c_mKnot ofThe end-most phase result is c_m+iKnot formation; with a₂Knot of each and b_1；b₂,b₃,b₄...b_i...b_nPhase and back are respectively connected to c_2，c₃,c₄...c_i..c_m,c_m+iThe phase at the extreme end of the junction is c_m+2Knot formation; with a₃Knot of each and b₁,b₂,b₃,b₄...b_i...b_nPhase and back are respectively connected to c₄...c_i..c_m，c_m+i,c_m+2The phase at the extreme end of the junction is c_m+3Knot formation; sequentially performing phase reaction until m junction is respectively subjected to phase reaction with b₁,b₂,b₃,b₄...b_i...b_nAnd the phase inversion is finished.

(3) The method comprises the steps of connecting four digital ropes into one digital rope and then manufacturing the digital rope into a standard digital rope.

When four digital ropes are connected into one digital rope, each digital rope is made into a standard digital rope, the head ends of the two middle digital ropes are connected to form one digital rope, the two digital ropes outside the digital rope are subjected to solid knot or solid knot section translation to form one digital rope, and then the digital rope is formed into the standard digital rope through the solid knot or solid knot section translation.

Setting: A. b, C, D are four digital cords, each digital cord having three knots. In the first step, each digital rope is translated into a solid knot or a solid knot section to become a standard digital rope. And secondly, connecting the head ends of the two middle digital ropes to form a digital rope. And thirdly, performing solid knot or solid knot section translation on the two outer digital ropes to the middle digital rope. And fourthly, making a standard digital rope.

(4) A method for connecting a plurality of digital ropes into one digital rope and then manufacturing the digital rope into a standard digital rope.

When a plurality of digital ropes are connected into one digital rope, every four digital ropes are divided into one group, and each group becomes one digital rope after translation. And then, the four digital ropes are used as a group to be translated until the digital ropes are translated into one digital rope, and then the last digital rope is translated into a standard digital rope.

For example: when 256 digital ropes are connected into one digital rope, the 256 digital ropes are converted into 128 digital ropes by the first-stage circuit, the 128 digital ropes are converted into 64 digital ropes by the second-stage circuit, and by analogy, the 256 digital ropes are converted into a standard digital rope through translation and need a 9-stage circuit.

Encoding method of mental logical code

And (IV) encoding the mental logical code, namely converting the binary code into the mental logical code through a circuit. The coding has three coding methods, the coding method 1 is that two paths of phase and circuit phase by layer are used for phase and circuit phase by layer, all decimal numerical values are respectively solved, the solved numbers are added to corresponding number rope knots, and in the number rope, any one solid knot is completely filled into a solid knot to form a standard number rope. The method 2 is to use the multi-phase and circuit to respectively calculate all decimal numbers, add the calculated numbers to the corresponding digital rope knots, and fill all knots below the knot into a real knot to form the standard digital rope. And 3, making each bit into a digital rope circuit, forming N digital ropes by N binary numbers, connecting the N digital ropes into one digital rope, and performing grouping translation real knot or real knot section on the N digital ropes to finally obtain the standard digital rope.

(1) Coding by two-way layer-by-layer phase-contrast method

The encoded binary is arranged from the lowest bit up to the 0 th bit and the 1 st bit. The 0 th bit is the 1 st knot of the digital rope after being isolated by the circuit, the 1 st bit is the 2 nd knot after being isolated by the circuit, the 3 rd bit is the 8 th knot after being isolated by the circuit, the ith bit is the 2 nd knot after being isolated by the circuitⁱAnd (6) knotting. Taking the phase of 0 and 1 as the 3 rd junction, taking the phase of 0 and 2 as the 5 th junction, taking the phase of 0 and i as the 2 nd junctionⁱ+1 junction; taking the phase of 1 and 2 as the 6 th junction, the phase of 1 and 3 as the 10 th junction, and the phase of 1 and i as the 2 nd junctionⁱ+2 junctions; until the i-1 bit and the i-bit are combined to form the first layer. Then, the second layer phase and the third layer phase are carried out until all the numerical values are completely calculated and expressed by the numerical knots. Then, any knot after the solid knot in the digital rope needs to be completely filledThe knot is solid. Examples are: the binary number is assumed to be four bits.

(2) Coding with a multipath phase and method

The code of the multi-path phase and is a two-stage circuit, the first and the second circuits calculate the numerical values expressed by all the digital knots by using the multi-path phase and phase method, and the second stage circuit fills all the knots after any one of the knots into a solid knot. Taking encoding of a four-bit binary number into a mental logical code as an example, a 0-bit is a 1-bit, a 1-bit is a 2-bit, a 0-bit and 1-bit phase is a 3-bit phase, a 2-bit is a 4-bit, a 0-bit and 2-bit phase is a 5-bit, a 1-bit and 2-bit phase is a 6-bit, a 0-bit, 1-bit and 2-bit three-phase is a 7-bit, a 3-bit 8-bit, a 0-bit and 3-bit phase is a 9-bit, a 1-bit and 3-bit phase is a 10-bit, a 0-bit, 1-bit and 3-bit three-phase is an 11-bit, a 2-bit and 3-bit phase is a 12-bit, a 0-bit, 2-bit and 3-bit three-phase is a 13-bit, a 1-bit, 2-bit and 3.

(3) Coding method by grouping and translating a plurality of digital ropes

The coding method for grouping, translating and knotting by using a plurality of digital ropes comprises the following steps: (1) each bit of the binary code is made into a standard digital rope. When each bit of the binary code is used as a standard digital rope, each standard digital rope is either all virtual knots or all real knots. The knot number of each 1 digital rope is the numerical value of the number of the digit, the knot number of the digital rope at 0 position is 1, the knot number of the digital rope at 1 position is 2, the knot number of the digital rope at 2 positions is 4, and the knot number of the digital rope at i position is 2^(i-1). (2) Translation is a solid combination and digital string. Every four digital ropes are combined into one digital rope by a primary circuit, the combined digital rope is made into a standard digital rope, and every four standard digital ropes are combined into one digital rope. And ending when the rope is combined into a standard digital rope. The circuit stage number is the digit of the binary code divided by 2, then the quotient is divided by 2, each division is a 1-stage circuit, and the quotient is 1. For example: the 128-bit binary number is encoded by a digital rope grouping translation method in the order of: the 1 st stage circuit combines 128 digital ropes into 32 digital ropes, the 2 nd stage 3 circuit combines 8 digital ropes, the 4 th stage 5 circuit combines 2 digital ropes, and the 6 th stage 7 circuit combines into a standard digital rope.

(IV) digital rope buoy

The digital rope buoy is formed by replacing the real knots of the standard digital ropes with the virtual knots and only keeping the top one. The method is that the ith junction is compared with the (i +1) th junction, the 1 st junction is converted into a virtual junction when the (i +1) th junction is a real junction, and the virtual junction of the ith junction can be reserved only when the (i +1) th junction is a real junction. There are 2 methods for logic circuits. The method 1 comprises the steps of performing phase comparison on the (i +1) th junction and the ith junction, and performing phase comparison on the phase comparison result and the ith junction after the phase comparison result is inverted by a NOT gate. Taking a 15-knot standard digital rope as an example, in the method 2, the i +1 th knot is inverted by a NOT gate and then is subjected to phase comparison with the i-th knot. Take 15 knots of standard digital rope as an example.

(V) digital cord decoding

Digital rope decoding is the conversion of mental logical codes into binary codes. The method comprises the following steps: on the buoy circuit of a digital rope, from the head end, the 1 st knot is connected to the 0 th bit of the binary code, the 2 nd knot is connected to the 1 st bit of the binary code, the 3 rd knot is connected to the 0 th bit and the 1 st bit of the binary code, the 4 th knot is connected to the 3 th bit of the binary code, the 5 th knot is connected to the 0 th bit and the 3 th bit of the binary code, and the like until all knots and the binary code are connected, and then isolation is carried out, so that each node and other nodes are in an isolation state. Take a standard digital rope of 15 knots as an example.

Six), digital rope addition method

The digital rope addition method is to encode two addition operands into two standard digital ropes through a circuit, connect the two standard digital ropes to perform real knot or real knot section translation to form one standard digital rope, and the standard digital rope is the sum of the two numbers. Namely: the addition of the two digital ropes is to combine the two digital ropes into a standard digital rope. The addition of the plurality of digital ropes is to combine the plurality of digital ropes into a standard digital rope.

In the addition circuit of two digital ropes, two added operands have 0 or non-0 flags, and the result has carry flags. The 0 or non-0 mark of the operand is two circuit ports led out from the head ends of the two encoded standard digital ropes, the two ports are respectively 0 or non-0 marks of the two operands, when the port is 0, the operand is 0, and when the port is 1, the operand is not 0. The carry flag bit is the carry flag bit at the top of the decoded result circuit, and when the addition circuit is two binary codes with N bits, the N +1 th bit of the result binary code is the carry flag.

The whole process of addition is as follows: and coding the binary code into a standard mental logical code, adding the code, making the added standard digital rope into a buoy, and decoding and restoring the standard digital rope into the binary code by using the digital rope buoy.

(VII) digital rope subtraction method

The digital rope subtraction is to make two operands of a subtracted number and a subtracted number into two standard digital ropes A and B respectively through circuit decoding, and align the head ends of the two standard digital ropes for comparison. Setting: the knot serial numbers of the two subtracted standard digital ropes from the head end are respectively a_1，a₂,a₃，a₄...a_i..a_mAnd b₁,b₂,b₃,b₄...b_i...b_nThe number of the difference digital rope is c₁,c_2，c₃,c₄...c_i...c_mA handle₁In the same way as b₁Performing NAND operation, and respectively obtaining the same result as a_1，And b₁And obtaining two operation results by phase inversion or obtaining the node c of the digital rope_i. And (3) making the digital rope C into a standard digital rope, then making the standard digital rope into a buoy digital rope, decoding the buoy digital rope to obtain a binary code, and leading out a symbol mark port from the arithmetic circuit. The method 2 is characterized in that: a is₁After being turned over by NOT gate, the leaf and the leaf are connected with each other₁And a result obtained, b₁After turning over by NOT gate, the same as a₁Phase-and-joining to obtain one result, and then re-phase the two results or obtaining the node c of the digital rope₁. And (3) making the digital rope C into a standard digital rope, then making the standard digital rope into a buoy digital rope, decoding the buoy digital rope to obtain a binary code, and leading out a symbol mark port from the arithmetic circuit. Method 1 is to subtract in the circuit of method 1 at a₁In the same way as b₁Performing NAND operation, and the operation result is identical to a₁The result of the AND operation is led out of port A at a₁In the same way as b₁Performing a NAND operation, and repeating the operation resultIn the same way as b₁Leading out the port B after the phase comparison result is obtained, and isolating the led-out port; method 2 is to subtract in the circuit of method 2 from a₁After being turned over by NOT gate, the leaf and the leaf are connected with each other₁The result of the AND is led out of port B, from B₁After turning over by NOT gate, the same as a₁Leading out the port A after the result of the AND, when A is 1, B must be 0 until the symbol; when B is 1, A must be 0 and the sign is negative. When A, B are 0 at the same time, the two subtracted operands are equal.

In the digital rope subtraction, there are also the 0 or non-0 flags of the two operands being subtracted and the subtraction, and the 0 or non-0 flag mentally disturbed of the result. Two operands may be compared by a sign flag, a 0 or non-0 flag of the operand, a 0 or non-0 flag of the result.

The whole process of the subtraction is as follows: the binary code is coded into A, B two standard digital ropes, the rope codes are compared, the compared result is translated into a real knot or a real knot section to become the standard digital ropes, the standard digital ropes are made into buoys, and the digital ropes are decoded and restored into the binary code.

(eighth), digital rope group and digital rope group stage

One number can be expressed by one digital rope and also can be expressed by a group of digital ropes. When a binary number is expressed by the digital rope set, the digital ropes in the digital rope set have grades. When the level of the digital rope group is m, the numerical value expressed by each real knot in the first digital rope is 1, the numerical value expressed by each real knot in the second digital rope is m, and the numerical value expressed by each real knot in the 4 th digital rope is m²The value of each real knot in the jth digital rope is m-^M ₀When a number is expressed by a number string set, m must be greater than 1. If the level m = i of the digital rope, the digital ropes are combined into one digital rope.

In a digital rope group, when knot number in every digital rope all is less than the progression of this group, this group of digital rope is knot unsaturated digital rope group, and knot unsaturated digital rope group can distinguish each digital rope and decode, and the decoding result that merges every digital rope after the decoding just reduced into a number.

In a digital rope set, when any one is in useWhen the knot number of the digital rope is not less than the stage number of the group, the group is the digital rope group with saturated knots. The method 1 is to convert the digital rope group with saturated knots into the digital rope group with unsaturated knots, decode each digital rope in the digital rope group with unsaturated knots respectively, and arrange the binary codes decoded by each digital rope in sequence; the method 2 is to combine the digital ropes into one digital rope with the number of stages being 1, and directly decode the digital rope with the number of stages being 1. The decoding play is realized by two steps by using the method 1, wherein the first step is that the knot number of each digital rope in the digital rope group is reduced through skipping, so that the knot number of each digital rope is smaller than or equal to the number of the digital rope group, and the number of the knots of each digital rope is equal to the number of the knots by increasing virtual knots; and the second step is that the saturated digital rope group with the knot number equal to the number of stages is made into an unsaturated digital rope group through skipping, each digital rope in the unsaturated digital rope group is decoded into a binary code, and the decoded binary code is arranged according to the sequence of each digital rope. Method 2 is to convert the digital rope group with saturated knots into a digital rope with the number of stages 1, and each knot in the ith digital rope is expanded into m during conversion^i-1And (4) knotting, namely forming a standard digital rope by translating the solid knots or the solid knot sections, and then decoding the first-level standard digital rope.

Method for reducing knot number of each digital rope in saturated digital rope group to be equal to stage number

There are two methods for reducing the number of knots of each digital rope in the saturated digital rope group to be equivalent to the number of steps. The method 1 is to skip stages through circuit operation, and reduce the knot number of the digital ropes layer by layer until the knot number of each digital rope is equal to the stage number. And 2, reducing the knot number of the digital ropes layer by decoding and skipping the grades until the knot number of each digital rope is equal to the grade number.

Method 1 for stage skipping by circuit operation:

each digital rope in the digital rope group is a standard digital rope, the number of the digital rope group is m, m is larger than i, and the knot number of at least one digital rope in the digital rope group is larger than m.(i) Making each digital rope in the digital rope group into a standard digital rope, and jumping up to the (i +1) th digital rope from the mth knot in the ith digital rope²The knot jumps up to the (i + 2) th digital rope, the m th³Skip upward to the i +3 th digital rope. (2) And comparing whether the skip-level junction is a solid junction or not. If m is¹When the knot is a real knot, all knots smaller than j are arranged into a virtual knot, and skip points smaller than j are also arranged into a virtual knot. (3) And reserving the number of junctions without the skip stage in front of the skip stage junction. When x skip level points are arranged in one digital rope, y skip level knots are arranged, the y skip level knot is a real knot, the knot after the y skip level knot is a T-jump level, the knot above the y +1 knot is a virtual knot, the knot after the y +1 knot and before the y knot can be a real knot and has no skip level, and the knot after the y +1 knot and before the y knot is reserved with K. If all skip level junctions are dummy junctions, the junctions after the first skip level junction remain. (4) The remained knots and the knots on the skipping step are made into a standard digital rope by moving the solid knots or the solid knot sections. (5) When the knot number of the digital rope is n, the maximum jumping stage number is h, n-h>m, performing parallel skipping on the parts above the digital rope; and if the nodes remained after the parallel stage skipping can still skip the stage, the parallel stage skipping is carried out again until no nodes remained can skip the stage. (6) And repeating the steps until the knot number of each digital rope in the digital rope group is equal to the number of stages.

Examples of the method are: the number of the digital rope group is 2, 8 digital ropes are provided, the number of the first digital rope is 1, the number of the 2 nd digital rope is 2, the number of the 3 rd digital rope is 3, the number of the 4 th digital rope is 4, the number of the 5 th digital rope is 5, the number of the 6 th digital rope is 6, the number of the 7 th digital rope is 6, the number of the 8 th digital rope is 8, and the 8 digital ropes are all standard digital ropes.

Method 2 for level hopping by decoding:

the method for decoding the skip level comprises the following steps: (1) decoding each digital rope in the digital rope group into a binary code, and determining a grade skipping point according to the grade number of the digital rope group. When the number of the digit group is 2, the number is released by the ith digit ropeAfter the code is a binary code, the 0 th bit does not skip, the 1 st bit skips to the (i +1) th digital rope, the 2 nd bit skips to the (i + 2) th digital rope , the 3 rd bit skips to the (i + 3) th digital rope, and the j th bit skips to the (i + j) th digital rope. When the number of stages of the digital rope group is 4, after the ith digital rope is decoded into a binary code, the 0 th bit and the 1 st bit do not skip stage, the 3 rd bit skips to the (i +1) th digital rope, the 4 th bit skips to the (i +1) th digital rope with 2 nodes, the 5 th bit skips to the (i + 2) th digital rope, the 6 th bit skips to the (i + 2) th digital rope with 2 nodes, and the 7 th bit skips to the (i + 3) th digital rope. When the number of the digital rope group is m and m is a multiple of 2, after each i digital ropes are decoded into binary codes, the bits smaller than m are reserved, the bits equal to m jump into the (i +1) th digital rope, and the bits equal to A multiplied by m (A is larger than 1 and A multiplied by m is smaller than m²) From A nodes to the (i +1) th digital rope, equal to m²Bit skipping to the second: i +2 digital ropes, equal to Axm²Is greater than 1 and A x m is less than m³) From the A node to the i +2 number rope , and so on, which is equal to mⁱIf the number of the digital rope group is 2, the reserved 0 th binary code is also the digital rope and is directly made into the standard digital rope without decoding, and then the above steps are repeated (3) until each digital rope in the digital rope group is reduced to the number of the steps equal to the number of the knots.

Examples of the method are: the number of the digital rope group is 2, 4 digital ropes are provided, the number of the first digital rope knot is 10, the number of the 2 nd digital rope knot is 9, the number of the 3 rd digital rope knot is 5, the number of the 4 th digital rope knot is 3, and the four digital ropes are all buoy digital ropes.

Method for converting digital ropes with number of stages equal to number of knots into knotted unsaturated digital ropes

When the knot number of each digital rope in the digital rope group is equal to the number of the steps, the unsaturated digital rope is formed as long as the knot number in each digital rope is reduced by one knot. Two methods are used for reducing one knot, wherein the method 1 is to reduce the knot in the digital rope group by a parallel skipping method; method 2 is to serially skip the grade reducing knot one by one digital rope.

Method 1 parallel skipping method for reducing knot of digital rope

When the digital rope group has m levels, each digital rope in the digital rope group is m knots. And each digital rope is made into a buoy digital rope, and the mth knot of each digital rope is an upward skip knot. The parallel skipping stage is that the mth knot of each digital rope skips upwards in parallel, and the mth knot of the ith digital rope skips to the (i +1) th digital rope and all the digital ropes above the (i +1) th digital rope in parallel skipping stage. After parallel skipping, each digital rope in the digital rope group keeps all knots below the (m-2) th knot and the (m-2) th knot, the number of the reserved knots is smaller than the number of the digital rope group, each digital rope is directly decoded into binary system, and binary codes decoded by each digital rope in the digital rope group are sequentially arranged to form the binary system expressed by one digital rope group.

The method for skipping the ith knot of the ith digital rope to the (i +1) th digital rope and all the digital ropes in the ratio of 1: simultaneously comprises the steps of forming a1 st phase and circuit by the mth knot of the ith digital rope and the m-1 th knot of the (i +1) th digital rope, forming a2 nd phase and circuit by the mth knot of the ith digital rope, the (i +1) th digital rope and the m-1 th digital rope of the (i + 2) th digital rope, forming a3 rd phase and circuit by the mth knot of the ith digital rope, the (i +1) th digital rope, the (i + 2) th digital rope and the m-1 th digital rope of the (i + 3) th digital rope, and so on, and forming an n-i phase and circuit when n digital ropes exist in a digital rope group. In the n-i phase AND circuit, the result of the j +1 phase AND circuit is inverted by an NOT gate and then is ANDed with the result of the j phase AND circuit again to a back jump stage in the i +2 digital rope. And the method for skipping to the (i +1) th digital rope is that the result of the (1) th phase AND circuit is inverted by a NOT gate and then is respectively subjected to phase comparison with the m knot of the (i) th digital rope and the m-1 knot of the (i +1) th digital rope. The phase of the (n-1) th phase and the circuit is the phase of a new digital rope in the digital rope group, and the phase is directly and mutually matched with the last digital rope in the original digital rope group.

Examples of the method are: the number of the digital rope group is 2, the digital rope group is composed of 8 digital ropes, the knot number of each digital rope is 2, and each digital rope is a buoy digital rope. Because the stage number of each digital rope is 2, only 1 jump stage node is reserved after parallel jump stage, and the mental logical code of one node is also a binary code, the parallel jump stage circuit with 2 nodes does not need to decode to form the binary code.

Method 2, grade-skipping reducing method for digital rope series by series

Setting: the number of stages of the digital rope group is m, and the knot number of each digital rope is equal to m. The number rope group has n number ropes.

The serial skipping stage-by-stage reduction and conversion method of digital ropes into unsaturated digital rope sets comprises the following steps_：And each digital rope in the digital rope group is made into a standard digital rope. (1) The m knots of the first digital rope jump into the 2 nd digital rope. When the m knots are real knots, the mediated knot of the first digital rope is a virtual knot, and the virtual knot is decoded into a binary code; when the m knots are virtual knots, the m-1 knots and knots below the m-1 knots are reserved, the reserved knots are made into a buoy digital rope, and then a binary code is decoded; (2) the m knots of the 2 nd digital rope and the i knots jumped in by the first digital rope are made into a standard digital rope with m + i knots, and the m knots of the second digital rope are jumped in the second digital rope. When the m knot is a real knot, only the (m +1) th knot is reserved, and one reserved knot is decoded into a binary code; when the m knots are virtual knots, the m-1 knots and knots below the m-1 knots are reserved, the reserved knots are made into a buoy digital rope, and then a binary code is decoded; similarly, the m knots of the ith digital rope and the i knots jumped into the (i-1) th digital rope are made into a standard digital rope with m + i knots, and the m knots of the ith digital rope are jumped into the (i + i) th digital rope. When the m knot is a real knot, only the (m +1) th knot is reserved, and one reserved knot is decoded into a binary code; when the m knots are virtual knots, the m-1 knots and the knots below the m-1 knots are reserved, the reserved knots are made into a buoy digital rope, and then the buoy digital rope is decoded into a binary code.

The circuit operation method for converting the serial skip stage reduction knot of the digital ropes into unsaturated digital ropes comprises the following steps: and (4) taking the m knots of each digital rope in the digital rope group as skip-level knots. Making the part below the m-1 knot into a buoy digital rope, and decoding the buoy digital rope into a binary code; decoding the m +1 knot into a binary code; the m-junction is turned over by the NOT gate and then used as an AND gate switch to control two groups of binary codes.

In the method, for example 1, the number of the digital rope groups is 2, the digital rope groups are composed of 5 digital ropes, the knot number of each digital rope is 4, and each digital rope is a standard digital rope.

Example 2 of the method includes: the number of the digital rope group is 2, the digital rope group is composed of 7 digital ropes, the knot number of each digital rope is 2, and each digital rope is a standard digital rope.

(ten), addition of digital cord sets

A binary code is expressed by a digital rope group, each digital rope in the group can express a one-bit binary code, a two-bit binary code, a three-bit binary code and an arbitrary-bit binary code. When each digital rope expresses a one-bit binary code, the number of the digital rope group is 2, and a knot is arranged in the unsaturated digital rope group; when each digital rope expresses a two-bit binary code, the number of the digital rope groups is 4, and one unsaturated digital rope has 3 knots; when the three-bit binary code is expressed, the number of the digital rope group is 8, and 7 knots are arranged in the unsaturated digital rope group; when expressing the four-digit binary code, the number of the digital rope group is 16, and 15 knots are arranged in the unsaturated digital rope.

The method for adding the digital rope group comprises the following steps: two digital rope groups of the same level are added, each digital rope in each group is made into a standard digital rope through a circuit, two standard digital ropes with the same digital knot expression value in the two digital rope groups are connected, the connected digital ropes are made into standard digital ropes, and then the two groups of unsaturated digital rope groups are converted into a group of saturated digital rope groups. The saturated digital string is the sum of the two digital string additions. The digital rope group is subjected to subtraction knot operation and decoding operation, so that binary codes are operated through the digital rope group.

(1) For example, 1: two 8-bit binary codes are made into two groups of 2-level digital ropes.

Setting: two binary code slaveThe code sequence from the low order to the high order is: a1, a₂，a_:3,a₄,a₅,a₆,a_7，a8，b1,b₂,b₃,b₄,b₅,b₆,b₇,b₈The two binary codes can be directly used as two 2-level digital rope groups. Each digital rope of the digital rope group is respectively a1+ b1, a₂+a₂,......a8+b₈After addition, each digital rope has two knots, the number of the grades is equal to the number of the knots, each digital rope is made into a standard digital rope, the standard digital rope is made into a buoy digital rope, and the addition result of the binary codes is obtained by performing parallel grade skipping and knot eliminating decoding on the buoy digital rope.

(2) Example 2 two 8-bit binary codes are made into two groups of 2-level digital rope addition operations.

Subtraction of (twelve) digital rope sets

Two binary operands of the subtraction operation are made into two digital rope groups with the number of stages not less than 2, and the digital ropes corresponding to the sequence in the digital rope groups are used for the subtraction operation. In the subtraction operation process of the digital rope group, when the result of subtracting the digital rope group B from the digital rope group A is the digital rope group C, each digital rope in the digital rope group C has different symbols, the digital rope group C needs to be subjected to unified symbol operation again, and the operation process is complex. To simplify the operation, the subtraction operation is made an addition operation by adding a dummy code. The method for adding the false code is to compare the values of the A, B operands and select the number string with a large value to add the false code. Setting: when B is greater than A, the carry bit of the operational circuit is first subtracted by A, and the result is then added by B. When A is equal to B, the subtraction result is set to 0, and no operation is performed. The mathematical expression is as follows:

a > B and a-B = C, a-B = a + (X-B) = X + C:

b > A and A-B = C, A-B = - [ B + (X-A) ] = - (X + C)

When increasing the false code to operate, the carry bit is cut off in the result digital rope group, and the operation result with positive and negative sign marks is obtained. And (4) skipping and code eliminating are carried out on the result digital rope, and then the result digital rope is decoded into a binary code, so that a subtraction result is obtained.

The circuit method for realizing the subtraction operation of the digital rope group comprises the following steps: the subtraction operation circuit is divided into three circuits, wherein the circuit 1 is the operation of adding a carry bit to subtract a B digital string group from an A digital string group; circuit 2 is the operation of adding the carry bit minus a digital string to the B digital string, and circuit 3 is the operation of A, B two digital strings comparing the value to get the symbol mark. In the circuit 3, when the sign of A is 1, A is larger than B, and when the sign of B is larger than 1, B is larger than A. Two sets of AND gate switches are controlled by the sign flags of A and B, respectively, the result of circuit 1 is derived and used as the subtraction result when the sign of A is 1, the result of circuit 2 is derived and used as the subtraction result when the sign of B is 1, and the subtraction result is 0 when A, B is 0 at the same time.

The number string group made by the carry bit is the same as the number string group of the operand, and the number of the number strings in the number string group is the same. When the number of stages of the digital rope group is m, the real knot number of the first digital rope in the carry digit digital rope group is equal to the number of stages, and the real knot number of each digital rope of the second and above digital ropes is m-1. Assuming that the number of stages is 2, the first digital rope in the carry digit rope group has 2 real knots, and the second and above digital ropes have 1 real knot. Assuming that the number of stages is 4, the real knot number of the first digital rope in the carry digit rope group is 4, and the real knot number of the second and above digital ropes is 3.

A method for pseudocode usage. Setting; by subtracting two binary numbers A, B, the code order of A number from lower to higher is a_1,a₂,a₃,a₄…，a_nThe code sequence of the B number from the low order to the high order is B1, B₂，b₃,b₄...，..b_n. When A, B is made into the subtraction of two digital rope sets with the number of stages 2, the mathematical expression after the addition of the false carry bit is that the first result digital rope is a₁+ (2-b1) and the second result number string is a₂+(i-b₂) The ith result number string is- [ b1+ (1-a)₁)]The nth result number string is [ b ]_n+(1-a_n)]。

The method for comparing the two binary numbers A and B is that A, B two binary numbers are directly used as two 2-level digital rope groups, when A and B two digital rope groups are compared, a digital rope is formed by the symbol marks of A, a digital rope is formed by the symbol marks of B, the two digital ropes formed by the two symbol marks are respectively filled and actually combined into two standard digital ropes, and then the two digital ropes combined by the two symbol marks are compared to obtain the symbol mark mentally disturbed a and the symbol mark mentally disturbed B. The symbol flag a and the symbol flag b can only have one symbol as 1, and the two symbol flags can be 0 at the same time but cannot be 1 at the same time. If a is 1, A is larger than B, if B is 1, B is larger than A, and if a and B are both 0, the two numbers A and B are equal.

Two binary numbers are compared for example:

the whole process of the digital rope group subtraction operation is as follows: when two binary operands A are subtracted: b, the whole process of the digital rope group subtraction operation is as follows: (1) a, B two binary numbers are made into two digital rope groups with the number of m; (2) the circuit 1 performs the operation of subtracting the B groups of digital ropes from the false codes, and the circuit 2 performs the operation of subtracting the A groups from the false codes; (3) the circuit 1 performs addition operation by using a digital rope group A and a result digital rope group of a false code minus digital rope group B, and the circuit 2 performs addition operation by using a digital rope B and a result digital rope of the false code minus digital rope A; (4) the addition operation results of the circuit i and the circuit 2 respectively pass through the skipping code elimination of the digital rope group to enable the result digital rope group to be a saturated digital rope group with the same level number and knot number, then respectively pass through the serial skipping code elimination or the parallel skipping code elimination to enable the digital rope group to be an unsaturated digital rope group, the two unsaturated digital rope groups are respectively decoded to obtain two binary result codes, the carry bit in the result codes is omitted, two subtraction operation results are obtained, one result is correct data, and the other result is wrong data. (5) When the circuit 1 and the circuit 2 are operated, the binary numbers A and B are compared at the same time, the two binary numbers are used as two 2-level digital rope groups in the comparison process, the two digital rope groups are compared to obtain two digital ropes with symbol marks, the two digital ropes are compared to obtain two symbol marks a and symbol marks B of A minus B, the symbol mark a is used for controlling one group of AND gate switch groups of the connecting circuit 1, and the symbol mark B is used for controlling one group of AND gate switch groups of the connecting circuit 2. (6) The output ports of the two AND gate switch groups are connected in parallel to obtain the subtraction result. When M is in time, in the comparison circuit of binary numbers A and B, the circuit can obtain the flag of the subtracted number 0 and the non-0, and the flag of the subtracted number 0 and the non-0. The subtraction result data, the symbol mark, the subtracted number, the 0 and non-0 marks of the subtracted number jointly form the result of the subtraction operation.

The whole process of binary subtraction is exemplified by 1, two 4-bit binary codes A minus B, where A is: al, a2, a3, a4, the binary code B is bl, B2, B3, B4, and serial skip erasure code is used.

The whole process of binary subtraction is exemplified by 2, two 4-bit binary codes A minus B, where A is: al, a2, a3, a4, binary code B bl, B2, B3, B4, with parallel skip cancellation.

Multiplication of digital rope sets

Two binary multiplication operands A, B in the multiplication operation are respectively used as two sets of number ropes with the number of 2, and then the factorization is carried out. Setting: the code sequence of A number from low order to high order is a_1，a₂,a₃,a₄...a_i...a_nThe code sequence of the B number from low order to high order is B_1，b₂,b₃,b₄...,b_i..b_nThe factorization results are as follows:

a_nb₁a_n-lb_l...a_ib_l...a₄b_la₃b_la₂b_la₁b_l

a_nb₂a_n-lb₂…a_ib₂…a₄b₂a₃b₂a₂b₂a₁b₂

a_nb₃a_n-lb₃…a_ib₃…a₄b₃a₃b₃a₂b₃a₁b₃

a_nb₄a_n-lb₄…a_ib₄…a₄b₄a₃b₄a₂b₄a₁b₄

……

a_nb_ia_n-lb_i…a_ib_i…a₄b_ia₃b_ia₂b_ia₁b_i

……

a_nb_na_n-b_n…a_ib_n…a₄b_na₃b_na₂b_na₁b_n

c_nc_n-1c₄c₃c₂c₁

when the result of multiplying the A digital rope group by the B digital rope group is a C digital rope group, the first digital rope of the C digital rope group is C₁,

The second digital rope is c₂The 3 rd digital rope is c₃The ith number rope is c_iThe n-1 number rope is Cn-1

The nth digital rope is a skipping-level digital rope and comprises:

c₁= a₁b_l；c₂= a₂b_l+a₁b₂；C₃= a₃b_l+a₂b₂+a₁b₃；c₄= a₄b₁+a₃b₂+a₂b₃+a₁b₄；……

c_i= a_ib₁+a_i-1b₂+a_i-2b₃...+a₄b_i-4+a₃b_i-3+a₂b_i-1+a₁b_i……

C_n= a_nb₁+a_n-1b₂+a_n-2b₃+a_n-1b₄...+a_ib_i...+a₄b_n-3+a₃b_n-2+a₂b_n-1+a₁b_n

C_n+1=a_nb₂+a_n-1b₃+a_n-2b₄...+a_ib_i...+a₅b_n-3+a₄b_n-2+a₃b_n-l+a₂b_n

C_n+2=a_nb₃+a_n-1b₄+a_n-2b₅...+a_ib_i...+a₅b_n-2+a₄b_n-1+a₃b_{n ……}

c_n-3=a_nb_n-2+a_n-lb_n-1+a_n-2b_n

c_n-2= a_nb_n-1+a_n-lb_n

c_n-1=a_nb_n

the multiplication operation of the digital rope group is to combine each digital rope C in the C digital rope group_iAnd making a standard digital rope, making the standard rope into a buoy digital rope, carrying out level skipping code elimination, making the number of knots of each digital rope in the digital rope group not more than 2 after several times of level skipping code elimination, and then converting the operation result expressed by the C digital rope into binary code data through parallel level skipping decoding.

Two methods are available for making each digital rope in the C digital rope group into a standard digital rope, wherein the method 1 is to take each factorized node in each digital rope in the C digital rope group as a digital rope, perform solid knot translation of digital ropes at the same level, and form a standard digital rope by translating solid knots or solid knot sections for multiple times; the method 2 is that each digital rope in the C digital rope group is made into a plurality of or a 2-level standard digital rope once by a parallel number finding mode, and the plurality of or one standard digital rope is subjected to level skipping code elimination until the digital rope is finally decoded into a binary code.

The method for parallel number finding to be the standard digital rope is that when an number of knots is in one digital rope, aj knots in the an knots are assumed to be real knots. Performing a common operation on the an junctions through a circuit, wherein when aj is equal to an, the result of the common operation is 1, when aj is smaller than an, the result of the common operation is 0, and the result of the common operation is used as a bn junction of the standard digital rope; taking an-l incompletely identical knots from the an knots, performing parallel and operation through a circuit, connecting the results of the parallel and operation together in parallel, wherein the result of the parallel and operation is 1 when aj is greater than or equal to an-1, the result of the parallel and operation is 0 when aj is less than an-l, and the result of the parallel and operation is used as a bn-i knot of the standard digital rope; ai nodes which are not identical are taken from an nodes and are subjected to parallel and operation through a circuit, the results of the parallel and operation are connected together in parallel, the result of the parallel and operation is 1 when aj is larger than or equal to ai, the result of the parallel and operation is 0 when aj is small ai, and the result of the parallel and operation is used as a second node of the standard digital rope, wherein n > i > 1; and when i =1, carrying out the common and operation on the a junctions through the circuit, wherein the common or operation result is 0 when all the a junctions are virtual junctions, and the common and operation result is taken as the 1 st junction of the standard digital rope as long as the common and operation result of one real junction in the a junctions is 1. Examples are: let 8 knots in a digital rope, respectively al, a2, a3, a4, a5, a6, a7, a8, and the parallel numbered standard digital ropes are bl, b2, b3, b4, b5, b6, b7, b 8.

Reciprocal operation of (fourteen) digital rope set

Setting: a and B are respectively n-bit binary numbers, and the multiplication result of A and B is 2²ⁿ。

2n-l 2-level digital rope group expression²ⁿComprises the following steps: c. C_2n-1,c_2n-2,c_2n-3....c_i...c₄,c₃,c₂,c₁Wherein, the first digital rope c₁The position is 2 solid knots, the second digital rope c₂To the 2n-l digital rope c_2-1All are 1 solid knot.

The digital rope group expressing the binary number A has n digital ropes: respectively as follows: a is_n,a_n-1,a_n-2...a_i...a₃,a₂,a₁

The digital rope group for expressing the binary number B comprises n digital ropes which are respectively: b_n,b_n-1,b_n-2...b_i...b₃,b₂,b₁

Take n =8 as an example; the multiplication logic of A B is as follows:

a₈b₁a₇b₁a₆b₁a₅b₁a₄b₁a₃b₁a₂b₁

a₈b₂a₇b₂a₆b₂a₅b₂a₄b₂a₃b₂a₂b₂

a₈b₃a₇b₃a₆b₃a₅b₃a₄b₃a₃b₃a₂b₃

a₈b₄a₇b₄a₆b₄a₅b₄a₄b₄a₃b₄a₂b₄

a₈b_{5 a7b5}a₆b₅a₅b₅a₄b₅a₃b₅a₂b₅

a₈b_{6 a7b6}a₆b₅a₅b₆a₄b₆a₃b₆a₂b₆

a₈b_{7 a7b7}a₆b₇a₅b₇a₄b₇a₃b₇a₂b₇

a₈b_{8 a7b8}a₆b₈a₅b₈a₄b_sa₃b₈a₂b₈a₁b₈

c₁₅c₁₄c₁₃c₁₂c₁₁c₁₀c₉c₈c₇c₆c₅c₄c₃c₂c₁

A=2¹⁶mathematical relationship of/BDerivation of

Order: b_8-1The C digital rope group takes 2-level 8 digital ropes, the first digital rope is 2 real knots, and the rest digital ropes are 1 real knots, and the C digital rope group has the following characteristics:

a₈=1； a₇=l-b₇； a₆=1-b₆；

a₅=1-(a₆b₇+a₇b₆+b₅)=l-[(l-b₆)b₇+(l-b₇)b₆+b₅]=1+2b₆b₇-(b₅+b₆+b₇)

a₄= 1- (a₅b₇+a₆b₆+a₇b₅+b₄)= 1-{[1+2b₆b₇-(b₅+b₆+b₇)]b₇+(l -b₆)b₆+(l -b₇)b₅+b₄}

= l-(b₇+b₆b₇+b₅b₇+b₆b₇+b₅-b₇b₅+b₄)= l+2b₇b₅-(b₆b₇+b₅+b₄)

a₃=1- (a₄b₇+a₅b₆+a₆b₅+a₇b₄+b₃)=1 -{[l+2b₇b₅-(b₆b₇+b₅+b₄)]b₇+[l+2b₆b₇-(b₅+b₆+b₇)]b₆+(l -b₆)b₅+(l-b₇)b₄+b₃}= 1-(b₇+2b₅b₇-b₆b₇-b₅b₇-b₄b₇+b₆+2b₆b₇-b₅b₆-b₆-b₇b₆+b₅-b₆b₅+b₄-b₇b₄+b₃)=1 -(b₅b₇-2b₅b₆-b₄b₇+b₇+b₅+b₄+b₃)= 1+2b₅b₆+2b₄b₇-(b₇+b₅+b₄+b₃+b₅b₇)

a₂=1- (a₃b₇-a₄b₆-a₅b₅-a₆b₄-a₇b₃-b₂)

=l-(l+2b₅b₆+2b₄b₇-b₇-b₅-b₄-b₃-b₅b₇)b₇-(l+2b₇b₅-b₆b₇-b₅-b4)b₆-(l+2b₆b₇-b₅-b₆-b₇)b₅-(1 -b₆)b₄-( 1 -b₇)b₃-b₂

=1-b₇-2b₅b₆b₇-2b₄b₇+b₇+b₅b₇+b₄b₇+b₃b₇+b₅b₇-b₆-2b₅b₆b₇+b₆b₇+b₅b₆+b₄b₆-b₅-2b₅b₆b₇+b₅+b₅

b₆+b₅b₇-b₄+b₄-b₃+b₃b₇-b₂

= l+2b₃b₇+3b₅b₇+b₆b₇+2b₄b₆+2b₅b₆-b₆-b₄-b₃-b₂-6b₅b₆b₇-b₄b₇

=1+2b₃b₇+2b₄b₆+2b₅b₆+3b₅b₇+b₆b₇-(b₆+b₄+b₃+b₂+6b₅b₆b₇+b₄b₇)

a₁= 2-a₂b₇-a₃b₆-a₄b₅-a₅b₄-a₆b₃-a₇b₂-b₁

=2-(l+2b₃b₇+2b₄b₆+2b₅b₆+3b₅b₇+b₆b₇-b₆-b₄-b₃-b₂-6b₅b₆b₇-b₄b₇)b₇-(l+2b₅b₆+2b₄b₇-b₇-b₅-b₄-b₃-

b₅b₇)b₆-(l+2b₇b₅-b₆b₇-b₅-b₄)b₅-(l+2b₆b₇-b₅-b₆-b₇)b₄-(l-b₆)b₃-(l-b₇)b₂-b₁

=2-b₇-2b₃b₇-2b₄b₆b₇-2b₅b₆b₇-3b₅b₇-b₆b₇+b₆b₇+b₄b₇+b₃b₇+b₂b₇+6b₅b₆b₇+b₄b₇-b₆-2b₅b₆-2b₄b₆b₇+b₆b₇+b₅b₆+b₄b₆+b3b₆+b₅b₆b₇-b₅-2b₅b₇+b₅b₆b₇+b₃+b₄b₅-b₄-2b₄b₆b₇+b₄b₅+b₄b₆+b₄b₇-b₃+b₃b₆-b₂+b₂b₇-b₁

=2+b₂b₇+b₂b₇+b₃b₆+b₃b₆-2b₃b₇+b₃b₇+b₄b₅+b₄b₅+b₄b₆+b₄b₆+b₄b₇+b₄b₇+b₄b₇-2b₅b₆+b₅b₆-3b₅b₇-2b₅b₇-b₆b₇+b₆b₇+b₆b₇-2b₄b₆b₇-2b₄b₆b₇-2b₄b₆b₇-2b₅b₆b₇+6b₅b₆b₇+b₅b₆b₇+b₅b₆b₇-b₇-b₆-b₅+b₅-b₄-b₃-b₂-b₁= 2+2b₂b₇+2b₃b₆+2b₄b₅+2b₄b₆+3b₄b₇+b₆b₇+6b₅b₆b₇-b₇-b₆-b₄-b₃-b₂-b₁-b₃b₇-b₅b₆-5b₅b₇-6b₄b₆b₇

for a derived from above_1;a₂, a₃, a₄, a₅, a₆, a₇, a₈8 2 grades of digital rope groups of level skip the level, have:

a₈=1；a₇=l-b₇；a₆=l+b₆b₇-b₆；a₅=l+b₇b₅-(b₅+b₆+b₇)；a₄=l+b₅b₆+b₄-b₄-(b₆b₇+b₅+b₄+b₅b₆b₇)

a₃=l+b₃b₇+b,ib₆+bgb₆+bgb₆b₇~(b₇+bg+b₄+b₃+b₅b₇+b₅b₆b₇+b₄b₆b₇)

a₂=1+b₂b₇+b₃b₆+-b₄b₅+b₄b₆+b₅b₇+b₆b₇+bgb₆b₇-(b₆+b₄+b₃+b₂+-b₄b₆b₇)

a₁=2+b₄b₇+b₆b₇-b₇-b₆-b₄-b₃-b2-b₁-b₃b₇-b₅b₆-b₅b₇

the digital rope group is simplified again, and the method comprises the following steps:

a₈=1；a₇=(l-b₇)；a₆=b₆b₇+(l-b₆)；a₅=b₇b₅+( 1 -b₅)+( 1 -b₆)+( 1 -b₇)-2

a₄=b₅b₆+b₄b₇+( 1 -b₆b₇)+( 1 -b₅)+( 1 -b₄)+( 1 -b₅b₆b₇)-3

a₃= b₃b₇+b₄b₆+b₅b₆+b₅b₆b₇+(1-b₇)+(1-b₅)+(1-b₄)+(1 -b₃)+( 1 -b₅b₇)+(1 -b₅b₆b₇)+(1 -b₄b₆b₇)-6a₂= b₂b₇+b3b₆+b₄b₅+b₄b₆+b₅b₇+b₆b₇+b₅b₆b₇+(1-b₆)+(l-b₄)+(1-b₃)+(l -b₂)+(1-b₄b₆b₇)-4a₁= b₄b₇+b₆b₇+(1-b₇)+(1-b₆)+(1-b₄)+(1-b₃)+(1-b₂)+(1-b₁)+(1-b₃b₇)+(1-b₅b₆)+(1-b₅b₇)-7

the negative number in the digital rope group is reduced into one knot for each digital rope through skipping, and the method comprises the following steps:

a₈=i；a₇=(l-b₇)-l；a₆= b₆b₇+(l-b₆)；a₅= b₇b₅+( 1 -b₅)+( 1 -b₆)+( 1 -b₇)- 1；

a₄= b₅b₆+b₄b₇+( 1 -b₆b₇)+( 1 -b₅)+( 1 -b₄)+( 1 -b₅b₆b₇) -1

a₃= b₃b₇+b₄b₆+b₅b₆+b₅b₆b₇+( 1 -b₇)+(l -b₅)+(l -b₄)+(1 -b₃)+(]-b₅b₇)+(1 -b₅b₆b₇)+(1 -b₄b₆b₇)-l

a₂= b₂b₇+b₃b₆+b₄b₅+b₄b₆+ b₅b₇+b₆b₇+b₅b₆b₇+( 1 -b₆)+( 1 -b₄)+( 1 -b₃)+( 1 -b₂)+( 1 -b₄b₆b₇)-1

a₁= b₄b₇+b₅b₇+(l -b₇)+(l -b₆)+(l -b₄)+( 1 -b₃)+( 1 -b₂)+(l -b₁)+(1 -b₃b₇)+(l-b₅b₆)+(l -b₅b₇)-l

eliminate the negative number in the above digital rope set, have

a₈=2；a₇=(l-b₇)；a₆= b₆b₇+(l-b₆)+l；a₅= b₇b₅+(1-b₅)+(1-b₆)+(l-b₇)；

a₄= b₅b₆+b₄b₇+(1-b₆b₇)+(1-b₅)+(l -b₄)+(1-b₅b₆b₇)；

a₃= b₃b₇+b₄b₆+b₅b₆+b₅b₆b₇+(1-b₇)+(1-b₅)+(1-b₄)+(1-b₃)+(1-b₅b₇)+(1-b₅b₆b₇)+(1 -b₄b₆b₇)

a₂= b₂b₇+b₃b₆+b₄b₅+b₄b₆+b₅b₇+b₆b₇+b₅b₆b₇(l -b₆)+(l -b₄)+(1-b₃)+(l-b₂)+(l-b₄b₆b₇)

a₁=b₄b₇+b_Gb₇+(l-b₇)+(l-b₆)+(l-b₄)+(l-b₃)+(l-b₂)+(1-b₁)+(1-b₃b₇)+(l-b₅b₆)+(1-b₅b₇)+l

The method for establishing the mathematical model of the reciprocal operation of the digital rope group comprises the following steps: deducing by the inverse operation that the A digital rope group multiplied by the B digital rope group is equal to the C digital rope group, wherein the mathematical model is integer operation, when the binary number expressed by the B digital rope is N bits, the A digital rope group is the reciprocal of the B digital rope group, the number of bits expressed by the B digital rope group is also N bits, and the C digital rope group is 2 expressed by 2N-l digital ropes²ⁿThe mathematical relation of the numerical value and reciprocal operation is A =2²ⁿAnd establishing a/B, and shifting the operation result by 2n bits to the right. Because the reciprocal mathematical model is established in the C digital rope group tableTo be 2²ⁿNumerically, the number represented by the nth number string of the 2-level number string group B is 1, i.e., the nth bit of the binary operand must be 1. If the N bit of the binary operand is not 1, the binary operand is left shifted to 1, and the reciprocal operation is mathematically related to A = (2) assuming that the operand is left shifted by m bits²ⁿ/B）×2^mThe result of the reciprocal operation should be multiplied by 2^m-2n

The operation of converting each digital rope into a standard digital rope in the reciprocal operation is addition and subtraction mixed operation of digital rope codes, and the addition of a false code in the addition and subtraction mixed operation can be converted into addition operation. The method for converting into the addition operation is as follows: (1) the expression jumps. All 2 × a in the expression_ib_iEliminating the current level code along with the symbol jumping up one level, and dividing all 4 x a in the expression_ib_iJumping up 2 levels together with the symbol eliminates the level code, making a in each digital rope_ib_iThe coefficient of r is 1. (2) The negative sign is converted to a not-gate sign. All the a with negative sign in each digital rope_i,b_i,a_ib_iConversion to (1-a)_i）（1-b_i）,（l-a_ib_i) Making it a positive term, adding the signed real junction due to the conversion in the expression. (3) And (5) performing solid junction jump. And when the real knots in each digital rope group are larger than 1, jumping up the grade together with the symbols, so that the absolute value of the number of the real knots in each digital rope group is maximum 1. (4) Negatives are eliminated with a pseudocode. Make a set of values equal to 2²ⁿThe first digital rope in the digital rope group is two real knots, and negative sign real knots in each digital rope group are eliminated by the digital rope group with the reciprocal digital rope group. (5) And (5) performing solid junction jump. And when the number of the real knots in each digital rope is more than 1, skipping the grade again to ensure that the maximum number of the real knots in each digital rope is 1.

The mathematical model of reciprocal operation is established based on 2-level digital rope sets. On the basis of the 2-level digital rope sets, a digital model of reciprocal operation of the N-level digital rope sets can be established by combining the digital rope sets.

The whole process of the reciprocal operation circuit is as follows: (1) and establishing a digital rope group for reciprocal operation. (2) And converting the operation of each digital rope in the digital rope group into an addition operation. (3) Each digital rope in the digital rope group is converted into a standard digital rope through addition operation, each digital rope with saturated knots is converted into a standard digital rope with the knots equal to the grades through skipping grade reduction knots, then the digital ropes with the grades equal to the knots are converted into unsaturated digital ropes through parallel skipping grade reduction knots, and the digital ropes are decoded into binary codes.

Examples are: a 6-bit reciprocal operator is built. Let the digital rope group of 6-bit binary code B be B6, B5, B4, B3, B2 and bl, and as a result, the digital rope group A is composed of 6 digital ropes of a6, a5, a4, a3, a2 and al, and the floating point code is not in the circuit,

a₆=2、0；a₅=l-b₅+l；a₄=b₄b₅+(l-b₄)；a₃=b₅b₃+(1-b₃)+(1-b₄)+(1-b₅)；a₂=b₂b₅+b₃b₄+(1-b₄b₅)+(1-b₃)+(l-b₂)；a₁=(1-b₅)+(1-b₃)+(l-b₂)+(l-b₁)+(1-b₅b₇)

expressed by the additional floating-point code interface circuitry. The derivation of the mathematical model is:

(fifteen) division operation of digital string group

The division operation of the digital rope group is to make dividend and divisor into two digital rope groups with 2 levels. The divisor is first reciprocal and then the result of reciprocal operation is multiplied by the dividend.

(sixteen) arithmetic operation circuit interface

The operands of addition, subtraction, multiplication, reciprocal and division operation of the digital rope or the digital rope group are unsigned integers, the binary number sent into the operation circuit has requirements on the digit number, addition and subtraction operation requires decimal point alignment, reciprocal operation requires alignment with the highest bit, and the operation data generally can not meet the requirements of the operation circuit when the operation data is binary code integers, fixed point numbers or floating point numbers. When the input binary code operand does not meet the bit requirement of the circuit, an input interface is required to be added at the front end of the operational circuit, data conversion is carried out on integers, fixed points or floating points through the interface, the integers, the fixed points or the floating points are firstly converted into the integer binary code meeting the operational requirement, and the integers, the fixed points or the floating points are converted through the output interface after the operation is finished. Many data to be arithmetically operated are signed numbers, and the arithmetic operation circuit needs to operate the signs of the data in an input interface and an output interface to be capable of operating the signed numbers. In general, addition and subtraction operations require signed number operations to be performed by the interface circuit, and multiplication, reciprocal, and division operations may be signed operations or unsigned operations.

In binary codes, the data representation format is generally an integer, a fixed point number, and a floating point number, and the arithmetic operation circuit should have input interfaces for processing the above three data at the same time. The addition, subtraction and multiplication operation circuit is provided with output interfaces of the three data forms, and only two output interfaces of fixed point number and floating point number are needed for reciprocal and division. When the input interface and the output interface of the arithmetic operation circuit have various forms, the CPU selects and conducts the used input interface, and the CPU selects the output interface of the lyric number.

1. Input interface for adder and subtractor

In an arithmetic operation circuit, decimal points of addition or subtraction operation need to be aligned, and the arithmetic operation circuit can be integer operation or fixed point operation in which an integer and a decimal operate simultaneously. Therefore, the addition and subtraction of N bits should be performed as an addition circuit and a subtraction circuit of 2N bits, where the first N bits are an integer part and the last N bits are a fractional part. The first N bits are used for integer operation, the first 2N bits are used for fixed point operation, and the floating point number is converted into the fixed point number and then the fixed point operation is carried out. Therefore, the input interface of the addition and subtraction circuit is a direct input for integer operands and data conversion is performed for fixed point operands or floating point operands.

Three input interfaces of the addition and subtraction operation are all connected to the input end of the operation circuit by three groups of AND gate switch groups, and the opening and closing of the AND gate switch groups are controlled by the operation instruction of the CPU. When the operation instruction is integer operation, the AND gate switch group connected with the integer interface is turned on; when the operation instruction is fixed point number operation, the fixed point number interface is opened; and when the operation instruction is a floating point number, the AND gate switch group connected with the floating point interface is turned on.

In the three input interfaces of addition and subtraction, each interface is connected to the input ends of the addition operation circuit and the subtraction operation circuit by an AND gate switch group, each interface is provided with a sign operation circuit, and the sign operation circuit controls the opening and closing of the two groups of AND gate switch groups. When the addition operation is carried out, when the two operand symbols of the addition are different, the AND gate switch group connected with the subtraction operation is switched on; when the two operands of the addition are the same in sign, the AND gate switch group connected with the addition circuit is turned on.

In the two interface circuits of the addition and the subtraction, the fixed point number interface and the floating point number interface need to carry out data conversion, and the fixed point number or the floating point number is converted into an integer meeting the circuit requirement.

Data conversion of the fixed point number interface: a fixed point number is that the size of the number is expressed by an n-bit numerical value before a decimal point is fixed at the highest position; or after fixing the decimal point at the lowest bit, expressing the size of the number by using an n-bit numerical value; the data conversion of fixed point number is to shift the binary code of N digit value to the left by N bits and to shift the binary code of-N digit value to the right by N bits, the shifted binary code is composed of an integer part and a decimal part, the integer part is fed to the front N-bit operation circuit, and the decimal part is fed to the back N-bit operation circuit. The left shift or the right shift is as follows: the maximum value of N is limited to the number N of bits of an arithmetic unit, a binary code which expresses N and is sent from an input operand inlet is made into a buoy digital rope with the knot number N, each knot of the buoy digital rope is used as a common input end of a group of AND gate switch groups, one bit of the fixed point number operand is sequentially connected with the other input end of each AND gate in the gate group, and the output end of the gate group is connected with the input end of the arithmetic circuit. When the value of N is positive, the highest bit of the output end of the AND gate group is connected to the input port of the first N-bit arithmetic circuit, and the serial number of the highest bit in the first N bits is the same as the serial number of the buoy digital rope knot from the head end; when N is a negative value, the lowest bit of the output end of the AND gate group is connected to the input port of the back N-bit operational circuit, and the serial number of the lowest bit in the front N bits is the same as the serial number of the buoy digital rope knot extending from the tail end to the head end. When the value of N is equal to m and is a positive value, the mth knot in the buoy digital rope is a real knot, the highest bit of the fixed point number operand enters the mth bit of the input end of the front N-bit operation circuit, and the bits after the highest bit of the fixed point number operand sequentially enter the m bits of the front N-bit operation circuit and then sequentially enter the back N-bit operation circuit. When the N value is equal and negative, the mth knot from the tail end in the buoy digital rope is a real knot, the lowest bit of the fixed point number operand enters the Nth-mth bit of the input end of the back N-bit operation circuit, and the fixed point operand sequentially enters the front N-bit operation circuit before the m bits of the back N-bit operation circuit from the lowest bit.

Data conversion of floating-point number n

The absolute value of the floating-point number opcode is limited to a maximum of N. A floating-point number consists of a sign, a mantissa, an order, and an order code. The data conversion of the floating point number interface is to convert the floating point number into an integer and a decimal part, wherein the integer part is sent to the front N-bit addition and subtraction operation circuit, and the decimal part is sent to the back N-bit addition and subtraction operation circuit. The operation process of the floating-point circuit conversion is as follows: (1) the highest value of the mantissa is aligned with the top of the next N-bit arithmetic circuit. (2) And making the step code into a buoy digital rope. (3) And controlling a group of AND gate switch groups to perform parallel translation on the mantissas by using each knot and the step symbol of the buoy digital rope. The shifting method is the same as the fixed point shifting method, when the code is a positive value, the mantissa is shifted to the front N-bit operation circuit, and when the code is a negative value, the mantissa is shifted to the back N-bit operation circuit.

In the three interface circuits of addition and subtraction, each interface circuit is simultaneously connected to the input end of the addition operation circuit and the input end of the subtraction operation circuit, and the two AND gate switch group connection circuits are controlled by the sign operation circuit. When the signs of two operands of the addition circuit are different, the sign operation circuit sends the two added operands into the subtraction operation circuit through the control AND gate and the programmable gate array, the sign of the first operand is reserved, and the operation result of the subtraction circuit is subjected to sign operation to serve as the sign of the result number; when the signs are the same, the sign arithmetic circuit sends the two added operands into the addition arithmetic circuit by controlling the AND gate switch group, and the same signs are reserved as the signs in the output interface circuit. When the signs of the two operands are different, the sign operation circuit sends the two operands into the addition operation circuit by controlling the AND gate switch group, the sign of the first operand is reserved, and the operation result of the addition circuit is subjected to sign operation to be used as the sign of the result number. When the signs are the same, the sign arithmetic circuit controls the AND gate switch group to send the two operands into the subtraction arithmetic circuit, the same signs are reserved, and sign arithmetic is carried out in the output result of the subtraction circuit as the signs in the output interface circuit.

The addition operation circuit and the subtraction operation circuit are double N-bit circuits. The signed addition operation requires a subtraction circuit at the same time, and the signed subtraction circuit requires an addition circuit at the same time. The interface circuit with symbolic addition operation is the same as that of subtraction operation, and the input end interface circuit consists of a double-operand inlet with three data forms of integer, fixed point number and floating point number, a fixed point number conversion circuit, a floating point number conversion circuit, an integer symbolic operation and control circuit, a fixed point number symbolic operation and control circuit, an integer instruction control circuit consisting of CPU operation instructions, a fixed point number instruction control circuit, a floating point number instruction control circuit and twelve and gate switch groups. The work flow of the input end interface circuit is as follows: the CPU command selects the operand form entering the interface circuit, when selecting one form of integer, fixed point number and floating point number, the AND gate switch group controlled by the command control circuit is opened, and the CPU inputs two corresponding operands according to the selected form; the fixed point number conversion circuit and the floating point number conversion circuit convert data into an integer part and a decimal part; the sign operation and control circuit performs sign operation and connects the addition operation circuit or the subtraction operation circuit.

2. Output interface of addition circuit and subtraction circuit

Since the addition operation and the subtraction operation are signed operands, two addition operands may enter the subtraction circuit when operating, two subtraction operands may enter the addition circuit when operating, and the results of the addition and subtraction operations can only be combined to the same output port.

⑴ combining the output ports of the addition circuit and the subtraction circuit, three sign operation circuits at three input ports of the addition and subtraction, and controlling two sets of AND gate switch sets to connect the addition circuit or the subtraction circuit, therefore, the operation circuits at two input ports of the addition operand control the signal output ends of the addition circuit and the subtraction circuit to be combined into 2 control signals by an OR gate, the 2 control signals control 2 AND gate switches of the output port respectively, the operation circuits at three input ports of the subtraction operand control the signal output ends of the addition circuit and the subtraction circuit to be combined into 2 control signals, the 2 control signals control 2 AND gate switches of the output port respectively, thus, the operation results of the addition and subtraction circuit are combined into an operation result by 4 AND gate switches, no matter the input ports input two addition operands or two subtraction operands, no matter the input ports enter the addition circuit or the subtraction circuit, the combined operation result must be the correct operation result.

(2) And a symbol 3 arithmetic circuit of the output interface. The data output from the addition circuit to the merging port is unsigned data, and the data output from the subtraction circuit to the merging port is signed data, and therefore, the data of the merging port is one signed data. And the sign of the first operand reserved by the input port sign operation circuit and the sign of the merging port are operated again through the circuit to obtain the sign of final result data.

(3) Carry bit flag. Both the addition and signed subtraction operations have carry flags, and the data output through the output interface must also have carry flags.

(3) And an integer and decimal output interface. The data of the merged port is a double N-bit data, the first N-bit being an integer

The last N bits are the fractional part. All the double N-bit data are output as an integer and decimal output interface, and the CPU points to what data to play and then to what data to fetch.

(4) And (5) a fixed point number output interface. And converting the double N bit data of the merging port into fixed point data. The conversion method comprises the following steps:

the binary code of double N bits is taken as a digital rope code, the knot is filled to form a standard digital rope, then a standard digital rope with the number of 2N knots and the number of the real knots being N is made, the first standard digital rope is subtracted from the second standard digital rope, the result is made into a buoy digital rope, and the binary code obtained by decoding the buoy digital rope is the digit 2N of the fixed point number. And during the operation, the last N bit is taken as a reverse digital rope, the reverse filling knot is formed into a standard digital rope, and the standard digital rope is further made into a buoy digital rope. When the operation result is positive, each knot of the buoy digital rope controls one group of AND gate switch group to carry out data translation rightward, the most numerical value bit of the binary code after translation is translated to the highest position of the N rear bits, and the fixed point number with the decimal point fixed to the highest numerical value bit is formed. When the subtraction operation result of the digital rope is negative, each knot of the buoy digital rope controls one group of AND gate switch groups to perform data translation, and the highest numerical bit of the binary code after translation is translated to the highest position of the last N positions to form the fixed point number of which the decimal point is fixed to the highest numerical bit. When the operation result of the digital rope is negative, each node of the buoy digital rope made of the last N bits controls one group of AND gate switch groups, the binary code of the last N bits is shifted to the left in parallel, the binary code decoded by the buoy digital rope of the last N bits is the number N of fixed points, and the sign is negative, so that the fixed points after the decimal point is fixed to the lowest value are formed.

(5) A floating point number output interface. The dual N-bit data of the merged port is converted to floating point data. The conversion method comprises the following steps:

and taking the double N bits as a first digital rope, making the first digital rope into a standard digital rope by a method of filling real knots, making the standard digital rope into a buoy digital rope, making a second digital rope with the number of 2N and the number of the real knots being N, subtracting the second digital rope from each digital rope, and decoding the subtraction result to obtain a binary code with a step code and a symbol with a step symbol. The 2N groups of AND gate switch groups are respectively controlled by the 2N knots of the first buoy digital rope to move left in parallel, the AND gate switch group controlled by the real knots of the buoy digital rope moves the highest position of the binary data in the merging port to the highest position of the 2N positions, and the double N-bit data after the displacement becomes the mantissa of the floating point number.

3. Input interface for multiplication circuit

The multiplication operation has no requirement on the position of the operand decimal point, and can reserve the position of left shift or right shift of the binary code. In order to reduce the loss of calculation accuracy, the binary code is input into the multiplication circuit as much as possible. The multiplication circuit does not need to perform sign operation, and the CPU calculates signs. Therefore, the input interface of the multiplication circuit is to connect the operand to the multiplication circuit directly or after circuit conversion. When the operand is an integer, the integer operand is directly accessed into the multiplication circuit; when the operand is a floating point number, the mantissa of the floating point number is moved to the left to be an integer, and the number of human-mobile bits is subtracted from the order code to be reserved as the order code. The method for shifting the mantissa of the floating-point number to the left is as follows: putting the mantissa into a first digital rope with the knot number of N, manufacturing a standard digital rope by filling the knots, and manufacturing the standard digital rope into a buoy digital rope; and coding the step codes to form a second standard digital rope with the knot number of N. When the order symbol of the floating point number is positive, the binary code decoded by the operation result of subtracting the second standard digital rope from the first standard digital rope is the order code, and the sign is the order symbol; when the order symbol of the floating point number is negative, the binary code decoded by the operation result of the first standard digital rope and the second standard digital rope is the order code, and the order symbol is negative; the level code and the level symbol are reserved.

4. Output interface for multiplication circuit

An N-bit multiplication circuit outputs binary codes with at most 2N-bit integers. The output interface has three output ports, the first output port is an integer output port, the second output port is a fixed point output port, and the third output port is a floating point output port. When two operands input by the CPU from the input terminals by the integer multiplication instruction are integers, the result is fetched from the integer output port. The integer output interface is directly communicated with the output interface of the multiplication circuit. When the fixed point number is input into the input port, data is output from the fixed point number output port. The fixed point output port is used for making an integer binary code of a multiplication result into a fixed point through a circuit, then adding a bit value reserved by the fixed point input interface of the multiplication input interface and a result bit value by a signed number, and performing operation by using a digital code when adding. When the input port inputs a floating-point number, the data is output from the floating-point output port. The floating-point number output port makes the binary integer into floating-point number, adds the order code of the floating-point number and the order code and order symbol of the input port in signed number, and uses digital code to operate when adding. The operation flow of the multiplication output port is the inverse process of the operation flow of the multiplication input port.

5. Input interface of reciprocal circuit

In the reciprocal operation of the digital rope, the number of bits of the reciprocal circuit is set to be N bits, when the reciprocal of the A number is obtained, the reciprocal circuit needs to be an integer with the number of bits being N bits when the A number enters an input port of the reciprocal circuit. Therefore, the input interface of the reciprocal circuit shifts the number a into an integer with a number of bits N, and multiplies the integer by an inverse shift value. When the number a is an integer, assuming that the number a is further shifted by m bits with the number of bits N, the expression of a is: the method for inputting (A x 2m) x 2-m, integer at the input interface of reciprocal circuit is to shift A left by m bits and then send it to reciprocal circuit to keep-m. When the A number is a fixed point number with a decimal point fixed at the minimum bit of the numerical value, the bit value is that the numerical value part is shifted left by m bits to make the numerical value part become an integer with N bits and the integer is sent to a reciprocal circuit to reserve-N-m. When the A number is a fixed point number with a decimal point fixed before the maximum bit of the numerical value and the digit is N, the numerical value part is shifted left by m bits to make the numerical value part become an integer with the digit of N bits and sent to a reciprocal circuit, and N-m is reserved. When A is a floating point number, the order code of the symbol is d, the mantissa part is shifted to the left by N bits to make the mantissa become an integer with N bits, and the integer is sent to a reciprocal circuit to keep d-N.

Therefore, the three input interfaces of the reciprocal operation are all used for converting input operands into integers with N bits and sending the integers to a reciprocal circuit, wherein the integer input interface is used for reserving-m, the fixed point number input interface is used for reserving-N-m or N-m, and the floating point number interface is used for reserving d-N.

6. Output interface of reciprocal circuit

The reciprocal operation is premised on a × B =22N, and therefore, in the reciprocal operation of the digital rope, when a is an integer and the number of digits is N, the final result of the reciprocal B of the number a is: b = (1/a) × 2^2NWhen A is expressed as A = X2^yAnd X is an integer with the number of digits N, the final result of the reciprocal B of the number A being_：B=(1/X)×2^-2a-y. Obviously, y is the bit value of A reserved in the three input interfaces, and the output binary integer value is multiplied by 2^-2n-yIs the actual value of the reciprocal circuit.

The reciprocal circuit may have two output interfaces, one being a fixed point number output interface in which the decimal point is fixed after the minimum numerical digit, and one being a floating point number output interface. The fixed point number output interface with the decimal point fixed at the minimum numerical digit directly outputs the integer value of the operation result of the reciprocal circuit, and then subtracts the digit value reserved by the input port from-2 n to be used as the digit of the fixed point number. The floating point number output interface shifts the integer output from the output port of the reciprocal circuit to the left again, the highest bit shifted to the output integer is aligned with the highest bit of the output port, when the left shift digit is h, the floating point number is the order code of the floating point number by subtracting the value of the digit reserved by the input port from-2 n plus h, and the symbol generated in the operation of the order code is the order symbol.

7. Input interface of division circuit

The division circuit multiplies the divisor by the dividend after the operation of the reciprocal circuit. The input interface of the division circuit consists of a dividend input interface and a divisor input interface, the dividend input interface is the same as the input interface of the multiplication circuit, and the divisor input interface is the same as the input interface of the reciprocal circuit.

8. Output interface of division circuit

The division operation is essentially a multiplication of a dividend and a reciprocal of a divisor, and therefore, an output interface thereof is the same as an output interface of the reciprocal circuit.

It can be seen from the above that, when the digital rope code decoding and arithmetic operation circuit is designed, there are very abundant schemes and combinations. The design key points are as follows: (1) the design index is determined according to the application. The use requirements can be met by designing arithmetic circuit bits in the CPU of the single chip microcomputer, the arithmetic circuit bits can be designed to be 128 bits in the CPU of the computer to ensure that all data can be operated, and the arithmetic circuit bits of the high-performance CPU chip can be 256 bits. (2) Different combinations of circuits are selected depending on the speed of the CPU. The CPU speed of the singlechip is low, the number of elements is reduced by using parallel circuits as little as possible, the CPU speed of the computer is high, and the number of stages of arithmetic operation circuits is reduced by using the parallel circuits as much as possible. (3) The combination of schemes is selected according to the capacity of the CPU capable of integrating electronic components. The single chip CPU can provide small capacity of integrated element, and it uses whole integer arithmetic circuit, and no longer uses interface circuit. The computer uses the program to calculate the number of elements used by different combination schemes on the premise of ensuring the parallel input interface and output interface of a plurality of systems, thereby selecting the schemes. (4) The scheme is selected according to the usage program provided to the user. The single chip microcomputer needs to be developed and used by a user, is generally a short program, and only needs four arithmetic operation circuits of unsigned integer addition, subtraction, multiplication and reciprocal. The computer needs to execute more functions, software development is generally a large program, the use is convenient, signed arithmetic circuits for addition, subtraction, multiplication, division and reciprocal are required to be finished, and the interface function is rich, so that the operation speed is high, and the software development is convenient.

The present invention encodes binary code into magic logical code, and performs arithmetic operation with the magic logical code, and the arithmetic operation does not generate carry in the operation process, and then decodes the magic logical code into binary code. The mental arithmetic logic code is a grading code, the operation rules in all the digital ropes are the same, the digital ropes at the same level can be connected into one digital rope, the digital ropes at different levels can form a digital rope group, and the operation of different digital ropes in the digital rope group is carried out according to the skipping-level operation rules. The arithmetic operation circuit composed of the mental arithmetic code has a number of circuit stages much smaller than that of the arithmetic operation circuit composed of the binary code. Taking 256-bit floating-point addition, subtraction, division and reciprocal operation as an example, a digital rope arithmetic operation circuit consisting of a magic logical code is used for sending an integer, a fixed point number and a floating point number of a binary code into an operation circuit and outputting the integer, the fixed point number and the floating point number into the operation circuit, the addition and subtraction operation circuit is about 10 stages of basic logic elements, the multiplication circuit is about 20 stages, the reciprocal circuit is about 20 stages, and the division circuit is the stage sum of the multiplication circuit and the reciprocal circuit. Assuming that the switching speeds of the three basic logic elements are 100 hundred million times per second, the operation speed of addition or subtraction is 10 hundred million 256-bit data operation results per second, the operation speed of multiplication is 5 hundred million 256-bit data operation results per second, division is 2.5 hundred million 256-bit data operation results per second, and parallel operation of addition, subtraction, multiplication and division can be performed. The operation speed of the huge computer is much faster than that of the huge computer with the highest speed in the world, the used electronic elements are not much, 256-bit arithmetic operation circuits can be integrated into a CPU of the computer, 32-bit arithmetic operation circuits can be integrated into a CPU of a singlechip, and an add-subtract-multiply-divide arithmetic operation circuit can be made into a plug-in circuit board to be externally hung on the CPU. The circuit number is few, binary operands (integers, fixed point numbers and floating point numbers) are sent to the arithmetic circuit, binary arithmetic results are output from the circuit, the circuit number of addition and subtraction is less than 10, the circuit number of multiplication and reciprocal operation is less than 25, and the circuit number of division operation is less than 45. The used electronic elements are few, the operation speed is improved by thousands of times, the electronic elements can be integrated into a chip of a computer and a chip of a single chip microcomputer, the working efficiency of the computer is improved, a new way for manufacturing the chip is developed, and the economic and social benefits are huge.