阅读说明：本技术 显示装置 (Display device ) 是由 岛武弘 仲尾贵之 于 2016-10-28 设计创作，主要内容包括：一实施方式的显示装置具备：一对基板,具有配置有多个像素的显示区域；液晶层,被封入在上述一对基板之间；像素电极,配置于上述多个像素的每一个；共通电极,与上述像素电极对置,在与上述像素电极之间产生驱动上述液晶层的电位差；信号线,被供给与图像数据对应的数字信号；第1驱动电路,向上述信号线供给上述数字信号；第2驱动电路,向上述共通电极供给交流的共通信号；存储器,在上述显示区域中,配置于上述多个像素的每一个；第1驱动线,被供给图像的显示信号；第2驱动线,被供给图像的非显示信号；存储控制电路,在存储期间中,使上述存储器存储供给到上述信号线中的上述数字信号；以及选择控制电路,在显示期间中,选择上述显示信号及上述非显示信号中的、与存储在上述存储器中的上述数字信号对应的一方并供给到上述像素电极；在从上述显示期间向上述存储期间转移时,上述第2驱动电路不使上述显示期间的上述共通信号的电位下降。(A display device according to one embodiment includes: a pair of substrates having a display region in which a plurality of pixels are arranged; a liquid crystal layer sealed between the pair of substrates; a pixel electrode disposed in each of the plurality of pixels; a common electrode which is opposed to the pixel electrode and generates a potential difference for driving the liquid crystal layer between the common electrode and the pixel electrode; a signal line to which a digital signal corresponding to image data is supplied; a 1 st drive circuit for supplying the digital signal to the signal line; a 2 nd drive circuit for supplying an alternating current common signal to the common electrode; a memory arranged in each of the plurality of pixels in the display region; a 1 st drive line to which a display signal of an image is supplied; a 2 nd driving line supplied with a non-display signal of an image; a memory control circuit that causes the memory to store the digital signal supplied to the signal line during a storage period; and a selection control circuit that selects one of the display signal and the non-display signal corresponding to the digital signal stored in the memory and supplies the selected one to the pixel electrode during a display period; when the display period is shifted to the memory period, the 2 nd drive circuit does not lower the potential of the common signal in the display period.)

1. A display device is characterized in that a display panel is provided,

the disclosed device is provided with:

a pair of substrates having a display region in which a plurality of pixels are arranged;

a liquid crystal layer sealed between the pair of substrates;

a pixel electrode disposed in each of the plurality of pixels;

a common electrode which is opposed to the pixel electrode and generates a potential difference for driving the liquid crystal layer between the common electrode and the pixel electrode;

a signal line to which a digital signal corresponding to image data is supplied;

a 1 st drive circuit for supplying the digital signal to the signal line;

a 2 nd drive circuit for supplying an alternating current common signal to the common electrode;

a memory arranged in each of the plurality of pixels in the display region;

a 1 st drive line to which a display signal of an image is supplied;

a 2 nd driving line supplied with a non-display signal of an image;

a memory control circuit that causes the memory to store the digital signal supplied to the signal line during a storage period; and

a selection control circuit that selects one of the display signal and the non-display signal corresponding to the digital signal stored in the memory and supplies the selected one to the pixel electrode during a display period;

when the display period is shifted to the memory period, the 2 nd drive circuit does not lower the potential of the common signal in the display period.

2. The display device of claim 1,

the 2 nd drive circuit lowers the potential of the common signal in the display period and then raises the potential of the common signal when the display period is shifted to the memory period.

3. The display device of claim 1,

the selection control circuit is provided with a switching element,

the switching element connects one of the 1 st driving line and the 2 nd driving line to the pixel electrode based on the digital signal stored in the memory.

4. The display device of claim 3,

when the display period is shifted to the storage period, the 2 nd driving circuit lowers the potential of the common signal by a predetermined amount before the switching element electrically disconnects the 1 st driving line, the 2 nd driving line, and the pixel electrode.

5. The display device of claim 4,

the 2 nd drive circuit lowers the potential of the common signal by the predetermined amount, and after the switching element electrically disconnects the 1 st drive line, the 2 nd drive line, and the pixel electrode, raises the potential of the common signal by the predetermined amount.

6. The display device of claim 1,

in the display period, the polarity of the potential between the pixel electrode and the common electrode is periodically inverted.

7. The display device of claim 1,

the signal line extends through between the adjacent pixels;

at least one of the pair of substrates includes a light shielding layer for shielding light;

the light-shielding layer does not overlap the signal line between the adjacent pixels in the display region.

8. The display device of claim 1,

the pair of substrates includes a 1 st substrate and a 2 nd substrate;

the pixel electrode is disposed on the 1 st substrate;

the 1 st substrate includes a reflective layer that reflects light that reaches the 1 st substrate from the 2 nd substrate in a direction toward the 2 nd substrate;

an image is displayed by the light reflected by the reflective layer.

9. The display device of claim 1,

having a digital mode and an analog mode;

the 1 st driving line and the signal line are the same wiring;

in the digital mode, the operations of the storage period and the display period are executed;

in the analog mode, a signal corresponding to a level of an image is supplied to the 1 st drive line.

10. The display device of claim 1,

an auxiliary capacitance line for forming an auxiliary capacitance for driving the liquid crystal layer between the auxiliary capacitance line and the pixel electrode;

the 2 nd driving line and the auxiliary capacitance line are the same wiring.

11. A display device is characterized in that a display panel is provided,

the disclosed device is provided with:

a pair of substrates having a display region in which a plurality of pixels are arranged;

a liquid crystal layer sealed between the pair of substrates;

a pixel electrode disposed in each of the plurality of pixels;

a common electrode which is opposed to the pixel electrode and generates a potential difference for driving the liquid crystal layer between the common electrode and the pixel electrode;

a signal line to which a digital signal corresponding to image data is supplied;

a 1 st drive circuit for supplying the digital signal to the signal line;

a 2 nd drive circuit for supplying an alternating current common signal to the common electrode;

a memory arranged in each of the plurality of pixels in the display region;

a 1 st drive line to which a display signal of an image is supplied;

a 2 nd driving line supplied with a non-display signal of an image;

a memory control circuit that causes the memory to store the digital signal supplied to the signal line during a storage period;

a selection control circuit that outputs one of the display signal and the non-display signal to a direction selection signal line corresponding to the digital signal stored in the memory during a display period;

a scanning line for supplying a scanning signal; and

a gate circuit connected to the selection signal line and the scanning line, and configured to supply the display signal or the non-display signal output to the selection signal line to the pixel electrode when the scanning signal is supplied to the scanning line,

a predetermined capacitance is formed between the scanning line and the pixel electrode,

when the display period is shifted to the storage period, the scanning signal of the scanning line is shifted from a high level to a low level,

when the display period is shifted to the memory period, the 2 nd drive circuit lowers the potential of the common signal in the display period by a predetermined amount smaller than the potential difference between the high level and the low level, and raises the potential of the common signal to the potential of the common signal in the display period before the memory period ends.

12. The display device of claim 11,

the selection control circuit is provided with a switching element,

the switching element connects one of the 1 st driving line and the 2 nd driving line to the selection signal line based on the digital signal stored in the memory.

13. The display device of claim 12,

when the display period is shifted to the storage period, the 2 nd drive circuit lowers the potential of the common signal by the predetermined amount before the switching element electrically disconnects the 1 st drive line, the 2 nd drive line, and the selection signal line.

14. The display device of claim 13,

the 2 nd drive circuit lowers the potential of the common signal by the predetermined amount, and after the switching element electrically disconnects the 1 st drive line, the 2 nd drive line, and the selection signal line, raises the potential of the common signal by the predetermined amount.

15. The display device of claim 11,

in the display period, the polarity of the potential between the pixel electrode and the common electrode is periodically inverted.

16. The display device of claim 11,

the signal line extends through between the adjacent pixels;

at least one of the pair of substrates includes a light shielding layer for shielding light;

the light-shielding layer does not overlap the signal line between the adjacent pixels in the display region.

17. The display device of claim 11,

the pair of substrates includes a 1 st substrate and a 2 nd substrate;

the pixel electrode is disposed on the 1 st substrate;

the 1 st substrate includes a reflective layer that reflects light that reaches the 1 st substrate from the 2 nd substrate in a direction toward the 2 nd substrate;

an image is displayed by the light reflected by the reflective layer.

18. The display device of claim 11,

having a digital mode and an analog mode;

the 1 st driving line and the signal line are the same wiring;

in the digital mode, the operations of the storage period and the display period are executed;

in the analog mode, a signal corresponding to a level of an image is supplied to the 1 st drive line.

19. The display device of claim 11,

an auxiliary capacitance line for forming an auxiliary capacitance for driving the liquid crystal layer between the auxiliary capacitance line and the pixel electrode;

the 2 nd driving line and the auxiliary capacitance line are the same wiring.

Technical Field

The present invention relates to a display device.

Background

A display device such as a liquid crystal display device in which a memory is provided for each pixel in a display region is known. In such a display device, a storage period in which digital data corresponding to an image to be displayed is written into each memory, and a display period in which an image is displayed in a display region by setting a drive potential of each pixel to a potential corresponding to the digital data stored in each memory are alternately repeated. In this way, a method of driving the pixels based on the digital data stored in the memory is referred to as a digital mode, a digital driving method, or the like, for example.

In addition, a display device having a function of an analog mode (or an analog driving method) in which a driving potential of each pixel is changed in a plurality of steps in addition to a function of a digital mode has been proposed.

In order to realize operations in the storage period and the display period, various circuits and switching elements are provided in each pixel. These switching elements are turned on and off, and thus, for example, during the storage period, the components such as the pixel electrodes are electrically floating. The potential of the floating component changes under the influence of potential variations of other components. Therefore, an undesired electric field may occur in the pixel, resulting in a change in brightness of an image or the like.

Disclosure of Invention

In the display device using the digital mode, improvement in display quality is required.

In general, a display device according to each embodiment includes: a pair of substrates having a display region in which a plurality of pixels are arranged; a liquid crystal layer sealed between the pair of substrates; a pixel electrode disposed in each of the plurality of pixels; a common electrode which is opposed to the pixel electrode and generates a potential difference for driving the liquid crystal layer between the common electrode and the pixel electrode; a signal line to which a digital signal corresponding to image data is supplied; a 1 st drive circuit for supplying the digital signal to the signal line; a 2 nd drive circuit for supplying an alternating current common signal to the common electrode; a memory arranged in each of the plurality of pixels in the display region; a 1 st drive line to which a display signal of an image is supplied; a 2 nd driving line supplied with a non-display signal of an image; a memory control circuit that causes the memory to store the digital signal supplied to the signal line during a storage period; and a selection control circuit that selects one of the display signal and the non-display signal corresponding to the digital signal stored in the memory and supplies the selected signal to the pixel electrode during a display period. In the display device, when the display period is shifted to the memory period, the 2 nd drive circuit maintains the potential of the common signal in the display period also in the memory period.

In addition, in each embodiment, the display signal includes a 1 st potential and a 2 nd potential; the potential of the digital signal stored in the memory in the storage period is a 3 rd potential. And a display device which causes the memory to store the 3 rd potential in the storage period when a potential which is smaller in potential difference with the 3 rd potential out of the 1 st potential and the 2 nd potential is a potential of the pixel electrode immediately before the start of the storage period.

With this configuration, the display quality of the display device using the digital mode can be improved.

Drawings

Fig. 1 is a plan view showing a structure common to the respective embodiments of the display device.

Fig. 2 is a schematic plan view of the 1 st substrate and the 2 nd substrate included in the display device.

Fig. 3 is a diagram showing an example of an equivalent circuit of a sub-pixel provided in the display device.

Fig. 4 is a timing chart showing an example of the operation of the display device in the analog mode.

Fig. 5 is a timing chart showing an example of the operation in the storage period of the display device.

Fig. 6 is a timing chart showing an example of an operation in a display period of the display device.

Fig. 7 is a timing chart for explaining an example of a problem that may occur in the digital mode.

Fig. 8 is a cross-sectional view showing the state of the electric field generated in the sub-pixel in the display period and the storage period in the timing chart of fig. 7.

Fig. 9 is a cross-sectional view showing the state of the electric field generated in the sub-pixel in the other display period and the storage period in the timing chart of fig. 7.

Fig. 10 is a timing chart showing an example of the operation of the display device according to embodiment 1.

Fig. 11 is a timing chart showing an example of the operation of the display device according to embodiment 2.

Fig. 12 is a timing chart showing an example of the operation of the display device according to embodiment 3.

Fig. 13 is a timing diagram used to illustrate other problems that may occur in digital mode.

Fig. 14 is a timing chart showing an example of the operation of the display device according to embodiment 4.

Detailed Description

Some embodiments are described below with reference to the drawings.

The present disclosure is merely an example, and it is needless to say that appropriate modifications can be made by those skilled in the art while maintaining the gist of the present invention, and the modifications are included in the scope of the present invention. The drawings are only for illustrative purposes and are not intended to limit the scope of the present invention. In the drawings, the same or similar elements arranged in series are not denoted by the same reference numerals. In the present specification and the drawings, the same reference numerals are given to components that perform the same or similar functions as those described for the conventional drawings, and the overlapping detailed description may be omitted.

In each embodiment, as an example of a display device, a reflective liquid crystal display device having a function of an analog mode in which pixels are driven by a multi-level display signal and a function of a digital mode is disclosed. However, the respective embodiments do not hinder the application of the respective technical ideas disclosed in the respective embodiments to other kinds of display devices. As other types of display devices, a self-light-emitting type display device such as an organic electroluminescence display device, an electronic paper type display device having an electrophoretic element, and the like are conceivable.

First, the configuration and operation of the display device common to the respective embodiments will be described with reference to fig. 1 to 5.

Fig. 1 is a plan view showing an example of a schematic configuration of a display device 1. The display device 1 includes a 1 st substrate SUB1, a 2 nd substrate SUB2, and a liquid crystal layer LC. The 1 st substrate SUB1 and the 2 nd substrate SUB2 are bonded to each other in a state of facing each other. The liquid crystal layer LC is sealed between the 1 st substrate SUB1 and the 2 nd substrate SUB 2.

The display device 1 has a display area DA. The display region DA corresponds to a region where the pixels PX are arranged in a matrix on the 1 st substrate SUB 1. Specifically, in the display area DA, a large number of pixels PX are arranged in a matrix along the 1 st direction X and the 2 nd direction Y. The 1 st direction X and the 2 nd direction Y are orthogonal to each other, for example. The pixel PX includes sub-pixels SPX of red (R), green (G), and blue (B). In the present disclosure, the sub-pixel SPX may be referred to as a "pixel" for short.

In the example of fig. 1, the sub-pixels SPX included in 1 pixel PX are arranged in the 1 st direction X. However, the layout of the pixels PX is not limited to the example of fig. 1. For example, the pixel PX may further include a sub-pixel SPX of another color such as white (W). In addition, at least a part of the sub-pixels SPX included in the 1 pixel PX may be arranged in the 2 nd direction Y.

The display device 1 further includes a plurality of scanning lines G, a plurality of signal lines S, a control device 2, a scanning line drive circuit 3, and a signal line drive circuit 4 (1 st drive circuit). The scanning lines G and the signal lines S are formed on the 1 st substrate SUB 1. The scanning line driving circuit 3 and the signal line driving circuit 4 are formed at least partially on the 1 st substrate SUB1, for example, and are connected to the control device 2. The scanning lines G extend from the scanning line driving circuit 3 to the display area DA along the 1 st direction X and are arranged in the 2 nd direction Y. The signal lines S extend from the signal line driving circuit 4 toward the display area DA in the 2 nd direction Y and are arranged in the 1 st direction X. Each signal line S passes between the sub-pixels SPX adjacent in the 1 st direction X in plan view.

The control device 2 is, for example, an integrated circuit mounted on the 1 st substrate SUB1, and functions as a signal supply source that outputs various signals necessary for image display based on image data input from the outside. The control device 2 may be connected to the 1 st substrate SUB1 or the 2 nd substrate SUB2 via a flexible wiring board or the like, instead of being mounted on these substrates. The scanning line driving circuit 3 sequentially supplies scanning signals to the scanning lines G. The signal line drive circuit 4 includes a multiplexer 40. For example, the multiplexer 40 is a switching element group for switching the output destination of the signal among 3 signal lines S connected to the sub-pixels SPX of RGB.

The sub-pixels SPX include a memory 10 and a pixel electrode PE, respectively. The memory 10 mainly stores a digital signal supplied via the signal line S in the digital mode. The pixel electrode PE faces the common electrode CE formed on the 2 nd substrate SUB 2. The common electrode CE may be formed on the 1 st substrate SUB 1. The pixel electrode PE and the common electrode CE may be formed of a transparent conductive material such as Indium Tin Oxide (ITO), for example. The common electrode CE is formed in the plurality of sub-pixels SPX, and is connected to an ac drive circuit 20 (2 nd drive circuit) provided in the control device 2 via a common electrode line LCM. The ac drive circuit 20 is also connected to a storage capacitor line LCS. The auxiliary capacitance line LCS also extends to the display area DA and is connected to the circuit of each sub-pixel SPX.

The display device 1 includes color filters facing the sub-pixels SPX. These color filters have a color corresponding to the display color of the SUB-pixel SPX facing each other, and are formed on, for example, the 2 nd substrate SUB 2.

Fig. 2 is a schematic plan view of the 1 st substrate SUB1 and the 2 nd substrate SUB 2. A peripheral area FA is formed around the display area DA. The peripheral area FA corresponds to an area other than the display area DA, of the area where the 1 st substrate SUB1 and the 2 nd substrate SUB2 overlap in a plan view. The display device 1 includes a light-shielding layer 5 that overlaps substantially the entire peripheral region FA. The light-shielding layer 5 is disposed on, for example, the 2 nd substrate SUB 2. By providing the light-shielding layer 5, light leakage from the peripheral region FA and reflection of light by circuits and wirings formed in the peripheral region FA can be prevented.

In the display area DA, a reflective layer 6 that reflects external light is disposed. The reflective layer 6 may be formed of, for example, a metal material. The display device 1 displays an image using light reflected by the reflective layer 6. The reflective layer 6 is formed on the 1 st substrate SUB1 in contact with one surface of the pixel electrode PE, for example, as shown in fig. 8 and 9 described later. The display device 1 may further include a front light (front light) disposed on a surface of the 2 nd substrate SUB2 not facing the 1 st substrate SUB 1. The display device 1 may further include a backlight (backlight) disposed on a surface of the 1 st substrate SUB1 not facing the 2 nd substrate SUB 2. For example, a surface light source device including a light guide plate facing the display area DA and a plurality of light emitting diodes arranged along an end portion of the light guide plate can be used as the front light and the backlight. Further, the display device 1 may be provided with a backlight without the reflection layer 6.

For example, the light-shielding layer 5 is not disposed in the display area DA. That is, the light-shielding layer 5 does not overlap the signal line S between the adjacent sub-pixels SPX in the display area DA. This can increase the aperture ratio of each pixel PX, thereby displaying a high-luminance image. The light-shielding layer 5 may overlap a part of the display area DA. In this case, for example, the light-shielding layer 5 may be formed to overlap the scanning lines G.

Fig. 3 is a diagram showing an example of an equivalent circuit of the sub pixel SPX. The pixel electrode PE, the memory 10, a gate (gate) circuit 11, a selection control circuit 12, and a memory control circuit 13 are disposed in each sub-pixel SPX.

The gate circuit 11 includes switching elements Q1 and Q2 in which the scanning line G is connected to the control terminal and the output terminal is connected to the pixel electrode PE. The switching elements Q1 and Q2 are, for example, double-gate thin film transistors. The scanning line G is supplied with a scanning signal GATEA for turning on the switching elements Q1, Q2.

The selection control circuit 12 includes a switching element Q3 having an input terminal connected to the signal line S, and a switching element Q4 having an input terminal connected to the auxiliary capacitance line LCS. The display signal SIG or the 1 st drive signal xFRP is supplied to the signal line S from the signal line driver circuit 4. The auxiliary capacitance signal CS or the 2 nd drive signal FRP is supplied to the auxiliary capacitance line LCS from the ac drive circuit 20. An auxiliary capacitance Csc for driving the liquid crystal layer LC is formed by a potential difference between the auxiliary capacitance line LCS and the pixel electrode PE. The selection control circuit 12 further includes a selection signal line 12a connecting the output terminals of the switching elements Q3, Q4 and the input terminal of the switching element Q2. While the switching elements Q1 and Q2 are on, the selection signal line 12a and the pixel electrode PE are electrically connected. On the other hand, while the switching elements Q1 and Q2 are off, the selection signal line 12a and the pixel electrode PE are electrically disconnected.

In fig. 3, the wiring extending from the ac drive circuit 20 branches into the auxiliary capacitor line LCS and the common electrode line LCM. That is, in this example, the auxiliary capacitance signal CS or the 2 nd drive signal FRP supplied to the auxiliary capacitance line LCS and the common signal VCOM supplied to the common electrode line LCM are at the same potential.

The memory 10 includes switching elements Q5 to Q8. To input terminals of the switching elements Q5 and Q7, a 1 st power supply line LP1 for supplying a power supply voltage VRAM is connected. The 2 nd power supply line LP2 supplied with the voltage VSS is connected to input terminals of the switching elements Q6 and Q8. For example, the switching elements Q5, Q7 are PMOS transistors, and the switching elements Q6, Q8 are NMOS transistors. The switching elements Q5 and Q6 constitute a CMOS type 1 st converter (inverter) whose output terminal is connected to the control terminal of the switching element Q4, and the switching elements Q7 and Q8 constitute a CMOS type 2 nd converter whose output terminal is connected to the control terminal of the switching element Q3. These 1 st and 2 nd inverters are connected in parallel in the reverse direction, and selectively turn on one of the switching elements Q3 and Q4.

The memory control circuit 13 is a circuit for causing the memory 10 to store a digital signal, and includes a switching element Q9. The switching element Q9 has an input terminal connected to the signal line S and an output terminal connected to control terminals of the switching elements Q5 and Q6. At the control terminal of the switching element Q9, a digital scanning line LGD is connected. On the digital scanning line LGD, a scanning signal GATED is supplied.

The switching elements Q1 to Q9 are, for example, thin film transistors, and are formed on the 1 st substrate SUB 1. The auxiliary capacitance line LCS, the scan line G, the 1 st power supply line LP1, the 2 nd power supply line LP2, and the digital scan line LGD are also formed on the 1 st substrate SUB1 and connected to a plurality of SUB-pixels SPX arranged in the 1 st direction X. Signals of the 1 st power supply line LP1, the 2 nd power supply line LP2, and the digital scan line LGD are supplied from the control device 2, for example.

The display device 1 having the above-described configuration can drive each sub-pixel SPX in both the analog mode and the digital mode. The analog mode is a mode in which the luminance of each sub-pixel SPX is controlled in multiple stages based on a display signal supplied to the signal line S. The digital mode is a mode of monochrome control for simply turning ON (ON) and OFF (OFF) the luminance of the sub-pixel SPX based ON the digital data stored in the memory 10. In the following description, the following is assumed: the display device 1 is a normally black (black) mode display device, and in the digital mode, the sub-pixels SPX are turned on (white display) when the memory 10 is set to the H level (high potential level), and are turned off (black display) when the memory 10 is set to the L level (low potential level).

The basic operation of the display device 1 in the analog mode and the digital mode will be described below.

(simulation mode)

In the analog mode, the scanning pulses are sequentially supplied to the scanning lines G, and the display signals of multiple levels corresponding to the image data of the sub-pixels SPX corresponding to the scanning lines G to which the scanning pulses are supplied are sequentially supplied to the signal lines S. Thus, the potential corresponding to the image data is sequentially written for each of a group of sub-pixels SPX (hereinafter, referred to as a horizontal line) arranged in the 1 st direction X.

Fig. 4 is a timing chart showing an example of the operation of the display device 1 in the analog mode. In this timing chart, focusing on 1 sub-pixel SPX shown in fig. 3, changes in the scanning signal GATEA supplied to the scanning line G, the display signal SIG supplied to the signal line S, the pixel potential PIX of the pixel electrode PE, the common signal VCOM supplied to the common electrode CE, the scanning signal GATED supplied to the digital scanning line LGD, the power supply voltage VRAM supplied to the 1 st power supply line LP1, and the memory potential RAM stored in the memory 10 are shown. In the following description, a period for writing the pixel potential PIX to one horizontal line is defined as a horizontal period TH.

In the analog mode, the memory 10 is set to the H level. The operation for setting the H level is the same as the operation of fig. 5 described later. When the memory 10 is set to the H level and the power supply voltage VRAM is raised from the voltage VDD to the voltage VDD2 which is the drive voltage of the sub pixel SPX, the voltage VDD2 is supplied from the memory 10 to the switching element Q3. Thereby, the switching element Q3 is turned on. On the other hand, the switching element Q4 is turned off.

When the scan signal GATEA of the scan line G is raised from the voltage VSS2 to the voltage VDD2 (when a scan pulse is input), the switching elements Q1, Q2 are turned on, and the pixel electrode PE is connected to the signal line S. At this time, as indicated by arrows in the figure, the pixel potential PIX is set to the level of the display signal SIG supplied to the signal line S in a plurality of stages. When the scanning signal GATEA falls to the voltage VSS2, the pixel electrode PE is floated, and the potential difference between the pixel electrode PE and the common electrode CE is maintained by the storage capacitor Csc. Therefore, the sub-pixel SPX displays a color of a gradation corresponding to the written pixel potential PIX until the pixel potential PIX is rewritten next.

In the example of fig. 4, the case of the line inversion control in which the polarity of the potential between the pixel electrode PE and the common electrode CE is inverted for each horizontal line is shown. Therefore, the potential of the common signal VCOM changes between the voltages VSS and VDD every horizontal period TH.

(digital mode)

In the digital mode, a storage period in which the memory 10 stores the digital signal supplied to the signal line S and a display period in which one of the 1 st drive signal xmrp and the 2 nd drive signal FRP corresponding to the digital signal (H level or L level) stored in the memory 10 is selectively supplied to the pixel electrode PE are repeated.

In the storage period, the scanning pulses are sequentially supplied to the digital scanning lines LGD, and digital display signals of one horizontal line corresponding to the digital scanning lines LGD to which the scanning pulses are supplied are sequentially supplied to the respective signal lines S. Thereby, the digital signal corresponding to the image data is sequentially written into the memory 10 for each horizontal line.

Fig. 5 is a timing chart showing an example of the operation in the storage period of the display device 1. In the timing chart, 1 subpixel SPX is focused as in the case of fig. 4. In the storage period, the scan signal GATEA of the scan line G is set to the voltage VSS 2. Thus, the pixel electrode PE floats.

In the horizontal period TH in which writing into the memory 10 is performed, the display signal SIG of the signal line S is set to a potential to be written into the memory 10. Here, it is assumed that the voltage VDD as the H level corresponds to white display, and the voltage VSS as the L level corresponds to black display. Since the power supply voltage VRAM of the 1 st power supply line LP1 has the same potential as that of the memory 10 during the storage period, the voltage is lowered from the voltage VDD2 to the voltage VDD. Then, when the scan signal GATED of the digital scan line LGD rises from the voltage VSS2 to the voltage VDD2 (when a scan pulse is input), the switching element Q9 is turned on, and the memory 10 is connected to the signal line S. At this time, as shown by the arrow in the figure, the level of the display signal SIG supplied to the signal line S is written into the memory 10. In fig. 5, a case where the H level is written to the memory 10 is exemplified.

Then, by lowering the scan signal GATED to the voltage VSS2 while the switching element Q9 is turned off, the power supply voltage VRAM is raised to VDD2 which is a voltage at which the switching elements Q3, Q4 are turned on. At this time, the voltage of memory 10 also rises from VDD to VDD 2. In this way, memory 10 connects 1 st power supply line LP1 to switching element Q3, and turns on switching element Q3 by power supply voltage VRAM. On the other hand, in the memory 10, the power supply line LP2 is connected to the switching element Q4, and the switching element Q4 is turned off by the voltage VSS. When the switching element Q3 is turned on, the potential of the signal line S is supplied to the pixel electrode PE.

If the potential supplied to the memory 10 is at the L level corresponding to black display, the memory 10 connects the 2 nd power supply line LP2 to the switching element Q3, and turns off the switching element Q3 with the voltage VSS. In memory 10, power supply line LP1 is connected to switching element Q4, and switching element Q4 is turned on by power supply voltage VRAM. When the switching element Q4 is turned on, the pixel electrode PE and the auxiliary capacitance line LCS are connected, and a signal having the same potential as the common signal is supplied. That is, the memory 10 exclusively turns on one of the switching elements Q3 and Q4 by the stored voltage, and selects one of the signal line S and the storage capacitor line LCS as the connection destination of the pixel electrode PE.

Fig. 6 is a timing chart showing an example of the operation in the display period of the display device 1. In the timing chart, 1 subpixel SPX is focused as in the case of fig. 5. In the example of fig. 5 and 6, the frame inversion control is employed in which the polarity of the potential between the pixel electrode PE and the common electrode CE is periodically inverted for each frame period TF in all the sub-pixels SPX arranged in the display area DA. The rewriting of the memory 10 for each horizontal line constituting 1 frame is performed, for example, during 1 frame period TF. That is, the series of horizontal periods TH shown in fig. 5 is included in 1 frame period TF, and the common signal VCOM and the auxiliary capacitance signal CS are constant. On the other hand, as shown in fig. 6, the display period is constituted by a plurality of frame periods TF, and the potentials of the common signal VCOM and the auxiliary capacitance signal CS change between the voltages VSS and VDD for each frame period TF.

In the display period, the storage capacitor signal CS that changes for each frame period TF corresponds to the alternating current 2 nd drive signal FRP. In the display period, the 1 st drive signal xFRP is supplied to the signal line S. The 1 st drive signal xFRP is an alternating current signal having an inverse phase to the 2 nd drive signal FRP, and changes between the voltages VDD and VSS for each frame period TF.

In the display period, the scan signal GATEA of the scan line G is raised from the voltage VSS2 to the voltage VDD 2. Therefore, when the switching element Q3 is turned on by the memory 10, the signal line S is connected to the pixel electrode PE, and when the switching element Q4 is turned on by the memory 10, the storage capacitor line LCS is connected to the pixel electrode PE. In fig. 6, a case where the pixel potential PIX is set to the 1 st drive signal xFRP since the signal line S is connected to the pixel electrode PE is exemplified. In this case, a potential difference between the voltage VDD and the voltage VSS occurs between the pixel electrode PE and the common electrode CE, and the sub-pixel SPX displays white. On the other hand, when the storage capacitor line LCS is connected to the pixel electrode PE, no potential difference occurs between the pixel electrode PE and the common electrode CE, and the sub pixel SPX displays black.

As is apparent from the above description, the signal line S has both a function as a signal line for supplying digital data stored in the memory 10 and a function as a 1 st drive line for supplying a 1 st drive signal xmrp that is a display signal of an image. The storage capacitor line LCS has a function of supplying the storage capacitor signal CS as a signal line and a function of supplying the 2 nd drive signal FRP as a non-display signal of an image as a 2 nd drive line. This reduces the number of wirings in the display area DA, and therefore, the sub-pixel SPX can be made finer and the aperture ratio can be increased.

In the storage period, the switching elements Q1 and Q2 are turned off, and thus the pixel electrode PE is floated. One of the problems that may occur with this will be described with reference to fig. 7 to 9.

Fig. 7 is a timing chart showing changes in the scanning signal GATEA, the common signal VCOM, the auxiliary capacitance signal cs (frp), the display signal sig (xfrp), and the pixel potential PIX in the storage period and the display period which are repeated in time series. In this example, it is assumed that all the sub-pixels SPX of the display area DA are continuously displayed in white. Here, the storage period is constituted by 1 frame period TF, and the display period is constituted by two frame periods TF. However, the storage period and the display period may be configured by more frame periods TF.

In the storage period 1 on the left side in the figure, a display signal SIG (solid line) of a voltage VDD is supplied to set the potential of the memory 10 to the H level. In the storage period 1, the scan signal GATEA is lowered to the voltage VSS2, and the pixel electrode PE is floated. Therefore, the pixel potential PIX (dotted line) is driven by the potential rise of the common signal VCOM to rise. That is, the pixel potential PIX is raised to the voltage VDDx2 so that the potential difference between the pixel potential PIX and the common signal VCOM in the immediately preceding display period 0 is maintained. The voltage VDDx2 is a voltage about 2 times the difference between the voltages VDD, VSS.

In the display period 1 following the memory period 1, the 1 st driving signal xFRP of the alternating current is supplied to the signal line S. In the storage period 2 following the display period 1, the display signal SIG of the voltage VDD is supplied again in order to continue the setting of the H level in the memory 10. Since the pixel electrode PE is floating in the storage period 2, the pixel potential PIX is lowered by the lowering of the potential of the common signal VCOM. That is, the voltage drops to the voltage-VDD so that the potential difference between the pixel potential PIX and the common signal VCOM in the immediately preceding display period 1 is maintained. The voltage-VDD is lower than the voltage VSS by a difference between the voltages VDD and VSS. In this way, in the storage period 2, a large potential difference Vx occurs between the signal line S and the pixel electrode PE.

Fig. 8 is a cross-sectional view showing the state of the electric field generated in the sub-pixel SPX in (a) the display period 0 immediately before the storage period 1 and (b) the storage period 1. In the example of the figure, the reflective layer 6 is formed on the surface of the pixel electrode PE on the liquid crystal layer LC side. The reflective layer 6 reflects light incident on the 2 nd substrate SUB2, passing through the liquid crystal layer LC and reaching the 1 st substrate SUB1, toward the 2 nd substrate SUB 2. In fig. 8(a), the pixel electrode PE is at a voltage VDD, and the common electrode CE is at a voltage VSS. Thus, an electric field from the pixel electrode PE toward the common electrode CE occurs. Further, since the signal line S is at the voltage VDD, an electric field also occurs from the signal line S toward the common electrode CE.

On the other hand, in fig. 8(b), the pixel electrode PE is at the voltage VDDx2, and the common electrode CE and the signal line S are at the voltage VDD. Therefore, an electric field from the pixel electrode PE toward the common electrode CE and an electric field from the pixel electrode PE toward the signal line S occur.

For example, if the voltage VSS is 0V and the voltage VDD is 3.2V, the voltage VDDx2 is about 6.4V. In this case, each electric field generated in fig. 8(a) and 8(b) is caused by a potential difference of 3.2V.

Fig. 9 is a cross-sectional view showing the state of the electric field generated in the sub-pixel SPX in (a) the display period 1 immediately before the storage period 2 and (b) the storage period 2. In fig. 9(a), the pixel electrode PE and the signal line S are at a voltage VSS, and the common electrode CE is at a voltage VDD. Thus, an electric field is generated from the common electrode CE toward the pixel electrode PE and the signal line S.

On the other hand, in fig. 9(b), the pixel electrode PE is at the voltage-VDD, the common electrode CE is at the voltage VSS, and the signal line S is at the voltage VDD. In this case, an electric field from the common electrode CE toward the pixel electrode PE and an electric field from the signal line S toward the pixel electrode PE mainly occur.

For example, if the voltage VSS is set to 0V and the voltage VDD is set to 3.2V, the voltage-VDD is about-3.2V. In this case, the electric field generated between the pixel electrode PE and the common electrode CE in fig. 9(a) and 9(b) is caused by a potential difference of 3.2V. In fig. 9(b), the electric field generated between the pixel electrode PE and the signal line S is a strong electric field due to the potential difference Vx of 6.4V. This strong electric field affects the vertical electric field between the pixel electrode PE and the common electrode CE as in the region surrounded by the broken line in fig. 9(b), and the alignment controllability of the liquid crystal layer LC is lowered, so that there is a possibility that a problem such as a decrease in the luminance of the sub-pixel SPX occurs.

In the lower part of fig. 7, a display area da (display) in which an image is displayed is schematically shown. Since it is assumed that all the sub-pixels SPX are continuously displayed in white, substantially all the display area DA is continuously displayed in white. However, in the storage period 2, the luminance due to the potential difference Vx decreases, and a flash phenomenon occurs in which the image in the display area DA becomes darker than in other periods. Such a flicker phenomenon becomes a factor of deterioration of display quality.

In addition, although the case of white display is illustrated here, in the case of black display as well, a large potential difference Vx is formed between the pixel electrode PE and the signal line S during the storage period, and a flash phenomenon may occur.

Hereinafter, embodiments for suppressing the deterioration of display quality due to the flicker phenomenon are disclosed.

(embodiment 1)

In embodiment 1, when the display period is shifted to the storage period, the potential of the common signal VCOM and the potential of the storage capacitor signal cs (frp) in the display period are also maintained in the storage period, thereby suppressing the flash phenomenon. The following describes the details of the present embodiment.

Fig. 10 is a timing chart showing an example of the operation of the display device 1 according to embodiment 1. In the figure, similarly to the case of fig. 7, a case is assumed in which the sub-pixel SPX is displayed in white, and the potentials of the respective signals in the display period 0, the storage period 1, the display period 1, the storage period 2, and the display period 2 in time series are shown.

In the frame period TF immediately before the memory period 1, i.e., in the second half of the display period 0, the voltages of the common signal VCOM and the auxiliary capacitance signal CS are VSS. In this case, the ac drive circuit 20 maintains the voltages of the common signal VCOM and the auxiliary capacitance signal CS at VSS also in the storage period 1. That is, the ac drive circuit 20 stops the ac output in the storage period 1. In the display period 1 following the memory period 1, the ac drive circuit 20 starts the ac output again. Thus, the common signal VCOM and the auxiliary capacitance signal CS become an alternating current signal (FRP) that shifts between the voltages VSS and VDD for each frame period TF.

In the frame period TF immediately before the storage period 2, i.e., in the second half of the display period 1, the voltages of the common signal VCOM and the auxiliary capacitance signal CS are VDD. In this case, the ac drive circuit 20 stops the ac output, maintains the voltages of the common signal VCOM and the auxiliary capacitance signal CS in the storage period 2 at VDD, and restarts the ac output in the display period 2 following the storage period 2.

In fig. 10, the waveform of the display signal sig (xmrp) is the same as that in fig. 7, but the waveform of the pixel potential PIX is different. That is, in the memory period 1, the common signal VCOM is the voltage VSS, so that the pixel potential PIX is the voltage VDD. In the storage period 2, the voltage of the common signal VCOM is VDD, and thus the pixel potential PIX is the voltage VSS.

In the example of fig. 7, the potential difference Vx between the pixel electrode PE and the signal line S becomes larger than or equal to the difference between the voltages VDD and VSS in the storage period 2, whereas in the example of fig. 10, the potential difference Vx ends up in the difference between the voltages VDD and VSS. Therefore, according to the present embodiment, the flicker phenomenon is suppressed, and the deterioration of the display quality can be prevented.

In addition, although the case of white display is described as an example, the flash phenomenon can be suppressed similarly also in the case of black display. In the present embodiment, the ac output of the common signal VCOM is stopped in both the storage period 1 and the storage period 2, but the ac output may be stopped only in a part of the storage period.

In the present embodiment, the output of the ac drive circuit 20 is controlled to suppress the flash phenomenon, and no new wiring or element is used. Therefore, the precision of the sub-pixel SPX is not lowered, and the manufacturing yield is not deteriorated due to the increase in the density of the circuit pattern.

In addition to the above description, various advantageous effects can be obtained from the present embodiment.

(embodiment 2)

In embodiment 2, the flash phenomenon is made difficult to capture by the human eye by making the storage period short. The following describes the details of the present embodiment.

Fig. 11 is a timing chart showing an example of the operation of the display device 1 according to embodiment 2. In the figure, similarly to the case of fig. 7, assuming that the sub-pixel SPX is in white display, the potentials of the respective signals in the display period 0, the storage period 1, the display period 1, the storage period 2, and the display period 2 in the display time series are shown.

Waveforms of signals in each display period and each storage period are the same as those in fig. 7. However, in fig. 11, the frame period constituting the storage period is TF1, and each frame period constituting the display period is TF 2. The frame period TF1 is shorter than the frame period TF2 (TF1< TF 2).

The frequencies of the common signal VCOM and the auxiliary capacitance signal CS output from the ac drive circuit 20 during the storage period are the 1 st frequency Fq1 (hz). On the other hand, the frequencies of the common signal VCOM and the auxiliary capacitance signal cs (frp) output by the ac drive circuit 20 during the display period are the 2 nd frequency Fq2 (hz). Since the frame period TF1 is shorter than the frame period TF2, the 1 st frequency Fq1 is higher than the 2 nd frequency Fq2 (Fq1> Fq 2). As shown in fig. 10, the frequency is based on the number of waveforms returned from a specific value to the specific value via a maximum value or a minimum value.

In the example of fig. 11, as in the case of fig. 7, the potential difference Vx between the pixel electrode PE and the common electrode CE in the storage period 2 becomes large, and a flash phenomenon may occur. However, since the 1 st frequency Fq1 is higher than the 2 nd frequency Fq2, the period during which the luminance is decreased in the storage period 2 becomes relatively short, and the flash phenomenon becomes inconspicuous.

For example, if the 1 st frequency Fq1 is 1.5 times or more the 2 nd frequency Fq2, it is possible to appropriately prevent the display quality from being degraded by the flash phenomenon. If the 1 st frequency Fq1 is 2 times or more the 2 nd frequency Fq2, a higher effect of preventing deterioration of the display quality can be obtained. In order to stably store the potential in the memory 10, the 1 st frequency Fq1 is preferably 5 times or less the 2 nd frequency Fq 2.

From another point of view, if the 1 st frequency Fq1 is set to 90hz or more, the flicker phenomenon becomes hard to catch by the human eyes, and the degradation of the display quality can be prevented appropriately. Further, if the 1 st frequency Fq1 is set to 120hz or more, the flash phenomenon is hardly recognized, which is more preferable. The 2 nd frequency Fq2 may be set to, for example, about 60 Hz. In order to stably store the potential in the memory 10, the 1 st frequency Fq1 is preferably 300hz or less.

In addition, although the case of white display is described as an example, the flash phenomenon can be suppressed similarly also in the case of black display.

In the present embodiment, as in embodiment 1, the output of the ac drive circuit 20 is controlled to suppress the flash phenomenon, and no new wiring or element is used. Therefore, the precision of the sub-pixel SPX is not lowered, and the manufacturing yield is not deteriorated due to the increase in the density of the circuit pattern.

In addition to the above description, various advantageous effects can be obtained from the present embodiment.

(embodiment 3)

In embodiment 3, the occurrence of the flash phenomenon is prevented by making it possible to shift from the display period to the storage period when the pixel potential PIX satisfies a predetermined condition. The following describes the details of the present embodiment.

Fig. 12 is a timing chart showing an example of the operation of the display device 1 according to embodiment 3. In the figure, similarly to the case of fig. 7, assuming that the sub-pixel SPX is in white display, the potentials of the respective signals in the display period 0, the storage period 1, the display period 1, the storage period 2, and the display period 2 in the display time series are shown.

In the present embodiment, when the display period is shifted to the storage period, the control device 2 determines whether or not the shift is possible. In this determination, the potential Va, the 1 st potential V1, the 2 nd potential V2, and the 3 rd potential V3 are used. The potential Va is the pixel potential PIX immediately before the start of the storage period. The 1 st potential V1 is the L-level voltage VSS of the 1 st drive signal xFRP, and the 2 nd potential V2 is the H-level voltage VDD of the 1 st drive signal xFRP. The 3 rd potential V3 is a potential of the display signal SIG stored in the memory 10 during the storage period.

Specifically, the control device 2 determines that the transition to the storage period is possible when the execution condition that "the potential Va is a potential having a smaller potential difference from the 3 rd potential V3 out of the 1 st potential V1 and the 2 nd potential V2" is satisfied. In this case, the operation shifts to the storage period, and the 3 rd potential V3 is stored in the memory 10. On the other hand, when the execution condition is not satisfied, the control device 2 determines that the transition to the storage period is not possible. In this case, the display period is extended by a predetermined frame period TF (for example, 1 frame period TF) without shifting to the storage period even when the write timing to be shifted to the storage period originally arrives. Then, it is determined again whether or not the transition to the storage period is possible, and if so, the transition is made to the storage period.

A specific example is shown with reference to fig. 12. First, the 3 rd potential V3 stored in the memory 10 in the storage period 1 is VDD which is a white potential. In this case, the 1 st potential V1(VSS) and the 2 nd potential V2(VDD) have a smaller potential difference from the 3 rd potential V3, and the 2 nd potential V2 has no potential difference from the 3 rd potential V3. In the display period 0 immediately before the write timing 1 in which the memory period 1 should be executed, the potential Va is the 2 nd potential V2. This makes it possible to perform a transition to the storage period when the execution condition is satisfied. Therefore, the operation of the storage period 1 is executed at the write timing 1.

On the other hand, in the display period 1 immediately before the write timing 2 in which the memory period 2 should be executed, the potential Va (in the figure, parentheses) is the 1 st potential V1. Further, the 3 rd potential V3 stored in the memory 10 in the storage period 2 is VDD. In this case, the execution condition is not satisfied, and therefore, the transition to the storage period cannot be performed. Therefore, the operation of the memory period 2 is not executed at the write timing 2, and the display period 1 is extended by 1 frame period TF.

Next, after the extension, in the display period 1 immediately before the write timing 2a at which the operation of the memory period 2 is to be performed (in the example of fig. 12, the extension period), the potential Va is the 2 nd potential V2. In this case, since the execution condition is satisfied, the transition to the storage period can be performed. Therefore, the operation of the memory period 2 is executed at the write timing 2 a.

In the example of fig. 12, the display period 1 is extended by 1 frame period TF when the execution condition is not satisfied, but the display period 1 may be extended by more frame periods TF.

Here, it is assumed that all the sub-pixels SPX included in the display area DA are displayed in white, but the same control can be adopted also when all the sub-pixels SPX are displayed in black or when the sub-pixels SPX displayed in white and the sub-pixels SPX displayed in black are mixed. When the sub-pixel SPX for white display and the sub-pixel SPX for black display are mixed, the sub-pixel SPX having the potential Va different from the 3 rd potential V3 is mixed in 1 writing timing. In this case, for example, when the number of sub-pixels SPX for which the execution condition is satisfied is equal to or greater than a predetermined threshold value among all the sub-pixels SPX, the display period may be extended and the storage period may be set to be later. Further, since the flash phenomenon in the sub-pixels SPX for black display has less influence on the display quality than in the case of white display, the display period may be extended and the storage period may be set in the wrong manner when the execution condition is satisfied for all the sub-pixels SPX for white display or when the number of sub-pixels SPX for which the execution condition is satisfied in the sub-pixels SPX for white display is equal to or greater than a predetermined threshold value.

According to the present embodiment, the potential of the display signal SIG in the storage period and the pixel potential PIX immediately before the storage period have values close to each other (the same value in the example of fig. 12). Therefore, even if the potential of the pixel electrode PE which becomes floating in the memory period fluctuates in accordance with the potential of the common electrode CE, the large potential difference Vx as shown in fig. 7 does not occur. This can suppress the flash phenomenon.

In addition to the above description, various advantageous effects can be obtained from the present embodiment.

(embodiment 4)

In embodiments 1 to 3, a method for eliminating the problems illustrated in fig. 7 to 9 is disclosed. Here, another problem that may occur in the digital mode will be described using the timing chart of fig. 13.

When the display period is shifted to the storage period, the scan signal GATEA falls to the voltage VSS2, and the switching elements Q1 and Q2 are turned off. Thereby, the selection signal line 12a and the pixel electrode PE are electrically disconnected, and the pixel electrode PE is floated. When the scanning signal GATEA falls, the pixel potential PIX may also fall by the prescribed potential Δ V by capacitive coupling of the pixel electrode PE and the scanning line G. In this case, the luminance of the sub-pixel SPX changes during the storage period, and the display quality is degraded.

In order to suppress such a luminance change, in the present embodiment, the potentials of the common signal VCOM and the auxiliary capacitance signal CS are lowered by a predetermined amount before the switching elements Q1 and Q2 electrically disconnect the selection signal line 12a and the pixel electrode PE. A specific example of this operation is described below.

Fig. 14 is a timing chart showing an example of the operation of the display device 1 according to embodiment 4. This timing chart is an example in which the present embodiment is applied to the operation of embodiment 1. When the ac drive circuit 20 shifts from the display period to the storage period, the potentials of the common signal VCOM and the auxiliary capacitance signal CS are lowered by a predetermined amount (Δ V in the drawing) at a timing slightly earlier than the timing at which the scanning signal GATEA is lowered.

When the scan signal GATEA falls, the pixel potential PIX falls by the potential Δ V through capacitive coupling of the scan line G and the pixel electrode PE. After the scanning signal GATEA falls and the selection signal line 12a and the pixel electrode PE are electrically disconnected, the ac drive circuit 20 increases the potentials of the common signal VCOM and the auxiliary capacitance signal CS by a predetermined amount (Δ V). At this time, since the pixel electrode PE is floating, the pixel potential PIX is driven by the potential rise of the common signal VCOM and rises together by a predetermined amount (Δ V).

With the above operation, the potential difference between the pixel electrode PE and the common electrode CE in the display period is also maintained in the memory period immediately after the display period. Therefore, a luminance change due to capacitive coupling between the scanning line G and the pixel electrode PE can be prevented.

In the example of fig. 14, the predetermined amount is the potential Δ V, but the predetermined amount does not necessarily completely match Δ V. For example, even if the above-described predetermined amount is a value smaller than Δ V, it can contribute to a reduction in luminance change during the storage period.

The ac drive circuit 20 may continuously decrease the common signal VCOM by the predetermined amount throughout the memory period.

In the example of fig. 14, the case where the present embodiment is applied to the operation of embodiment 1 is described as an example, but the present embodiment may be applied to the operation of embodiment 2 or embodiment 3.

While the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

For example, the structures disclosed in the respective embodiments may be combined as appropriate.

Further, although the display device having the functions of the analog mode and the digital mode is disclosed in each embodiment, the operation of the display device in each embodiment can be applied to a display device having only the function of the digital mode.