阅读说明：本技术 一种提高光电探测器芯片产出量的制备工艺方法 (Preparation process method for improving output of photoelectric detector chip ) 是由 王权兵 王丹 徐之韬 余沛 于 2019-10-23 设计创作，主要内容包括：本发明公开了一种提高光电探测器芯片产出量的制备工艺方法,首先在外延片上完成欧姆环光刻和腐蚀,并进行SiO<Sub>2</Sub>扩散阻挡膜沉积,然后开扩散孔并进行导电介质扩散,导电介质扩散完成后再进行SiNx增透膜沉积,光刻P窗口和解理道,蚀刻P窗口和解理道,并进行退火处理；然后再进行P电极和N电极的制作。本发明可提高制作光电探测器芯片的性能和稳定性,使芯片产出率提高30％以上,大大提高了光电探测器芯片的生产效率,有效节约生产成本。(The invention discloses a preparation process method for improving the output of a photoelectric detector chip, which comprises the steps of firstly completing photoetching and corrosion of an ohmic ring on an epitaxial wafer and carrying out SiO (silicon dioxide) etching 2 Depositing a diffusion barrier film, then forming diffusion holes and conducting medium diffusion, then depositing a SiNx antireflection film, photoetching a P window and a cleavage path, etching the P window and the cleavage path, and annealing after the conducting medium diffusion is finished; then, the P electrode and the N electrode are manufactured. The invention can improve the performance and stability of manufacturing the photoelectric detector chip, improve the output rate of the chip by more than 30 percent, greatly improve the production efficiency of the photoelectric detector chip and effectively save the production cost.)

1. A preparation process method for improving the output of a photoelectric detector chip is characterized by comprising the following steps:

s1, cleaning the epitaxial wafer, and photoetching and corroding the ohmic contact ring;

S2、SiO₂depositing a diffusion barrier film, photoetching and etching diffusion holes, and diffusing a conductive medium to form a Zn diffusion region;

s3, depositing a SiNx antireflection film, photoetching a P window and a cleavage street, etching the P window and the cleavage street, and annealing;

s4, carrying out P electrode photoetching and evaporation, thinning the bottom of the epitaxial wafer, and carrying out N electrode evaporation at the bottom of the epitaxial wafer;

and S5, detecting each single chip of the whole wafer, and cleaving the whole wafer into single detector chips.

2. The manufacturing method according to claim 1, wherein the ohmic contact ring in step S1 is etched by a wet etching process using a photolithography apparatus for photolithography.

3. The preparation process method according to claim 1, wherein the step S2 is implemented by the following steps:

s21, use of PECVD process for depositing SiO₂Diffusion barrier film of SiO₂The thickness of the diffusion barrier film is 2000-7000 Å;

s22, photoetching of diffusion holes by using photoetching equipment, wherein the size of the diffusion holes is phi 150-250 mu m;

s23, etching the diffusion holes by using an RIE dry etching process;

s24, conducting conductive medium diffusion, and carrying out Zn doping by using a high-temperature diffusion furnace to form a Zn diffusion zone, wherein the surface concentration range of the Zn diffusion zone is 5E 17-2E 18cm^-3。

4. The preparation process method according to claim 1, wherein the step S3 is implemented by the following steps:

s31, depositing a SiNx anti-reflection film by using a PECVD (plasma enhanced chemical vapor deposition) process, wherein the thickness of the SiNx anti-reflection film is 1600-1900 Å;

s32, photoetching a P window and a cleavage street by using photoetching equipment, wherein the size of the cleavage street is 20-40 mu m;

s33, etching the P window and the cleavage street by using an RIE dry etching process;

and S34, after the etching is finished, carrying out high-temperature furnace annealing treatment, wherein the annealing temperature is 300-500 ℃, and the annealing time is 1-3 min.

5. The manufacturing method according to claim 1, wherein the evaporation of the P-electrode and the N-electrode in step S4 is performed by an electron beam evaporation apparatus.

6. The preparation process method according to claim 1, wherein the thickness of the bottom of the extension sheet in the step S4 is reduced to 120-180 μm.

Technical Field

The invention relates to a semiconductor manufacturing technology, in particular to a preparation process method for improving the output of a photoelectric detector chip.

Background

The rapid development of optical fiber communication gradually replaces the traditional information communication mode using electrons as carriers, and uses photons as propagation carriers to realize the huge increase of communication capacity. The explosion of data transmission quantity puts higher requirements on the response speed and the sensitivity of the photoelectric device. As a key module for detecting optical signals in an optical receiver, performance and process research of a photodetector has become a problem of important attention of relevant organizations. The performance of the photodetector determines its detection effect and also determines the signal transmission quality of the entire optical fiber communication system. Therefore, designing a high-stability and high-performance photoelectric detector and solving the problem of the production and processing technology thereof are the main concerns of the current optical communication photoelectric detection system.

The basic working principle of the semiconductor photoelectric detector is as follows:

the semiconductor photoelectric detector is a core device which is made of InGaAs/InP material and can receive and detect optical signals. When light irradiates the active region of the device, it converts the optical signal into an electrical signal, i.e., when light irradiates, if the energy of a photon is greater than or equal to the forbidden bandwidth of the semiconductor, the photon jumps the electron in the valence band to the conduction band, so that an electron appears in the conduction band and a hole appears in the valence band. Under the further action of the electric field, electrons drift to the N region in the depletion region, and holes drift to the P region in the depletion region, so that free electron-hole pairs (photo-generated carriers for short) are generated. The high electric field in the depletion region causes the electron-hole pairs to split immediately and flow in the reverse biased junction region towards both ends and then be absorbed at the boundary, thereby forming a photocurrent in the external circuit.

Dark current is an important parameter of a photoelectric detector, and the dark current becomes large, so that the noise power of the detector becomes large, the detection sensitivity is reduced, and the detection performance of the detector is seriously influenced. The dark current performance of the photoelectric detector is related to the structural design of the detector, and more particularly, the manufacturing process of the photoelectric detector. How to effectively control the magnitude of the dark current of the photodetector through the research of the manufacturing process method has become a research focus of many research institutions in recent years. With the rapid development of the optical fiber communication technology, the demand of the photoelectric detector is increasing, and how to control the cost on the basis of ensuring the product quality also becomes a key point of attention of enterprises.

In the conventional process, cleavage lines are generally opened and participate in the diffusion process at the same time. In order to further reduce the chip production cost, the chip yield of a single epitaxial wafer must be increased, so that the chip size must be considered to be more compact, but when the sizes of the cleavage channel and the diffusion hole are closely separated, there is a certain risk that a depletion region is generated when the two diffusion regions (the cleavage region and the diffusion region) are closely separated under the action of an applied voltage, so that a current channel (i.e., a current leakage channel) is formed by carriers, and a larger current leakage is generated. Further, considering that the cleavage region and the active diffusion region are simultaneously opened, the size of a single chip becomes large, and the yield of the entire chip is lowered.

Disclosure of Invention

The invention aims to solve the technical problems of large dark current, poor stability and low production efficiency in the prior art and provides a preparation process method for improving the output of a photoelectric detector chip.

The technical scheme adopted by the invention for solving the technical problems is as follows:

the preparation process method for improving the yield of the photoelectric detector chip comprises the following steps:

s1, cleaning the epitaxial wafer, and photoetching and corroding the ohmic contact ring;

S2、SiO₂depositing a diffusion barrier film, photoetching and etching diffusion holes, and diffusing a conductive medium to form a Zn diffusion region;

s3, depositing a SiNx antireflection film, photoetching a P window and a cleavage street, etching the P window and the cleavage street, and annealing;

s4, carrying out P electrode photoetching and evaporation, thinning the bottom of the epitaxial wafer, and carrying out N electrode evaporation at the bottom of the epitaxial wafer;

and S5, detecting each single chip of the wafer, and cleaving the wafer into single detector chips.

In connection with the above technical solution, the ohmic contact ring in step S1 is subjected to photolithography by using a photolithography apparatus, and is etched by using a wet etching process.

In connection with the above technical solution, the specific implementation of step S2 includes the following steps:

s21 deposition of SiO by PECVD process₂Diffusion barrier film of SiO₂The diffusion barrier film has a thickness of

S22, photoetching diffusion holes with the size of phi 150-250 microns by utilizing photoetching equipment;

s23, etching the diffusion holes by using an RIE dry etching process;

s24, conducting conductive medium diffusion, and carrying out Zn doping by using a high-temperature diffusion furnace to form a Zn diffusion zone, wherein the surface concentration range of the Zn diffusion zone is 5E 17-2E 18cm^-3。

In connection with the above technical solution, the specific implementation of step S3 includes the following steps:

s31, depositing a SiNx anti-reflection film by using a PECVD process, wherein the thickness of the SiNx anti-reflection film is

S32, photoetching a P window and a cleavage street by using photoetching equipment, wherein the size of the cleavage street is 20-40 mu m;

s33, etching the P window and the cleavage street by using an RIE dry etching process;

and S34, after the etching is finished, carrying out high-temperature furnace annealing treatment, wherein the annealing temperature is 300-500 ℃, and the annealing time is 1-3 min.

In the above technical solution, the evaporation of the P electrode and the N electrode in the step S4 is performed by using an electron beam evaporation apparatus.

In connection with the above technical solution, in the step S4, the thickness of the bottom of the outer extension sheet is reduced to 120 to 180 μm.

The invention has the following beneficial effects: according to the preparation process method of the photoelectric detector, the photoetching and etching of the cleavage channel and the photoetching and etching of the diffusion hole are separately carried out, so that the cleavage area does not participate in the diffusion process at all, a leakage current channel formed by a photon-generated carrier formed in the diffusion hole and a carrier formed in the cleavage channel can be avoided at all, the performance and the stability of the manufactured photoelectric detector chip are improved, meanwhile, the distance between the chips can be further reduced, the yield of the chip is improved by more than 30%, the production efficiency of the photoelectric detector chip is greatly improved, and the production cost is effectively saved.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a process flow diagram of a photodetector chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a diffusion process for a photodetector chip according to an embodiment of the present invention;

FIG. 3 is a process diagram of a photodetector chip process flow according to an embodiment of the present invention;

FIG. 4 is a process diagram of a conventional fabrication process flow for a photodetector;

FIG. 5 is a graph of dark current versus diffusion spacing for an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1, the preparation method for improving the yield of the photodetector chip according to the embodiment of the present invention includes the following steps:

s1, cleaning the epitaxial wafer, and photoetching and corroding the ohmic contact ring 7;

S2、SiO₂depositing a diffusion barrier film 3, carrying out photoetching and etching on the diffusion holes 2, and carrying out conductive medium diffusion to form a Zn diffusion region 6;

s3, depositing a SiNx antireflection film 4, photoetching a P window 9 and a cleavage path 1, etching the P window 9 and the cleavage path 1, and annealing;

s4, carrying out photoetching and evaporation on the P electrode 5, thinning the bottom of the epitaxial wafer, and then carrying out evaporation on the N electrode at the bottom of the epitaxial wafer;

and S5, detecting each single chip of the whole wafer, and cleaving the whole wafer into single detector chips.

As shown in fig. 3, the photo-etching and etching of the cleavage channel 1 and the photo-etching and etching of the diffusion hole 2 are performed separately, so that the cleavage region does not participate in the diffusion process at all, the photo-generated carriers formed in the diffusion hole 2 and the leakage current channel 8 formed by the carriers in the cleavage channel 1 can be avoided completely, the performance and stability of the photo-detector chip can be improved, the chip pitch can be further reduced, the size of a single chip can be designed to 285um under the condition that the size of the photosensitive surface (such as 200um) is not changed, the chip yield can be improved by more than 30%, the production efficiency of the photo-detector chip is greatly improved, and the production cost is effectively saved. In the invention, the cleavage path 1 is not opened in the process of opening the diffusion hole 2, so that SiO on the whole Wafer₂The diffusion barrier films 3 are connected into a whole, the vector sum of various forces in the diffusion barrier films is not zero, so the stress is very large, and the annealing treatment is carried out after the photoetching and etching of the P window 9 and the cleavage path 1 are finished, thereby effectively eliminating SiO₂The stress of the barrier film 3 is diffused.

As shown in fig. 4, in the conventional fabrication process of the photodetector, the photolithography and etching of the cleavage street 1 and the photolithography and etching of the diffusion hole 2 are performed simultaneously, and the cleavage street 1 and the diffusion hole 2 participate in the diffusion process simultaneously. Due to the existence of the cleavage site 1, the doped Zn atoms diffuse into the P region diffusion holes and also diffuse towards the inner side of the cleavage site 1. Under the action of an external voltage, a depletion region is generated when two diffusion regions (a cleavage region and a diffusion region) are closely separated, so that a photogenerated carrier forms an electric leakage current channel 8, and then a larger leakage current is generated, so that the dark current of the photoelectric detector is greatly increased, and the reliability of the photoelectric detector chip has a greater risk. The cleavage channels 1 are opened at the same time when the diffusion holes 2 are opened, but no leakage current can be ensured only by ensuring that the distance between the diffusion holes 2 and the cleavage channels 1 is more than 25um, so that the size of a single chip is increased, and the whole chip yield is reduced.

Further, the ohmic contact ring 7 in step S1 is subjected to photolithography using a photolithography apparatus and is etched using a wet etching process.

Further, as shown in fig. 2, the specific implementation of step S2 includes the following steps:

s21 deposition of SiO by PECVD process₂ Diffusion barrier film 3, SiO₂The diffusion barrier film 3 has a thickness of

S22, photoetching the diffusion holes 2 by using photoetching equipment, wherein the size of the diffusion holes 2 is phi 150-250 mu m;

s23, etching the diffusion holes 2 by using an RIE dry etching process;

s24, conducting conductive medium diffusion, and carrying out Zn doping by using a high-temperature diffusion furnace to form a Zn diffusion zone 6, wherein the surface concentration range of the Zn diffusion zone 6 is 5E 17-2E 18cm^-3。

Further, as shown in fig. 2, the specific implementation of step S3 includes the following steps:

s31, depositing the SiNx antireflection film 4 by using a PECVD process, wherein the thickness of the SiNx antireflection film 4 is equal to

S32, photoetching a P window and a cleavage street 1 by using photoetching equipment, wherein the size of the cleavage street 1 is 20-40 mu m;

s33, etching the P window and the cleavage path 1 by using an RIE dry etching process;

and S34, after the etching is finished, carrying out high-temperature furnace annealing treatment, wherein the annealing temperature is 300-500 ℃, and the annealing time is 1-3 min. After the photoetching and etching of the P window 9 and the cleavage street 1 are finished, annealing treatment is carried out, which can effectively eliminate SiO₂The stress of the barrier film 3 is diffused.

Further, the evaporation of the P electrode 5 and the N electrode in step S4 uses an electron beam evaporation apparatus.

Further, in step S4, the thickness of the bottom of the extension sheet is reduced to 120-180 μm.

The photoelectric detector is manufactured by the manufacturing process method of the photoelectric detector, single chip detection is carried out after the manufacturing process is finished, the relationship between the measured distance between the cleavage region and the diffusion region of the chip and the dark current of the chip is shown in figure 5, and when the distance is more than 25um, the index of the dark current can be made to be very small (less than 1 nA).

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.