Oxide semiconductor device and method for manufacturing oxide semiconductor device
阅读说明:本技术 氧化物半导体装置以及氧化物半导体装置的制造方法 (Oxide semiconductor device and method for manufacturing oxide semiconductor device ) 是由 汤田洋平 绵引达郎 古川彰彦 于 2018-06-08 设计创作,主要内容包括:在抑制异种材料向肖特基界面扩散的同时,提高被施加反向电压时的耐压。氧化物半导体装置具备:n型的氧化镓外延层(2);p型的氧化物半导体层(5),是与氧化镓外延层的材料不同的材料的氧化物;电介体层(7),以覆盖氧化物半导体层的侧面的至少一部分的方式形成;阳极电极(4);以及阴极电极(3),在氧化物半导体层的下表面与氧化镓基板(1)之间或者氧化物半导体层(5a)的下表面与氧化镓外延层(2)之间形成异质pn结。(The diffusion of a different material to a Schottky interface is suppressed, and the withstand voltage when a reverse voltage is applied is improved. The oxide semiconductor device includes: an n-type gallium oxide epitaxial layer (2); a p-type oxide semiconductor layer (5) which is an oxide of a material different from that of the gallium oxide epitaxial layer; a dielectric layer (7) formed so as to cover at least a part of a side surface of the oxide semiconductor layer; an anode electrode (4); and a cathode electrode (3) that forms a hetero-pn junction between the lower surface of the oxide semiconductor layer and the gallium oxide substrate (1) or between the lower surface of the oxide semiconductor layer (5a) and the gallium oxide epitaxial layer (2).)
1. An oxide semiconductor device includes:
an n-type gallium oxide epitaxial layer (2) formed on the upper surface of the n-type gallium oxide substrate (1);
a p-type oxide semiconductor layer (5, 5a) which is formed at least from the upper surface to the inside of the gallium oxide epitaxial layer (2) and is an oxide of a material different from that of the gallium oxide epitaxial layer (2);
a dielectric layer (7, 7a, 7b) that is formed so as to cover at least a part of a side surface of the oxide semiconductor layer (5, 5a) and is made of a material having a dielectric constant lower than that of the material constituting the oxide semiconductor layer (5, 5 a);
an anode electrode (4) which is formed on the upper surface of the gallium oxide epitaxial layer (2) and forms a Schottky junction with the gallium oxide epitaxial layer (2); and
a cathode electrode (3) formed on the lower surface of the gallium oxide substrate (1) and in ohmic contact with the gallium oxide substrate (1),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5) and the gallium oxide substrate (1) or between the lower surface of the oxide semiconductor layer (5a) and the gallium oxide epitaxial layer (2).
2. The oxide semiconductor device according to claim 1,
the side surfaces of the oxide semiconductor layers (5, 5a) are surfaces along a current flow direction that is a direction connecting the anode electrode (4) and the cathode electrode (3).
3. The oxide semiconductor device according to claim 1 or 2, wherein,
the lower surfaces of the dielectric layers (7a, 7b) are located shallower than the lower surfaces of the oxide semiconductor layers (5, 5 a).
4. The oxide semiconductor device according to claim 1 or 2, wherein,
the dielectric layers (7, 7a) are formed so as to cover the entire side surfaces of the oxide semiconductor layers (5, 5 a).
5. The oxide semiconductor device according to any one of claims 1 to 4,
the oxide semiconductor layer (5a) is formed from the upper surface to the inside of the gallium oxide epitaxial layer (2),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5a) and the gallium oxide epitaxial layer (2).
6. The oxide semiconductor device according to any one of claims 1 to 4,
the oxide semiconductor layer (5) is formed from the upper surface to the lower surface of the gallium oxide epitaxial layer (2),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5) and the gallium oxide substrate (1).
7. The oxide semiconductor device according to any one of claims 1 to 6,
the impurity concentration of the gallium oxide epitaxial layer (2) is lower than that of the gallium oxide substrate (1).
8. The oxide semiconductor device according to any one of claims 1 to 7,
the oxide semiconductor layer (5, 5a) is a metal oxide containing Cu or Ni.
9. A method for manufacturing an oxide semiconductor device, wherein,
a cathode electrode (3) which is ohmically bonded to the gallium oxide substrate (1) is formed on the lower surface of the n-type gallium oxide substrate (1),
epitaxially growing an n-type gallium oxide epitaxial layer (2) on the upper surface of the gallium oxide substrate (1),
forming a groove portion (10) extending from the upper surface of the gallium oxide epitaxial layer (2) to at least the inside,
forming dielectric layers (7, 7a, 7b) on at least a part of side surfaces of the groove (10),
forming p-type oxide semiconductor layers (5, 5a) which are oxides of a material different from the material of the gallium oxide epitaxial layer (2) and are made of a material having a higher dielectric constant than the dielectric layers (7, 7a, 7b) in the groove portions (10) in a state in which the dielectric layers (7, 7a, 7b) are formed on the side surfaces thereof,
an anode electrode (4) which is in Schottky junction with the gallium oxide epitaxial layer (2) is formed on the upper surface of the gallium oxide epitaxial layer (2),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5) and the gallium oxide substrate (1) or between the lower surface of the oxide semiconductor layer (5a) and the gallium oxide epitaxial layer (2).
10. The method for manufacturing an oxide semiconductor device according to claim 9,
the oxide semiconductor layer (5, 5a) is formed at a formation temperature of 200 ℃ or lower.
11. The method for manufacturing an oxide semiconductor device according to claim 9 or 10,
forming a groove portion (10) reaching the inside from the upper surface of the gallium oxide epitaxial layer (2),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5a) and the gallium oxide epitaxial layer (2).
12. The method for manufacturing an oxide semiconductor device according to claim 9 or 10,
forming a groove portion (10) extending from the upper surface to the lower surface of the gallium oxide epitaxial layer (2),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5) and the gallium oxide substrate (1).
13. A method for manufacturing an oxide semiconductor device, wherein,
a cathode electrode (3) which is ohmically bonded to the gallium oxide substrate (1) is formed on the lower surface of the n-type gallium oxide substrate (1),
epitaxially growing an n-type 1 st gallium oxide epitaxial layer (2a) on the upper surface of the gallium oxide substrate (1),
a p-type oxide semiconductor layer (5a) which is an oxide of a material different from that of the 1 st gallium oxide epitaxial layer (2a) is partially formed on the upper surface of the 1 st gallium oxide epitaxial layer (2a),
forming a dielectric layer (7, 7a, 7b) made of a material having a dielectric constant smaller than that of the material constituting the oxide semiconductor layer (5a) on at least a part of a side surface of the oxide semiconductor layer (5a),
epitaxially growing an n-type 2 nd gallium oxide epitaxial layer (2b) so as to cover the 1 st gallium oxide epitaxial layer (2a), the oxide semiconductor layer (5a), and the dielectric layers (7, 7a, 7b),
an anode electrode (4) which is in Schottky junction with the 2 nd gallium oxide epitaxial layer (2b) is formed on the upper surface of the 2 nd gallium oxide epitaxial layer (2b),
a hetero pn junction is formed between the lower surface of the oxide semiconductor layer (5a) and the upper surface of the 1 st gallium oxide epitaxial layer (2 a).
14. An oxide semiconductor device includes:
an n-type gallium oxide epitaxial layer (2c) formed on the upper surface of the n-type gallium oxide substrate (1);
a p-type oxide semiconductor layer (5c) which is formed at least from the upper surface to the inside of the gallium oxide epitaxial layer (2c) and is an oxide of a material different from that of the gallium oxide epitaxial layer (2 c);
a dielectric layer (7c) that is formed so as to cover at least a part of a side surface of the oxide semiconductor layer (5c) and is made of a material having a dielectric constant lower than that of the material that constitutes the oxide semiconductor layer (5 c);
a source electrode (11) which is formed on the upper surface of the gallium oxide epitaxial layer (2c) and is directly bonded to the gallium oxide epitaxial layer (2c) and the oxide semiconductor layer (5 c);
a gate electrode (12) in contact with the gallium oxide epitaxial layer (2c) and the oxide semiconductor layer (5c) through the dielectric layer (7 c); and
a drain electrode (13) formed on the lower surface of the gallium oxide substrate (1) and directly bonded to the gallium oxide substrate (1),
a hetero pn junction is formed between the lower surface of the gallium oxide epitaxial layer (2c) and the gallium oxide substrate (1).
Technical Field
The technology disclosed in the present specification relates to an oxide semiconductor device and a method for manufacturing the oxide semiconductor device.
Background
Power Electronics (PE) is a technology for rapidly and efficiently converting dc, ac, or frequency, and is a term representing a technology that integrates recent semiconductor-based electronic engineering (electronic engineering) and control engineering (control engineering) in addition to conventional power engineering (power engineering).
PE is a technology that is currently applied to power utilization, industrial utilization, transportation, household utilization, and other power utilization scenarios.
In recent years, the percentage of electric energy in the total energy consumption, that is, the power factor, has been increasing in japan as well as in the world. In recent years, devices excellent in convenience and energy saving have been developed for use of electric power, and the utilization rate of electric power has been improved. The technology that underlies these foundations is PE technology.
In addition, the PE technology can also be said to be the following technology: the electric state (for example, the magnitude of frequency, current, or voltage) to be converted is converted into an electric state suitable for the device to be used, regardless of the state. The basic elements in PE technology are a rectifier and an inverter. These elements are based on semiconductors, and are semiconductor elements such as diodes and transistors using semiconductors.
In the PE field, diodes as semiconductor rectifier devices are currently used for various applications including electrical devices. Also, the diode is applied to a wide range of frequency bands.
In recent years, switching elements which can operate at high frequencies with low loss have been developed and put to practical use for applications with high withstand voltage and large capacity. In addition, the material used is also changed to a wide band gap material, and high withstand voltage of the device is achieved.
Typical examples of such diodes include Schottky Barrier Diodes (SBDs) and pn diodes (PNDs), and these diodes are widely used for various applications.
For example, a semiconductor device having a merged P-i-n/schottky diode (MPS, hybrid P-i-n schottky diode) structure in which a schottky junction and a pn junction are provided as exemplified in
In the MPS structure, a surge current larger than a rated value can be caused to flow with a small voltage drop as compared with the case of the SBD alone by bipolar operation of the PND. Thus, in the MPS configuration, the forward surge tolerance is improved. Thus, a semiconductor device having a rectifying function with high forward surge tolerance while suppressing an increase in forward voltage drop has been developed.
Further, as exemplified in
Disclosure of Invention
In the semiconductor device exemplified in
In the semiconductor device using SiC exemplified in
The technology disclosed in the present specification has been made to solve the above-described problems, and an object thereof is to provide a technology for improving a withstand voltage when a reverse voltage is applied while suppressing diffusion of a dissimilar material to a schottky interface in an oxide semiconductor device formed of an oxide semiconductor material.
The technology disclosed in the present specification, according to
In addition, according to the 2 nd aspect of the technology disclosed in the present specification, a cathode electrode that is ohmically bonded to an n-type gallium oxide substrate is formed on a lower surface of the n-type gallium oxide substrate, an n-type gallium oxide epitaxial layer is epitaxially grown on an upper surface of the gallium oxide substrate to form a groove portion that extends from the upper surface of the gallium oxide epitaxial layer to at least an inner portion, a dielectric layer is formed on at least a part of a side surface of the groove portion, a p-type oxide semiconductor layer that is an oxide of a material different from the material of the gallium oxide epitaxial layer and is made of a material having a higher dielectric constant than the dielectric layer is formed in the groove portion in a state in which the dielectric layer is formed on the side surface, and an anode electrode that is schottky-bonded to the gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide epitaxial layer, and forming a hetero pn junction between the lower surface of the oxide semiconductor layer and the gallium oxide substrate or between the lower surface of the oxide semiconductor layer and the gallium oxide epitaxial layer.
In addition, according to the 3 rd aspect of the technology disclosed in the present specification, a cathode electrode that is ohmically bonded to an n-type gallium oxide substrate is formed on a lower surface of the n-type gallium oxide substrate, an n-
In addition, the 4 th aspect of the technology disclosed in the present specification includes: an n-type gallium oxide epitaxial layer formed on the upper surface of the n-type gallium oxide substrate; a p-type oxide semiconductor layer which is formed at least from the upper surface to the inside of the gallium oxide epitaxial layer and is an oxide of a material different from that of the gallium oxide epitaxial layer; a dielectric layer formed so as to cover at least a part of a side surface of the oxide semiconductor layer, and made of a material having a dielectric constant lower than that of the material constituting the oxide semiconductor layer; a source electrode formed on an upper surface of the gallium oxide epitaxial layer and directly bonded to the gallium oxide epitaxial layer and the oxide semiconductor layer; a gate electrode in contact with the gallium oxide epitaxial layer and the oxide semiconductor layer through the dielectric layer; and a drain electrode formed on a lower surface of the gallium oxide substrate and directly bonded to the gallium oxide substrate, wherein a hetero-pn junction is formed between the lower surface of the gallium oxide epitaxial layer and the gallium oxide substrate.
The technology disclosed in the present specification, according to
In addition, according to the 2 nd aspect of the technology disclosed in the present specification, a cathode electrode that is ohmically bonded to an n-type gallium oxide substrate is formed on a lower surface of the n-type gallium oxide substrate, an n-type gallium oxide epitaxial layer is epitaxially grown on an upper surface of the gallium oxide substrate to form a groove portion that extends from the upper surface of the gallium oxide epitaxial layer to at least an inner portion, a dielectric layer is formed on at least a part of a side surface of the groove portion, a p-type oxide semiconductor layer that is an oxide of a material different from the material of the gallium oxide epitaxial layer and is made of a material having a higher dielectric constant than the dielectric layer is formed in the groove portion in a state in which the dielectric layer is formed on the side surface, and an anode electrode that is schottky-bonded to the gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide epitaxial layer, and forming a hetero pn junction between the lower surface of the oxide semiconductor layer and the gallium oxide substrate or between the lower surface of the oxide semiconductor layer and the gallium oxide epitaxial layer. With this structure, in the manufacture of an oxide semiconductor device in which a heterogeneous pn junction is formed from different oxide semiconductor materials, a p-type semiconductor layer can be formed without performing p-type carrier concentration control by adding a p-type impurity. Specifically, the above structure can be realized by forming a groove portion in an n-type gallium oxide epitaxial layer and forming a dielectric layer and a p-type oxide semiconductor layer in the groove portion.
In addition, according to the 3 rd aspect of the technology disclosed in the present specification, a cathode electrode that is ohmically bonded to an n-type gallium oxide substrate is formed on a lower surface of the n-type gallium oxide substrate, an n-
In addition, the 4 th aspect of the technology disclosed in the present specification includes: an n-type gallium oxide epitaxial layer formed on the upper surface of the n-type gallium oxide substrate; a p-type oxide semiconductor layer which is formed at least from the upper surface to the inside of the gallium oxide epitaxial layer and is an oxide of a material different from that of the gallium oxide epitaxial layer; a dielectric layer formed so as to cover at least a part of a side surface of the oxide semiconductor layer, and made of a material having a dielectric constant lower than that of the material constituting the oxide semiconductor layer; a source electrode formed on an upper surface of the gallium oxide epitaxial layer and directly bonded to the gallium oxide epitaxial layer and the oxide semiconductor layer; a gate electrode in contact with the gallium oxide epitaxial layer and the oxide semiconductor layer through the dielectric layer; and a drain electrode formed on a lower surface of the gallium oxide substrate and directly bonded to the gallium oxide substrate, wherein a hetero-pn junction is formed between the lower surface of the gallium oxide epitaxial layer and the gallium oxide substrate. With such a configuration, in an oxide semiconductor device in which a heterogeneous pn junction is formed of a different oxide semiconductor material, diffusion of the different material to a schottky interface is suppressed, and a withstand voltage when a reverse voltage is applied can be improved.
Objects, features, aspects and advantages related to the technology disclosed in the present specification will become more apparent from the detailed description and the accompanying drawings shown below.
Drawings
Fig. 1 is a plan view schematically illustrating a structure for realizing a semiconductor device according to an embodiment.
Fig. 2 is a cross-sectional view schematically illustrating the structure of the semiconductor device in section I-I' of fig. 1.
Fig. 3 is a sectional view schematically illustrating the structure of the semiconductor device according to the embodiment.
Fig. 4 is a sectional view schematically illustrating the structure of the semiconductor device according to the embodiment.
Fig. 5 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 6 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 7 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 8 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 9 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 10 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 11 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment.
Fig. 12 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 13 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 14 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 15 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 16 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 17 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 18 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 19 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 20 is a sectional view illustrating a manufacturing process of a semiconductor device according to the embodiment.
Fig. 21 is a sectional view schematically illustrating the structure of the semiconductor device according to the embodiment.
Fig. 22 is a sectional view schematically illustrating the structure of the semiconductor device according to the embodiment.
(symbol description)
1: an n-type gallium oxide substrate; 2. 2a, 2b, 2 c: an n-type gallium oxide epitaxial layer; 3: a cathode electrode; 4: an anode electrode; 5. 5a, 5 c: a p-type oxide semiconductor layer; 6: a dielectric layer for a field plate (field plate); 7. 7a, 7b, 7 c: a dielectric layer; 10: a groove part; 11: a source electrode; 12: a gate electrode; 13: and a drain electrode.
Detailed Description
Hereinafter, embodiments will be described with reference to the accompanying drawings.
The drawings are schematically illustrated, and the configuration is omitted or simplified as appropriate for the convenience of explanation. The mutual relationship between the size and the position of the structures and the like shown in the different drawings is not necessarily described correctly, and may be appropriately changed.
In the following description, the same components are denoted by the same reference numerals, and the same names and functions are assumed. Therefore, detailed descriptions thereof may be omitted to avoid redundancy.
In the following description, terms such as "upper", "lower", "left", "right", "side", "bottom", "table", and "back" may be used to indicate specific positions and directions, but these terms are used for ease of understanding the contents of the embodiments and are used for convenience of description, and are not related to the directions in actual implementation.
In the following description, ordinal numbers such as "1 st" and "2 nd" may be used, but these terms are used for ease of understanding the contents of the embodiments and are not limited to the order in which the ordinal numbers can be generated.
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The following describes an oxide semiconductor device and a method for manufacturing the oxide semiconductor device according to this embodiment.
< Structure of oxide semiconductor device >
First, the structure of the semiconductor device according to this embodiment will be described.
Fig. 1 is a plan view schematically illustrating a structure for realizing a semiconductor device according to this embodiment. Fig. 2 is a cross-sectional view schematically illustrating the structure of the semiconductor device in section I-I' of fig. 1.
As illustrated in fig. 1 and 2, the semiconductor device according to the present embodiment is provided with a Schottky Barrier Diode (SBD) and a MPS of a pn junction diode (PND) at the same time.
In this embodiment, a schottky barrier diode in which the 1 st electrode is an anode electrode and the 2 nd electrode is a cathode electrode is described as a semiconductor device, but the semiconductor device is not limited to the schottky barrier diode and may be a semiconductor device constituting another switching element.
As illustrated in fig. 2, an n-type
The semiconductor device further includes a plurality of p-type oxide semiconductor layers 5, and the plurality of p-type oxide semiconductor layers 5 are formed from the upper surface of the n-type gallium
The semiconductor device further includes a field
The semiconductor device further includes a dielectric layer 7, and the dielectric layer 7 is formed on the entire surface of the contact surface between the n-type gallium
The n-type
That is, the n-type
The n-type carrier concentration of the n-type
An n-type gallium
The
Such a metal material may be, for example, titanium (Ti). The
The
Examples of such a metal material include platinum (Pt), nickel (Ni), gold (Au), and palladium (Pd). The
The p-type oxide semiconductor layer 5 is formed from the upper surface to the lower surface of the n-type gallium
In addition, the p-type oxide semiconductor layer 5 may be made of Cu2O、Ag2O, NiO or SnO containing indium oxide (In)2O3) Gallium oxide (Ga)2O3) Or a p-type oxide semiconductor of zinc oxide (ZoN). The p-type oxide semiconductor layer 5 is formed of a p-type oxide semiconductor which exhibits p-type conductivity without adding a p-type impurity as described above, but a p-type impurity may be added.
For example, in Cu2In O, nitrogen (N) can be used as a p-type impurity. When a p-type impurity is added, the total of the absence of metal atoms in the p-type oxide semiconductor and the p-type impurity becomes the p-type carrier concentration. Therefore, the p-type oxide semiconductor layer 5 contains a p-type impurity, and even if the metal oxide of the p-type oxide semiconductor is oxidized to lose the p-type conductivity, the p-type oxide semiconductor may exhibit the p-type conductivity as a wholeSince the p-type conductivity of the entire oxide semiconductor is reduced, it is important not to oxidize the metal oxide of the p-type oxide semiconductor.
The field
The dielectric layer 7 is made of, for example, silicon dioxide (SiO)2) Silicon nitride (SiN), gallium nitride (GaN) or aluminum oxide (Al)2O3) And the like. The dielectric layer 7 is formed so as to cover the entire side surface of the p-type oxide semiconductor layer 5, that is, the entire surface along the current direction which is the direction connecting the
In addition, the thickness of the dielectric layer 7 is preferably 3nm or more, and may be 3nm or more and 300nm or less, for example, particularly when the metal oxide included in the p-type oxide semiconductor layer 5 and the metal oxide forming the mixed crystal material are included.
< method for manufacturing oxide semiconductor device >
Next, a method for manufacturing a semiconductor device according to this embodiment will be described.
First,
Next, an n-type gallium
Next, a metal material to be the
Thereafter, a heat treatment is performed at 550 ℃ for 5 minutes, for example, in a nitrogen atmosphere or an oxygen atmosphere. As a result,
As a method for reducing the contact resistance between the n-type
Here, as a method for forming the p-type oxide semiconductor layer 5 and the dielectric layer 7, there are 2 methods. The 1 st method is as follows: a groove portion is formed in the n-type gallium
For example, in the 2 nd method, in the reaction of Cu2In the case where O forms the p-type oxide semiconductor layer 5, argon (Ar) gas and nitrogen (N)2) In the mixed gas of gases, by mixing Cu2O is used for sputtering of a target (target), and Cu is deposited on the 1 st principal surface of the n-type gallium oxide substrate 12O, thereby enabling p to be formedAnd a type oxide semiconductor layer 5.
By increasing the N of the gas mixture2The carrier concentration of the p-type oxide semiconductor layer 5 can be increased to increase the p-type conductivity. In addition, by reducing the N of the mixed gas2The carrier concentration of the p-type oxide semiconductor layer 5 can be reduced to reduce the p-type conductivity.
In addition, in the 1 st method, as a method of forming a groove portion in the n-type gallium
The method for forming the dielectric layer 7 is not particularly limited, and an existing method such as a sputtering method or a CVD method can be used. The thickness of the dielectric layer 7 in the horizontal direction of the device is preferably a thickness that can prevent diffusion of metal atoms from the p-type oxide semiconductor layer 5 and that does not suppress the expansion of the depletion layer as much as possible.
<
An oxide semiconductor device and a method for manufacturing the oxide semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
< Structure of oxide semiconductor device >
Fig. 3 is a sectional view schematically illustrating the structure of the semiconductor device according to this embodiment. In the semiconductor device illustrated in fig. 3, the length of the
As illustrated in fig. 3, the length of the
<
An oxide semiconductor device and a method for manufacturing the oxide semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
< Structure of oxide semiconductor device >
Fig. 4 is a sectional view schematically illustrating the structure of the semiconductor device according to this embodiment. In the semiconductor device illustrated in fig. 4, the length of the p-type
As illustrated in fig. 4, the length of the
< method for manufacturing oxide semiconductor device >
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to fig. 5 to 20. Fig. 5 to 20 are sectional views illustrating a manufacturing process of the semiconductor device according to the present embodiment.
As described above, there are 2 methods as methods for forming the p-type
First, as for the
Next, as illustrated in fig. 7, an n-type gallium
Next, as illustrated in fig. 8, a
Next, as illustrated in fig. 9,
Next, as illustrated in fig. 11, a field
Next, as illustrated in fig. 12, the
According to the above manufacturing method, the p-type
In the above-described manufacturing method, the n-type gallium
Next, the 2 nd method is explained. First, as illustrated in fig. 13, an n-type
Next, as illustrated in fig. 15, an n-type gallium
Next, as illustrated in fig. 16, a p-type
Next, as illustrated in fig. 17, a
Next, as illustrated in fig. 19, a field
Next, as illustrated in fig. 20, the
By the above manufacturing method, a semiconductor device having a structure similar to that shown in fig. 12 can be obtained.
In addition, in the method for manufacturing the semiconductor device illustrated in fig. 5 to 20, for example, photolithography may be used.
<
An oxide semiconductor device and a method for manufacturing the oxide semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
< Structure of oxide semiconductor device >
Fig. 21 is a sectional view schematically illustrating the structure of the semiconductor device according to this embodiment. In the semiconductor device illustrated in fig. 21, the length of the
As illustrated in fig. 21, the length of the
< operation of oxide semiconductor device >
Next, the operation of the semiconductor device according to this embodiment will be described.
A voltage is applied between the
In the semiconductor device according to the present embodiment, when a forward bias is applied, a forward current flows from the
Since the p-type
As a result, the depletion layer that has spread toward n-type gallium
Since the depletion layer is an insulator, most of the reverse bias voltage applied between the
Regarding the gallium oxide semiconductor, it is possible to easily control the n-type carrier concentration by adding an n-type impurity such as Si or Sn, but on the other hand, it is extremely difficult to control the p-type carrier concentration by adding a p-type impurity, and there has been no report that clear hole conduction is observed by adding a p-type impurity.
Therefore, it is difficult to form a p-type semiconductor by adding a p-type impurity into the n-type gallium
The semiconductor device according to this embodiment mode has the following structure: by forming the p-type
In the semiconductor device according to the present embodiment, since the
< embodiment 5 >
An oxide semiconductor device and a method for manufacturing the oxide semiconductor device according to this embodiment will be described. In the following description, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.
< Structure of oxide semiconductor device >
Fig. 22 is a sectional view schematically illustrating the structure of the semiconductor device according to this embodiment. The semiconductor device illustrated in fig. 22 is a field effect transistor in which the vertical direction in fig. 22 is the current direction.
As shown in fig. 22, an n-type gallium oxide epitaxial layer 2c is formed on the upper surface of the n-type
Further, a
Further, a source electrode 11 is formed on the upper surface of the n-type gallium oxide epitaxial layer 2 c. Then, the source electrode 11 is directly bonded to the n-type gallium oxide epitaxial layer 2 c. Further, a
The p-type oxide semiconductor layer 5c is directly bonded to the source electrode 11 at a certain position in the depth direction in fig. 22. In this case, the p-type oxide semiconductor layer 5c is formed to extend directly below the source electrode 11, or the source electrode 11 is formed to extend directly above the p-type oxide semiconductor layer 5 c.
Fig. 22 shows a case where the source electrode 11 in contact with the p-type oxide semiconductor layer 5c is extracted. A dielectric layer 7c is inserted into the interface between the upper portion of the p-type oxide semiconductor layer 5c and the n-type gallium oxide epitaxial layer 2 c. Therefore, in the present structure, similarly to the structure shown in the above embodiment, by forming the dielectric layer 7c on the side surface of the p-type oxide semiconductor layer 5c, diffusion of atoms between the p-type oxide semiconductor layer and the n-type gallium oxide epitaxial layer 2c can be suppressed. Therefore, threshold shift at the interface between the electrode and the semiconductor layer is suppressed.
The present structure is a field effect transistor that controls the amount of current flowing between the source electrode 11 and the
The semiconductor device according to this embodiment mode has the following structure: by forming the p-type oxide semiconductor layer 5c of a material different from gallium oxide inside the n-type gallium oxide epitaxial layer 2c, a depletion layer is formed within the n-type gallium oxide epitaxial layer 2c by a hetero pn junction.
That is, when a reverse voltage is applied to the source electrode 11 and the
In the semiconductor device according to the present embodiment, since the dielectric layer 7c is provided in a part of the surface parallel to the current direction of the device between the n-type gallium oxide epitaxial layer 2c and the p-type oxide semiconductor layer 5c, the metal atoms diffused from the p-type oxide semiconductor layer 5c can suppress the threshold shift in the interface between the source electrode 11 and the n-type gallium oxide epitaxial layer 2 c.
According to such a structure, in an oxide semiconductor device in which a heterogeneous pn junction is formed of a different oxide semiconductor material, diffusion of the different material to the interface between the electrode and the semiconductor can be suppressed, and the withstand voltage when a reverse voltage is applied can be improved.
< effects produced by the above-described embodiments >
Next, the effects produced by the above-described embodiments will be exemplified. In the following description, the effects are described based on the specific configurations exemplified in the above-described embodiments, but may be replaced with other specific configurations exemplified in the present specification within the range where the similar effects are produced.
In addition, the permutation may be performed across a plurality of embodiments. That is, the same effects may be produced by combining the respective configurations illustrated in the different embodiments.
According to the above-described embodiment, the oxide semiconductor device includes the n-type gallium oxide epitaxial layer, the p-type oxide semiconductor layer, the dielectric layer 7, the
With such a configuration, in an oxide semiconductor device in which a heterogeneous pn junction is formed of a different oxide semiconductor material, diffusion of the different material to a schottky interface is suppressed, and a withstand voltage when a reverse voltage is applied can be improved. Specifically, by forming the dielectric layer 7 on the side surface of the p-type oxide semiconductor layer, diffusion of atoms between the p-type oxide semiconductor layer and the n-type gallium
In addition, other structures than these structures exemplified in the present specification may be appropriately omitted. That is, the above-described effects can be produced by providing at least these structures.
However, the above-described effects can be similarly produced even when at least 1 of the other configurations exemplified in the present specification is appropriately added to the above-described configurations, that is, when the other configurations exemplified in the present specification that are not described as the above-described configurations are added to the above-described configurations.
In addition, according to the above-described embodiment, the side surface of the p-type oxide semiconductor layer 5 is a surface along the current direction which is the direction connecting the
In addition, according to the above-described embodiment, the lower surface of the
In addition, according to the above-described embodiment, the dielectric layer 7 is formed so as to cover the entire side surface of the p-type oxide semiconductor layer 5. With such a structure, diffusion of atoms to the schottky interface can be suppressed.
In addition, according to the above-described embodiment, the p-type
In addition, according to the above-described embodiment, the p-type oxide semiconductor layer 5 is formed from the upper surface to the lower surface of the n-type gallium
In addition, according to the above-described embodiment, the impurity concentration of the n-type gallium
In addition, according to the above-described embodiment, the p-type oxide semiconductor layer 5 is a metal oxide containing Cu or Ni. According to such a structure, Cu is added2O or NiO is used for the p-type oxide semiconductor layer 5, and can improve withstand voltage when a reverse voltage is applied and reduce leakage current.
According to the above-described embodiments, in the method for manufacturing an oxide semiconductor device, the
According to such a structure, when an oxide semiconductor device in which a hetero pn junction is formed of a different oxide semiconductor material is manufactured, a p-type semiconductor layer can be formed without performing p-type carrier concentration control by adding a p-type impurity. Specifically, the above structure can be realized by forming a groove portion in the n-type gallium
In addition, other structures than these structures exemplified in the present specification may be appropriately omitted. That is, the above-described effects can be produced by providing at least these structures.
However, the above-described effects can be similarly produced even when at least 1 of the other configurations exemplified in the present specification is appropriately added to the above-described configurations, that is, when the other configurations exemplified in the present specification that are not described as the above-described configurations are added to the above-described configurations.
In addition, the order of executing the respective processes can be changed without particular limitation.
In addition, according to the above-described embodiment, the p-type
In addition, according to the above-described embodiment, the
In addition, according to the above-described embodiment, the
In addition, according to the above-described embodiment, the
According to such a structure, when an oxide semiconductor device in which a hetero pn junction is formed of a different oxide semiconductor material is manufactured, a p-type semiconductor layer can be formed without performing p-type carrier concentration control by adding a p-type impurity. Specifically, the above structure can be realized by forming a p-type oxide semiconductor layer and a dielectric layer 7 partially on the upper surface of the n-type gallium
In addition, other structures than these structures exemplified in the present specification may be appropriately omitted. That is, the above-described effects can be produced by providing at least these structures.
However, the above-described effects can be similarly produced even when at least 1 of the other configurations exemplified in the present specification is appropriately added to the above-described configurations, that is, when the other configurations exemplified in the present specification that are not described as the above-described configurations are added to the above-described configurations.
In addition, the order of executing the respective processes can be changed without particular limitation.
< modification of the above-described embodiment >
In the above-described embodiments, materials, dimensions, shapes, relative arrangement, conditions for implementation, and the like of the respective constituent elements are described in some cases, but these are merely examples in all respects and are not limited to the examples described in the present specification.
Therefore, a myriad of modifications and equivalents not illustrated are assumed to be within the scope of the technology disclosed in the present specification. For example, the case where at least 1 component is modified, added, or omitted, and the case where at least 1 component in at least 1 embodiment is extracted and combined with the components of other embodiments are included.
In addition, the constituent elements described as being provided with "1" in the above-described embodiments may be provided with "1 or more" as long as no contradiction occurs.
Each of the components in the above-described embodiments is a conceptual unit, and includes a case where 1 component is configured by a plurality of structural members, a case where 1 component corresponds to a part of a certain structural member, and a case where a plurality of components are provided in 1 structural member within the scope of the technology disclosed in the present specification.
In addition, each component in the above-described embodiments may include a structural object having another structure or shape as long as the same function is exerted.
In addition, the description in the specification of the present application is referred to for all purposes related to the present technology, and should not be construed as a prior art.
In the above-described embodiments, when a material name or the like is described without being particularly specified, an alloy or the like containing another additive in the material is included as long as no contradiction occurs.
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