Static memory cell and forming method thereof
阅读说明:本技术 静态存储单元的形成方法及静态存储单元 (Static memory cell and forming method thereof ) 是由 王楠 于 2018-08-14 设计创作,主要内容包括:本发明提供了一种静态存储单元的形成方法及静态存储单元,首先单独对所述鳍部中的源极区域执行第一离子注入工艺,然后再对所述源极区域及漏极区域执行第二离子注入工艺,以形成源极和漏极,使所述源极的掺杂浓度较所述漏极的掺杂浓度大,后续对静态存储单元进行读写操作时,所述源极到所述漏极的电流与所述漏极到所述源极的电流是不相等的,即读取电流与写入电流不相等,进而降低了读/写裕量,提高了器件的可靠性和性能。(The invention provides a static memory unit and a forming method thereof.A first ion implantation process is firstly carried out on a source region in a fin part independently, and then a second ion implantation process is carried out on the source region and a drain region to form a source electrode and a drain electrode, so that the doping concentration of the source electrode is larger than that of the drain electrode, and when the static memory unit is subsequently read and written, the current from the source electrode to the drain electrode is not equal to the current from the drain electrode to the source electrode, namely the read current is not equal to the write current, thereby reducing the read/write margin and improving the reliability and performance of a device.)
1. A method for forming a static memory cell, the method comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first medium layer covering the polycrystalline silicon material layer on the substrate;
forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
forming a first side wall on the side wall of the first opening to form a second opening aligned with the source region, and performing a first ion implantation process to perform ion implantation on the source region;
removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
2. The method of claim 1, wherein the source is implanted with ions at a higher concentration than the drain.
3. The method of claim 2, wherein the source region implanted ions comprise arsenic ions and/or phosphorous ions and the drain region implanted ions comprise boron ions and/or boron fluoride ions.
4. The method of claim 1, wherein the first ion implantation is performed with an energy of 10 or more for implanting ions into the source region5ev; in the second ion implantation process, the energy of the ion implantation performed on the source region and the drain region is less than 105ev。
5. The method of claim 1, wherein after forming the third opening and the fourth opening and before performing the second ion implantation process, the method further comprises:
removing the first side wall;
and forming second side walls on the side walls of the third opening and the fourth opening.
6. The method of claim 1, wherein the first sidewall spacers have a cross-sectional width of 10nm to 15 nm.
7. The method of claim 1, wherein a second dielectric layer is formed between the polysilicon material layer and the first dielectric layer, and the second dielectric layer comprises one or more of silicon oxide, silicon nitride, or silicon oxynitride.
8. The method of claim 7, wherein gate dielectric layers are formed between the second dielectric layer and the polysilicon material layer and between the fin and the polysilicon material layer.
9. The method of claim 1, wherein a material of the first dielectric layer comprises one of amorphous carbon or amorphous silicon.
10. A static memory cell, comprising:
the substrate comprises a substrate and a fin part formed on the substrate, wherein a source electrode and a drain electrode are formed in the fin part, and the ion implantation concentration of the source electrode is greater than that of the drain electrode;
and the grid structure is positioned on the substrate, is positioned between the source electrode and the drain electrode and covers the top wall and the side wall of the fin part.
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a static memory cell and a static memory cell.
Background
A Fin Field effect transistor (FinFET) in a static memory is a novel metal oxide semiconductor Field effect transistor, and compared with a conventional static memory, the FinFET has a smaller size and better performance, but the reliability and performance of the existing FinFET need to be improved.
Disclosure of Invention
The invention provides a method for forming a static memory cell and a static memory cell, which are used for improving the reliability and the performance of the conventional fin field effect transistor.
In order to achieve the above object, the present invention provides a method for forming a static memory cell, including:
providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first medium layer covering the polycrystalline silicon material layer on the substrate;
forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
forming a first side wall on the side wall of the first opening to form a second opening aligned with the source region, and performing a first ion implantation process to perform ion implantation on the source region;
removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
Optionally, the ion implantation concentration of the source is higher than that of the drain.
Optionally, the ions implanted into the source region include arsenic ions and/or phosphorus ions, and the ions implanted into the drain region include boron ions and/or boron fluoride ions.
Optionally, in the first ion implantation process, the energy of ion implantation performed on the source region is greater than or equal to 105ev; in the second ion implantation process, the energy of the ion implantation performed on the source region and the drain region is less than 105ev。
Optionally, after the third opening and the fourth opening are formed and before the second ion implantation process is performed, the method for forming the static memory cell further includes:
removing the first side wall;
and forming second side walls on the side walls of the third opening and the fourth opening.
Optionally, the width of the cross section of the first side wall is 10nm to 15 nm.
Optionally, a second dielectric layer is further formed between the polysilicon material layer and the first dielectric layer, and the material of the second dielectric layer includes one or more of silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, gate dielectric layers are formed between the second dielectric layer and the polysilicon material layer and between the fin portion and the polysilicon material layer.
Optionally, the material of the first dielectric layer includes one of amorphous carbon or amorphous silicon.
The invention also provides a static storage unit, which comprises a plurality of static storage units, wherein the static storage unit comprises:
the substrate comprises a substrate and a fin part formed on the substrate, wherein a source electrode and a drain electrode are formed in the fin part, and the ion implantation concentration of the source electrode is greater than that of the drain electrode;
and the grid structure is positioned on the substrate, is positioned between the source electrode and the drain electrode and covers the top wall and the side wall of the fin part.
In the method for forming the static storage unit and the static storage unit, a first ion implantation process is performed on a source region in the fin part at first, and then a second ion implantation process is performed on the source region and a drain region to form a source electrode and a drain electrode, so that the doping concentration of the source electrode is larger than that of the drain electrode, and when the static storage unit is subjected to read-write operation subsequently, the current from the source electrode to the drain electrode is not equal to the current from the drain electrode to the source electrode, namely the read current is not equal to the write current, so that the read/write margin is reduced, and the reliability and the performance of a device are improved.
Drawings
FIG. 1 is a flow chart of a method for forming a static memory cell according to an embodiment of the present invention;
FIGS. 2-8 are schematic cross-sectional views of a semiconductor structure formed by the method for forming a static memory cell according to an embodiment of the present invention;
the structure comprises a
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, which is a flowchart illustrating a method for forming a static memory cell according to the present embodiment, the method for forming a static memory cell includes:
s1: providing a substrate, wherein the substrate comprises a substrate and a fin part formed on the substrate, and the fin part comprises a source electrode region and a drain electrode region;
s2: sequentially forming a polycrystalline silicon material layer covering the substrate and the fin part and a first medium layer covering the polycrystalline silicon material layer on the substrate;
s3: forming a first opening corresponding to the source electrode region in the first dielectric layer, wherein a part of the polycrystalline silicon material layer is exposed out of the first opening;
s4: forming a first side wall on the side wall of the first opening to form a second opening aligned with the source region, and performing a first ion implantation process to perform ion implantation on the source region;
s5: removing the remaining first dielectric layer, the polysilicon material layer below the remaining first dielectric layer and the polysilicon material layer below the second opening to form a third opening aligned with the source region and a fourth opening aligned with the drain region;
s6: performing a second ion implantation process to implant ions into the source region and the drain region to form a source and a drain.
According to the invention, firstly, the source region in the fin part is subjected to primary ion implantation, and then the source region and the drain region are subjected to primary ion implantation to form the source electrode and the drain electrode, so that the doping concentrations of the source electrode and the drain electrode are different, and when the static memory cell is subjected to subsequent read-write operation, the current from the source region to the drain region is unequal to the current from the drain region to the source region, namely the read current is unequal to the write current, so that the read/write allowance is reduced, and the reliability and the performance of the device are improved.
Specifically, referring to fig. 2 to 8, which are schematic cross-sectional views of a semiconductor structure formed by the method for forming a static memory cell according to the present embodiment, the method for forming a static memory cell according to the present invention will be further described with reference to fig. 2 to 8.
First, referring to fig. 2, a
Referring to fig. 3, a
Next, referring to fig. 4 to 5, an etching process is used to remove a portion of the first
Referring to fig. 5, a first ion implantation process is performed on the source region of the
Referring to fig. 6, the remaining first
Referring to fig. 7 to 8, the
After two ion implantation processes, the impurity ion concentration of the
The embodiment also provides a static memory cell, and the static memory cell is formed by adopting the forming method of the static memory cell.
Specifically, as shown in fig. 8, the static memory cell includes a
Optionally, the gate structure includes a gate electrode made of a polysilicon material, and a gate dielectric layer and a second sidewall surrounding the gate electrode, where the gate dielectric layer and the second sidewall are used to protect the gate electrode from being damaged.
In summary, in the method for forming a static memory cell and the static memory cell provided in the embodiments of the present invention, a first ion implantation process is performed on a source region in the fin portion, and then a second ion implantation process is performed on the source region and a drain region to form a source and a drain, so that a doping concentration of the source is higher than a doping concentration of the drain, and when a read/write operation is performed on the static memory cell subsequently, a current from the source to the drain is not equal to a current from the drain to the source, that is, a read current is not equal to a write current, thereby reducing a read/write margin and improving reliability and performance of a device.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
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