阅读说明：本技术 具有半导体性栅极的场效应晶体管 (Field effect transistor with semiconducting gate ) 是由 陈敬 钱庆凯 于 2019-08-08 设计创作，主要内容包括：提供了一种场效应晶体管，包括：衬底；源极层，其位于所述衬底上；漏极层，其位于所述衬底上；沟道层，其电连接所述源极层和所述漏极层；栅极介电层，其位于所述沟道层的远离所述衬底的一侧；半导体性栅极层，其位于所述栅极介电层的远离所述沟道层的一侧；栅电极，其与所述半导体性栅极层电连接，所述栅电极在所述衬底上的正投影在所述沟道层在所述衬底上的正投影之外。所述半导体性栅极层具有与所述沟道层在场效应晶体管导通状态下的导电沟道相同的载流子，并且所述半导体性栅极层的厚度和掺杂度设置为使得在向所述栅电极施加的电压大于预定电压时所述半导体性栅极被耗尽，同时所述沟道层的沟道完全导通。(Provided is a field effect transistor including: a substrate; a source layer on the substrate; a drain layer on the substrate; a channel layer electrically connecting the source layer and the drain layer; a gate dielectric layer on a side of the channel layer away from the substrate; a semiconducting gate layer on a side of the gate dielectric layer away from the channel layer; a gate electrode electrically connected to the semiconducting gate layer, an orthographic projection of the gate electrode on the substrate being outside an orthographic projection of the channel layer on the substrate. The semiconducting gate layer has the same charge carriers as a conducting channel of the channel layer in an on-state of a field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.)

1. A field effect transistor, comprising:

a substrate;

a source layer on the substrate;

a drain layer on the substrate;

a channel layer electrically connecting the source layer and the drain layer;

a gate dielectric layer on a side of the channel layer away from the substrate;

a semiconducting gate layer on a side of the gate dielectric layer away from the channel layer;

a gate electrode electrically connected to the semiconducting gate layer, an orthographic projection of the gate electrode on the substrate being outside an orthographic projection of the channel layer on the substrate,

wherein the semiconducting gate layer has the same carrier type as a conducting channel of the channel layer in an on-state of the field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.

2. The field effect transistor of claim 1, wherein a voltage applied to the gate electrode affects conductivity of the channel layer indirectly through the semiconducting gate layer.

3. The field effect transistor of claim 2, wherein the material of the semiconducting gate layer comprises Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

4. The field effect transistor of claim 1, further comprising a first semiconductor layer on a side of the semiconducting gate layer remote from the substrate, wherein a carrier type of the semiconducting gate layer is opposite to a carrier type of the first semiconductor layer, and both the semiconducting gate layer and the first semiconductor layer are connected to the gate electrode.

5. The field effect transistor of any of claims 1-4, wherein the semiconducting gate layer extends beyond the channel layer in a direction parallel to the substrate.

6. The field effect transistor of any of claims 1-4, further comprising a conductive gate layer, wherein the conductive gate layer is on a side of the gate dielectric layer distal to the channel layer and is electrically connected to the gate electrode through the semiconducting gate layer.

7. The field effect transistor of claim 6, wherein the semiconducting gate layer overlies a portion of the channel layer in a direction perpendicular to the substrate and the conducting gate layer overlies another portion of the channel layer in a direction perpendicular to the substrate.

8. The field effect transistor of claim 6, further comprising a second semiconductor layer connected to the source layer and spaced apart from the channel layer, the semiconducting gate layer overlying the second semiconductor layer in a direction perpendicular to the substrate, the conducting gate layer overlying the channel layer in a direction perpendicular to the substrate.

9. The field effect transistor according to claim 6, wherein the channel layer includes a protruding portion that faces the gate electrode when viewed in a plan view and is located outside an area between the source layer and the drain layer, and the semiconductive gate layer is located outside the area between the source layer and the drain layer when viewed in a plan view and at least partially overlaps with the protruding portion.

10. The field effect transistor of claim 6, further comprising a third semiconductor layer connected to the source layer, wherein the third semiconductor layer is outside of a region between the source layer and the drain layer and spaced apart from the channel layer when viewed in plan view, the semiconducting gate layer being outside of the region between the source layer and the drain layer and at least partially overlapping the third semiconductor layer.

11. The field effect transistor of claim 1, wherein the channel layer material comprises Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

12. The FET of claim 1, wherein the gate electrode material comprises a metal, heavily doped Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

13. The field effect transistor of claim 6, wherein the material of the conductive gate layer comprises a metal, heavily doped Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

14. A field effect transistor, comprising:

a substrate;

a semiconducting gate layer on the substrate;

a gate electrode on the substrate and electrically connected to the semiconducting gate layer;

a gate dielectric layer on a side of the semiconducting gate layer away from the substrate;

a source layer;

a drain layer;

a channel layer located on a side of the gate dielectric layer remote from the substrate and electrically connecting the source layer and the drain layer, an orthographic projection of the channel layer on the substrate being outside an orthographic projection of the gate electrode on the substrate,

wherein the semiconducting gate layer has the same carrier type as a conducting channel of the channel layer in an on-state of the field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.

15. A field effect transistor, comprising:

a substrate;

a source layer on the substrate;

a drain layer on the substrate;

a channel layer electrically connecting the source layer and the drain layer;

a semiconducting gate layer having an orthographic projection on the substrate outside an orthographic projection of the channel layer on the substrate;

a first gate dielectric layer on a side of the channel layer away from the substrate;

a second gate dielectric layer on a side of the semiconducting gate layer away from the substrate;

a conductive coupling layer on a side of the first and second gate dielectric layers remote from the substrate; and

a gate electrode electrically connected to the semiconducting gate layer, an orthographic projection of the gate electrode on the substrate being outside an orthographic projection of the channel layer on the substrate,

wherein the semiconducting gate layer has the same carrier type as a conducting channel of the channel layer in an on-state of the field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly to a field effect transistor having a semiconducting gate.

Background

Field Effect Transistors (FETs) are the core of modern semiconductor technology (e.g., CMOS, TFT, compound semiconductor HEMTs, etc.) as voltage driven devices. It has the advantages of large input impedance, good isolation between gate control and channel current, and has supported a wide range of existing and emerging applications. For example, low power FETs are used for high speed computing and internet of things (IoT) logic and analog ICs. In particular, Complementary Metal Oxide Semiconductor (CMOS) FETs have become the basis for Very Large Scale Integration (VLSI) due to their low static power consumption. In addition to the low power FET, the power FET is another important branch of the FET. The power FET includes a MISFET/MOSFET or HEMT based on wide bandgap semiconductors (i.e., GaN or SiC). These power devices can operate at high speed and large currents at high voltages and high temperatures. They have wide application in energy conversion and power supply, and are important components for building modern energy-saving society.

Despite the advantages and broad applications described above, voltage-driven FETs have the disadvantage of being susceptible to an overload gate voltage, particularly under forward gate bias. The general structure of a conventional FET is schematically shown in fig. 1 (a). As shown in fig. 1(a), the FET 10 includes a source layer 11, a drain layer 12, a channel layer 13, a gate dielectric layer 14, and a gate layer 15. The gate layer 15 is typically made of metal or thick heavily doped polysilicon. The gate dielectric layer 14 includes one or more insulating layers, or one or more semiconductor layers, to provide capacitive coupling between the gate layer 15 and the channel layer 13. When a large voltage is applied to the gate electrode layer 15, a large electric field may be applied to the gate dielectric layer 14. As a result, the gate dielectric layer 14 will experience breakdown or cause threshold voltage instability. Although power FETs are designed to withstand large drain biases, they are also susceptible to forward gate over-voltage. To achieve a FET with good gate robustness, gate overvoltage protection is crucial not only to prevent gate dielectric breakdown, but also to improve device reliability and threshold voltage stability. Various gate overvoltage protection schemes have been developed for field effect transistors for a long time. These protection schemes can be divided into two categories: current limiting and voltage limiting, for example, as shown in fig. 1 (b). All these solutions require external peripheral components such as bootstrap FETs, zener diodes, etc. However, these additional components not only degrade device performance due to increased gate capacitance or gate resistance, but also introduce additional difficulties and waste device area for monolithic integration.

Disclosure of Invention

For prior art FETs, metal or heavily doped polysilicon is used as the Conductive Gate (CG), which has a very high carrier density. For example, Ni films as thin as 10nm have at least about 1.8X 10¹⁷cm^-2Is much greater than the sheet carrier density of an active channel when the channel has been considered to be fully on (1 x 10)¹³cm^-2). Due to the extremely high carrier density of the conductive gate, an excessively high gate bias may be applied on the gate dielectric layer through the metal/polysilicon gate without any limitation. In the present invention, instead of using a conventional conductive gate based on metal or heavily doped polysilicon, a Semiconductor Gate (SG) based on a thin layer of moderately doped semiconductor for FETs is disclosed. In contrast to metal or polysilicon gates in the prior art, the conductivity of the SG can be effectively modulated by the gate electric field, and a large gate bias will deplete the SG and decouple it from the underlying dielectric and channel layers. As a result, the SG can provide inherent overvoltage protection for the FET without any additional peripheral circuits or elements, and immunity to forward and reverse gate voltages can be achieved.

According to an embodiment of the present disclosure, there is provided a field effect transistor including: a substrate; a source layer on the substrate; a drain layer on the substrate; a channel layer electrically connecting the source layer and the drain layer; a gate dielectric layer on a side of the channel layer away from the substrate; a semiconducting gate layer on a side of the gate dielectric layer away from the channel layer; a gate electrode electrically connected to the semiconducting gate layer, an orthographic projection of the gate electrode on the substrate being outside an orthographic projection of the channel layer on the substrate. That is, the field effect transistor may be configured as a top gate device. Alternatively, the field effect transistor includes: a substrate; a semiconducting gate layer on the substrate; a gate electrode on the substrate and electrically connected to the semiconducting gate layer; a gate dielectric layer on a side of the semiconducting gate layer away from the substrate; a source layer; a drain layer; a channel layer located on a side of the gate dielectric layer away from the substrate and electrically connecting the source layer and the drain layer, an orthographic projection of the channel layer on the substrate being outside an orthographic projection of the gate electrode on the substrate. That is, the field effect transistor may be configured as a back gate device. In the above top-gate and back-gate devices, the semiconducting gate layer has the same type of carriers as the conducting channel of the channel layer in the on-state of the field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.

According to an embodiment of the present disclosure, a voltage applied to the gate electrode indirectly affects conductivity of the channel layer through the semiconducting gate layer.

According to an embodiment of the present disclosure, the material of the semiconductor gate layer includes Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

According to an embodiment of the present disclosure, the field effect transistor further includes a first semiconductor layer located on a side of the semiconductor gate layer away from the substrate, wherein a carrier type of the semiconductor gate layer is opposite to a carrier type of the first semiconductor layer, and the semiconductor gate layer and the first semiconductor layer are both connected to the gate electrode.

According to an embodiment of the present disclosure, the semiconducting gate layer extends beyond the channel layer in a direction parallel to the substrate.

According to an embodiment of the present disclosure, the field effect transistor further comprises a conductive gate layer, wherein the conductive gate layer is located on a side of the gate dielectric layer away from the channel layer and is electrically connected to the gate electrode through the semiconducting gate layer.

According to an embodiment of the present disclosure, the semiconducting gate layer covers a portion of the channel layer in a direction perpendicular to the substrate, and the conducting gate layer covers another portion of the channel layer in a direction perpendicular to the substrate.

According to an embodiment of the present disclosure, the field effect transistor further includes a second semiconductor layer connected to the source layer and spaced apart from the channel layer, the semiconducting gate layer covering the second semiconductor layer in a direction perpendicular to the substrate, and the conducting gate layer covering the channel layer in a direction perpendicular to the substrate.

According to an embodiment of the present disclosure, the channel layer includes a protruding portion that faces the gate electrode when viewed in a plan view and is located outside an area between the source layer and the drain layer, and the semiconductive gate layer is located outside the area between the source layer and the drain layer when viewed in a plan view and at least partially overlaps the protruding portion.

According to an embodiment of the present disclosure, the field effect transistor further includes a third semiconductor layer connected to the source layer, wherein the third semiconductor layer is outside an area between the source layer and the drain layer and spaced apart from the channel layer when viewed in a plan view, and the semiconducting gate layer is outside the area between the source layer and the drain layer and at least partially overlaps the third semiconductor layer.

According to an embodiment of the present disclosure, the field effect transistor, wherein the material of the channel layer includes Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNT.

According to the embodiment of the present disclosure, the material of the gate electrode comprises metal, heavily doped Si, Ge, SiGe, ZnO,IGZO、GaAs、GaN、SiC、MoS₂、WSe₂、WS₂Black phosphorus or CNTs, and other semiconductors.

According to an embodiment of the present disclosure, the material of the conductive gate layer comprises metal, heavily doped Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus or CNTs, and other semiconductors.

There is also provided a field effect transistor comprising: a substrate; a source layer on the substrate; a drain layer on the substrate; a channel layer electrically connecting the source layer and the drain layer; a semiconducting gate layer having an orthographic projection on the substrate outside an orthographic projection of the channel layer on the substrate; a first gate dielectric layer on a side of the channel layer away from the substrate; a second gate dielectric layer on a side of the semiconducting gate layer away from the substrate; a conductive coupling layer on a side of the first and second gate dielectric layers remote from the substrate; and a gate electrode electrically connected to the semiconducting gate layer, an orthographic projection of the gate electrode on the substrate being outside an orthographic projection of the channel layer on the substrate. The semiconducting gate layer has the same charge carriers as a conducting channel of the channel layer in an on-state of a field effect transistor, and the thickness and doping of the semiconducting gate layer is such that the semiconducting gate is depleted while the channel of the channel layer is fully conducting when a voltage greater than a predetermined voltage is applied to the gate electrode.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

fig. 1(a) shows a general structure of a conventional field effect transistor.

Fig. 1(b) shows a typical technique for protecting a field effect transistor.

Fig. 2(a) is a side view of a field effect transistor according to a first embodiment of the present invention.

Fig. 2(b) is a top view of a field effect transistor according to a first embodiment of the present invention.

Fig. 2(c) is a sectional view of the field effect transistor taken along a broken line in fig. 2 (b).

Fig. 3(a) is a top view of a field effect transistor according to a second embodiment of the present invention.

Fig. 3(b) is a sectional view of the field effect transistor taken along a broken line in fig. 3 (a).

Fig. 4(a) is a top view of a field effect transistor according to a third embodiment of the present invention.

Fig. 4(b) is a sectional view of the field effect transistor taken along a broken line in fig. 4 (a).

Fig. 5(a) is a top view of a field effect transistor according to a fourth embodiment of the present invention.

Fig. 5(b) is a sectional view of the field effect transistor taken along a broken line in fig. 5 (a).

Fig. 6(a) is a top view of a field effect transistor according to a fifth embodiment of the present invention.

Fig. 6(b) is a sectional view of the field effect transistor taken along a broken line in fig. 6 (a).

Fig. 7(a) is a top view of a field effect transistor according to a sixth embodiment of the present invention.

Fig. 7(b) is a sectional view of the field effect transistor taken along a broken line in fig. 7 (a).

Fig. 8(a) is a side view of a first example of a field effect transistor according to a first embodiment of the present invention.

Fig. 8(b) is a top view of the field effect transistor in fig. 8 (a).

Fig. 8(c) is a sectional view of the field effect transistor taken along a broken line in fig. 8 (b).

Fig. 9(a) is a side view of a second example of the field effect transistor according to the first embodiment of the present invention.

Fig. 9(b) is a top view of the field effect transistor in fig. 9 (a).

Fig. 9(c) is a sectional view of the field effect transistor taken along a broken line in fig. 9 (b).

Fig. 10 is a side view of a third example of the field effect transistor according to the first embodiment of the present invention.

Fig. 11(a) is a side view of a fourth example of the field effect transistor according to the first embodiment of the present invention.

Fig. 11(b) is a top view of a fourth example of the field effect transistor according to the first embodiment of the present invention.

FIG. 12(a) shows MoS in a single layer₂A simulated electron density distribution in the gate width direction of an AlGaN/GaN HEMT as a semiconductor gate.

FIG. 12(b) shows MoS in a single layer₂A simulated potential distribution in the gate width direction of an AlGaN/GaN HEMT as a semiconductor gate.

FIG. 13(a) shows the transfer curve and gate leakage for an AlGaN/GaN HEMT with a Ni/Au gate.

FIG. 13(b) shows MoS in a single layer₂Transfer curve and gate leakage of AlGaN/gan hemt as a semiconducting gate.

Fig. 14(a) shows the output characteristics of an AlGaN/GaN HEMT having Ni/Au as the gate.

FIG. 14(b) shows MoS in a single layer₂AlGaN/GaNHEMT as a semiconductor gate has an output characteristic.

FIG. 15(a) compares an AlGaN/GaN HEMT with a Ni/Au metal gate and a MoS₂Sub-threshold swing (SS) for AlGaN/GaN HEMTs with semiconducting gates.

FIG. 15(b) compares an AlGaN/GaN HEMT with a Ni/Au metal gate and a MoS₂Off-state breakdown of the AlGaN/GaN HEMT of the semiconducting gate.

Fig. 16(a) is a side view of a field effect transistor according to a seventh embodiment of the present invention.

Fig. 16(b) is a top view of a field effect transistor according to a seventh embodiment of the present invention.

Fig. 16(c) is a sectional view of the field effect transistor taken along a broken line in fig. 16 (b).

Detailed Description

The present disclosure describes several embodiments and examples, and the following statements are not to be considered as generally limiting the claims. The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiments (by way of example and not of limitation). For simplicity and clarity of illustration, the drawing figures show a general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. In addition, the elements in the figures are not necessarily to scale, some regions or elements may be expanded to help improve understanding of embodiments of the invention.

The terms first, second, third, fourth and the like in the description and in the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, apparatus, or composition that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, apparatus, or composition.

Spatially relative terms, such as "below," "lower," "below," "over," "above," and the like, may be used herein for ease of description to describe a relationship between a feature and another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced in other directions) and the spatially relative descriptors used herein interpreted accordingly.

It is contemplated and intended that the design of the control section in the present application applies to all semiconductor devices, such as semiconductor devices based on Si, SiC and GaAs or heterostructures such as InAlN/GaN; for clarity, some examples are preferably based on AlGaN/GaN platforms on Si. However, one of ordinary skill in the art will recognize modifications to the design to make variations to other combinations and forms of the design.

Fig. 2(a) is a side view of a field effect transistor according to a first embodiment of the present invention; fig. 2(b) is a top view of a field effect transistor according to a first embodiment of the present invention; fig. 2(c) is a sectional view of the field effect transistor taken along a broken line in fig. 2 (b). As shown in fig. 2(a) to 2(c), a field effect transistor (SG-FET)20 having a semiconducting gate includes a source layer 21, a drain layer 22, a channel layer 23, a gate dielectric layer 24, a semiconducting gate layer 25, and a gate electrode 26 formed on a substrate (not shown).

In some embodiments, the substrate may comprise silicon, sapphire, diamond, SiC, AlN, GaN, or the like. The semiconducting gate layer 25 comprises a thin layer of moderately doped semiconductor with a doping concentration and thickness such that it can be depleted and, when depleted, the conduction channel carriers reach a desired surface density of carriers, typically 1 x 10¹²cm^-2To 1X 10¹⁴cm^-2Within the range. In some embodiments, the material of the source layer 21 and the drain layer 22 may include a doped semiconductor, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. In some embodiments, the material of the source layer 21 and the drain layer 22 may include a metal, such as Ni, Au, Al, Cr, or the like. The material of the channel layer 23 includes a semiconductor such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 23 may comprise the same semiconductor material as the source layer 21 or the drain layer 22 (if they comprise semiconductor material), but may also be other semiconductor materials. The channel layer 23 may be doped or undoped which will affect the threshold voltage of the FET and determine whether the FET is a depletion mode device or an enhancement mode device. The channel layer 23 is electrically connected to the source layer 21 and the drain layer 22. The gate dielectric layer 24 may be a single layer of insulating material or semiconductor material, but may also be a combination of insulating and/or semiconductor layers. A semiconducting gate layer 25 is located on top of the channel layer 23 and the gate dielectric layer 24. As shown in fig. 2(b) and 2(c), the semiconductor gate layer 25 extends from both sides of the channel layer 23 in the y direction beyond the trenchA track layer 23. The semiconducting gate layer 25 may also include an additional semiconductor layer of the opposite carrier type on top of a single thin layer of moderately-doped semiconductor (see fig. 9 (a)). The material of the semiconductor gate layer 25 may be the same as the channel layer 23, but may be other semiconductor materials such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 25 is electrically connected to the gate electrode 26. The material of the gate electrode 26 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The gate electrode 26 is located outside the region of the channel layer 23 (specifically, an orthogonal projection of the gate electrode 26 on the substrate does not overlap with an orthogonal projection of the channel layer 23 on the substrate), so that the gate electrode 26 is not directly coupled to the channel layer 23 by an electric field effect. The voltage applied to the gate electrode 26 should indirectly affect the conductivity of the channel layer 23 through the semiconducting gate layer 25. To provide overvoltage protection, the semiconducting gate layer 25 has the same type of carriers as the active channel of channel layer 23, i.e., the type of carriers in channel layer 23 when channel layer 23 is on allowing current to flow along source layer 21, channel layer 23, and drain layer 22. For the case where FET20 is an n-channel device, the semiconducting gate layer 25 is n-type, so a large positive gate bias applied to gate electrode 26 will tend to deplete the semiconducting gate layer 25 above channel layer 23. If the doping of the semiconducting gate layer 25 is carefully adjusted to be fully depleted when the underlying channel layer 23 is fully on, any additional voltage present at the gate electrode 26 will be decoupled from the gate dielectric layer 24 and the underlying channel layer 23, resulting in inherent gate overvoltage protection and suppression of gate leakage of SG-FET20 without the need for any additional protection circuitry or components.

Fig. 16(a) is a side view of a field effect transistor according to a seventh embodiment of the present invention; fig. 16(b) is a top view of a field effect transistor according to a seventh embodiment of the present invention; fig. 16(c) is a sectional view of the field effect transistor taken along a broken line in fig. 16 (b). Fig. 2(a) -2 (c) show a field effect transistor with a top gate structure, and fig. 16(a) -16 (c) show a field effect transistor with a back gate structure corresponding to the field effect transistor with the top gate structure shown in fig. 2(a) -2 (c), which have similar structures and are not repeated herein.

Fig. 3(a) is a top view of a field effect transistor according to a second embodiment of the present invention; fig. 3(b) is a sectional view of the field effect transistor taken along a broken line in fig. 3 (a). As shown in fig. 3(a) and 3(b), SG-FET 30 includes a source layer 31, a drain layer 32, a channel layer 33, a gate dielectric layer 34, a semiconducting gate layer 35, a gate electrode 36, and a conductive gate layer 37 formed on a substrate (not shown).

Unlike the SG-FET20 in the first embodiment, the semiconductor gate layer 35 included in the SG-FET 30 in the present embodiment covers only a part of the channel layer 33, and a part of the channel layer 33 is covered with the conductive gate layer 37. As shown in fig. 3(a) and 3(b), the semiconductor gate layer 35 covers only one side edge of the channel layer 33 in the y direction. The conductive gate layer 37 is electrically connected to the gate electrode 36 indirectly through the semiconductor gate layer 35. As a result, partial coverage of channel layer 33 by semiconducting gate layer 35 will maintain the inherent gate overvoltage protection capability while reducing the gate resistance of SG-FET 30. The substrate may comprise silicon, sapphire, diamond, SiC, AlN, GaN, or the like. The material of the source layer 31 and the drain layer 32 may include a doped semiconductor such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, etc., but may also include metals such as Ni, Au, Al, Cr, etc. The material of the channel layer 33 may comprise a semiconductor, which may be the same as the semiconductor comprised by the source layer 31 and the drain layer 32 (if they comprise a semiconductor material), but may also comprise other kinds of semiconductors, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 33 may be doped or undoped which will affect the threshold voltage of the FET and determine whether the FET is a depletion mode device or an enhancement mode device. The channel layer 33 is electrically connected to the source layer 31 and the drain layer 32. The gate dielectric layer 34 may be a single layer of insulating material or semiconductor material, but may also be a combination of insulating and/or semiconductor layers. The semiconducting gate layer 35 comprises a thin layer of moderately doped semiconductor located between the channel layer 33 and the gate dielectric layer 34A top portion. The material of the semiconductor gate layer 35 may be the same as the channel layer 33, and may also include other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 35 is electrically connected to the gate electrode 36. The gate electrode 36 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The conductive gate layer 37 may be the same material as the gate electrode 36, but may also be another metal, heavily doped polysilicon, or other heavily doped semiconductor. The gate electrode 36 is located outside the channel layer 33 such that the gate electrode 36 is not directly coupled to the channel layer 33 by an electric field effect. The voltage applied to the gate electrode 36 indirectly affects the conductivity of the channel layer 33 through the semiconducting gate layer 35 and the conducting gate layer 37. To provide overvoltage protection, semiconducting gate layer 35 has the same type of carriers as the active channel of channel layer 33, i.e., the type of carriers when channel layer 33 is turned on to allow current to flow along source layer 31, channel layer 33, and drain layer 32.

Fig. 4(a) is a top view of a field effect transistor according to a third embodiment of the present invention; fig. 4(b) is a sectional view of the field effect transistor taken along a broken line in fig. 4 (a). As shown in fig. 4(a) and 4(b), the SG-FET 40 includes a source layer 41, a drain layer 42, a channel layer 43, a gate dielectric layer 44, a semiconductive gate layer 45, a gate electrode 46, a conductive gate layer 47, and a semiconductor layer 48 formed on a substrate (not shown).

In the SG-FET 30 according to the second embodiment, the channel layer 33 under the semiconductive gate layer 35 and the conductive gate layer 37 is a single continuous layer. Unlike SG-FET 30 in the second embodiment, in SG-FET 40 according to the third embodiment, as shown in fig. 4(a) and 4(b), semiconductor layer 48 under semiconductor gate layer 45 and channel layer 43 under conductive gate layer 47 are two layers spaced apart from each other and independently connected to source layer 41. In some embodiments, the semiconducting gate layer 45 completely covers the semiconductor layer 48 and the conductive gate layer 47 completely covers the channel layer 43 when viewed in plan view. The conductive gate layer 47 is electrically connected to the gate electrode 46 indirectly through the semiconductive gate layer 45. All possibilities from gate electrode 46 to conductive gate layer 47Should include at least a portion of the semiconducting gate layer 45 over the semiconductor layer 48. The substrate may comprise silicon, sapphire, diamond, SiC, AlN, GaN, or the like. The source layer 41 and the drain layer 42 may be doped semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, etc., but may also be a metal such as Ni, Au, Al, Cr, etc. The material of the channel layer 43 comprises a semiconductor, which may be the same as the semiconductor comprised by the source layer 41 and the drain layer 42 (if they comprise semiconductor materials), but may also comprise other kinds of semiconductors, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 43 may be doped or undoped, which affects only the threshold voltage of the FET and determines whether the FET is a depletion mode device or an enhancement mode device. The channel layer 43 is electrically connected to the source layer 41 and the drain layer 42. The gate dielectric layer 44 may be a homogeneous layer of insulator or semiconductor, but may also be a combination of insulating and/or semiconducting layers. The material of the semiconductor layer 48 may be the same as the channel layer 43, but may be other kinds of semiconductors, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 45 comprises a thin layer of moderately doped semiconductor on top of the semiconductor layer 48 and the gate dielectric layer 44. The material of the semiconducting gate layer 45 may be the same as the channel layer 43, but may also include other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 45 is electrically connected to the gate electrode 46. The gate electrode 46 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The conductive gate layer 47 may be the same material as the gate electrode 46, but may also be another metal, heavily doped polysilicon, or other heavily doped semiconductor. The material of the semiconductor layer 48 may be the same as the channel layer 43, but may also include other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. Semiconductor layer 48 mayEither doped or undoped, which will only affect the clamped gate voltage. The gate electrode 46 is located outside the channel layer 43 and the semiconductor layer 48 such that the gate electrode 46 is not directly coupled with the channel layer 43 and the semiconductor layer 48 by an electric field effect. A voltage applied to the gate electrode 46 indirectly affects the conductivity of the channel layer 43 and the semiconductor layer 48 through the semiconducting gate layer 45 and the conducting gate layer 47. To provide overvoltage protection, the semiconducting gate layer 45 has the same carrier type as the active channel of the channel layer 43, i.e., when the channel layer 43 is on to allow current to flow along the source layer 41, the channel layer 43, and the drain layer 42.

Fig. 5(a) is a top view of a field effect transistor according to a fourth embodiment of the present invention; fig. 5(b) is a sectional view of the field effect transistor taken along a broken line in fig. 5 (a). Such as

As shown in fig. 5(a) and 5(b), SG-FET50 includes a source layer 51, a drain layer 52, a channel layer 53, a gate dielectric layer 54, a semiconducting gate layer 55, a gate electrode 56, and a conductive gate layer 57 formed on a substrate (not shown).

Unlike SG-FET 30 according to the second embodiment, semiconductive gate layer 55 in SG-FET50 is located completely outside the area between source layer 51 and drain layer 52. The channel layer 53 also has a portion outside the region between the source layer 51 and the drain layer 52. The portion of the channel layer 53 underlies the semiconducting gate layer 55. A conductive gate layer 57 is located over a portion of the channel layer 53 located between the source layer 51 and the drain layer 52. The conductive gate layer 57 is electrically connected to the gate electrode 56 through a semiconductive gate layer. Because semiconducting gate layer 55 in fig. 5 is located outside the area between source layer 51 and drain layer 52, the semiconducting gate layer may have a wider and adjustable contact length than gate electrode 56 and conductive gate layer 57. As a result, SG-FET50 has an advantage of further reducing the gate resistance. The substrate may be silicon, sapphire, diamond, SiC, AlN, GaN, etc. The source layer 51 and the drain layer 52 may include a doped semiconductor such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, etc., but may also include metals such as Ni, Au, Al, Cr, etc. ChannelThe material of layer 53 may comprise a semiconductor, which may be the same as the semiconductor comprised by source layer 51 and drain layer 52 (if they comprise a semiconductor material), but may also comprise other types of semiconductors, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 53 may be doped or undoped, which affects only the threshold voltage of the FET and determines whether the FET is a depletion mode device or an enhancement mode device. The channel layer 53 is electrically connected to the source layer 51 and the drain layer 52. The gate dielectric layer 54 may be a single layer of insulating material or semiconductor, but may also be a combination of insulating and/or semiconductor layers. The semiconducting gate layer 55 comprises a thin layer of moderately doped semiconductor on top of the channel layer 53 and the gate dielectric layer 54. The material of the semiconductor gate layer 55 may be the same as the channel layer 53, but may be other semiconductor materials such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 55 is electrically connected to a gate electrode 56. The gate electrode 56 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The conductive gate layer 57 may be the same material as the gate electrode 56, but may also be another metal, heavily doped polysilicon, or other heavily doped semiconductor. The gate electrode 56 is located outside the region of the channel layer 53 such that the gate electrode 56 is not directly coupled to the channel layer 53 by an electric field effect. A voltage applied to the gate electrode 56 indirectly affects the conductivity of the channel layer 53 through the semiconducting gate layer 55 and the conducting gate layer 57. To provide overvoltage protection, the semiconducting gate layer 55 has the same type of carriers as the active channel of the channel layer 53, i.e., the type of carriers when the channel layer 53 is turned on to allow current to flow along the source layer 51, the channel layer 53, and the drain layer 52.

Fig. 6(a) is a top view of a field effect transistor according to a fifth embodiment of the present invention; fig. 6(b) is a sectional view of the field effect transistor taken along a broken line in fig. 6 (a). As shown in fig. 6(a) and 6(b), SG-FET 60 includes a source layer 61, a drain layer 62, a channel layer 63, a gate dielectric layer 64, a semiconducting gate layer 65, a gate electrode 66, a conducting gate layer 67 and a semiconductor layer 68 formed on a substrate (not shown).

In the SG-FET50 according to the fourth embodiment, the channel layer 53 under the semiconductor gate layer 55 and the channel layer 53 under the conductive gate layer 57 form continuous layers. Unlike the SG-FET50 in the fourth embodiment, in the SG-FET 60 according to the fifth embodiment, as shown in fig. 6(a) and 6(b), the semiconductor layer 68 and the channel layer 63 spaced apart from each other are independently connected to the source layer 61. The semiconductor layer 68 is located below the semiconductor gate layer 65. Channel layer 63 is located below conductive gate layer 67. All possible electrical paths from the gate electrode 66 to the conductive gate layer 67 should include at least a portion of the semiconducting gate layer 65 above the semiconductor layer 68. The conductive gate layer 67 is electrically connected to the gate electrode 66 through the semiconductive gate layer 65. The substrate may be silicon, sapphire, diamond, SiC, AlN, GaN, etc. The source layer 61 and the drain layer 62 may be doped semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, etc., but may also be a metal such as Ni, Au, Al, Cr, etc. The material of the channel layer 63 may be a semiconductor, which may be the same as the semiconductor of the source layer 61 and the drain layer 62 (if they are semiconductors), but may also be other types of semiconductors, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 63 may be doped or undoped, which only affects the threshold voltage of the FET and determines whether the FET is a depletion mode device or an enhancement mode device. The channel layer 63 is electrically connected to the source layer 61 and the drain layer 62. The gate dielectric layer 64 may be a single layer of insulating or semiconducting material, but may also be a combination of insulating and/or semiconducting layers. The material of the semiconductor layer 68 may be the same as the channel layer 63, but may be other kinds of semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 65 comprises a thin layer of moderately doped semiconductor on top of the semiconductor layer 68 and the gate dielectric layer 64. The semiconducting gate layer 65 may be the same material as the channel layer 63, but may also be other thin layer semiconductors such as Si, Ge, SiGe, ZnO, IGZO, and,GaAs、GaN、SiC、MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 65 is electrically connected to the gate electrode 66. The gate electrode 66 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The conductive gate layer 67 may be the same material as the gate electrode 66, but may also be another metal, heavily doped polysilicon, or other heavily doped semiconductor. The material of the semiconductor layer 68 may be the same as the channel layer 63, but may be other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. Semiconductor layer 68 may be doped or undoped, which will only affect the clamped gate voltage. Gate electrode 66 should be located outside of channel layer 63 and semiconductor layer 68 such that gate electrode 66 should not be directly coupled to channel layer 63 and semiconductor layer 68 by electric field effects. A voltage applied to the gate electrode 66 indirectly affects the conductivity of the channel layer 63 and the semiconductor layer 68 through the semiconducting gate layer 65 and the conducting gate layer 67. To provide overvoltage protection, the semiconducting gate layer 65 has the same carrier type as the active channel of the channel layer 63, i.e., when the channel layer 63 is on to allow current to flow along the source layer 61, channel layer 63, and drain layer 62.

Fig. 7(a) is a top view of a field effect transistor according to a sixth embodiment of the present invention; fig. 7(b) is a sectional view of the field effect transistor taken along a broken line in fig. 7 (a). As shown in fig. 7(a) and 7(b), SG-FET 70 includes a source layer 71, a drain layer 72, a channel layer 73, a first gate dielectric layer 74, a semiconducting gate layer 75, a gate electrode 76, a conductive coupling layer 77, and a second gate dielectric layer 78 formed on a substrate (not shown).

Unlike the SG-FETs in the above-described embodiments, the semiconducting gate layer 75 in SG-FET 70 is not disposed directly over the channel layer 73, but is capacitively coupled to the channel layer 73 through the conductive coupling layer 77 and the second gate dielectric layer 78. The substrate may be silicon, sapphire, diamond, SiC, AlN, GaN, etc. The material of the source layer 71 and the drain layer 72 may be a doped semiconductor, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, etc., but may also be a metal such as Ni, Au, Al, Cr, etc. The material of the channel layer 73 may be a semiconductor, which may be the same as the semiconductor of the source layer 71 and the drain layer 72 (if their material is a semiconductor), but may also be another kind of semiconductor, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The channel layer 73 may be doped or undoped, which only affects the threshold voltage of the FET and determines whether the FET is a depletion mode device or an enhancement mode device. The channel layer 73 is electrically connected to the source layer 71 and the drain layer 72. The first gate dielectric layer 74 may be a single layer of insulating or semiconducting material, but may also be a combination of insulating and/or semiconducting layers. The semiconducting gate layer 75 comprises a thin layer of moderately doped semiconductor. The material of the semiconductor gate layer 75 may be the same as the channel layer 73, but may be other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. The semiconducting gate layer 75 is electrically connected to the gate electrode 76. The gate electrode 76 may be a metal, heavily doped polysilicon, or other heavily doped semiconductor. The conductive coupling layer 77 may be the same material as the gate electrode 76, but may also be other metals, heavily doped polysilicon, or other heavily doped semiconductors. The material of the second gate dielectric layer 78 may be the same as the first gate dielectric layer 74, but may also be a single layer of other insulating or semiconducting material, or a combination of other insulating and/or semiconducting layers. A voltage applied to the gate electrode 76 indirectly affects the conductivity of the channel layer 73 through the semiconducting gate layer 75, and the semiconducting gate layer 75 is further coupled to the channel layer 73 through the conductive coupling layer 77. To provide overvoltage protection, the semiconducting gate layer 75 has the same type of carriers as the active channel of channel layer 73, i.e., the type of carriers when channel layer 73 is on to allow current to flow along source layer 71, channel layer 73, and drain layer 72.

Fig. 8(a) is a side view of a first example of a field effect transistor according to a first embodiment of the present invention; fig. 8(b) is a top view of the field effect transistor in fig. 8 (a); FIG. 8(c) is a field effect crystal taken along the dashed line in FIG. 8(b)A cross-sectional view of the tube. As shown in fig. 8(a) to 8(c), the field effect transistor 80 is an enhancement type n-channel FET based on Si CMOS technology. N-type doped silicon is used as the source layer 81 and the drain layer 82. P-type doped silicon is used as the channel layer 83. The material of the gate dielectric layer 84 is silicon dioxide and/or a material such as HfO by thermal oxidation₂、ZrO₂、HfZrO₂And the like. A thin layer of n-type silicon is used as the semiconducting gate layer 85. Alternatively, other n-type semiconductors may be used as the semiconductor gate layer 85, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂CNTs, etc. An n-type semiconducting gate layer 85 is connected to the gate electrode 86. The gate electrode 86 may be heavily doped n-type silicon or other heavily doped n-type semiconductor or metal. Although an n-type field effect transistor is shown in the figure, the field effect transistor 80 can be a p-type field effect transistor with a semiconducting gate that also has an inherent overvoltage protection capability by switching the doping type of all semiconductors in the figure between n-type and p-type.

Fig. 9(a) is a side view of a second example of the field effect transistor according to the first embodiment of the present invention; fig. 9(b) is a top view of the field effect transistor in fig. 9 (a); fig. 9(c) is a sectional view of the field effect transistor taken along a broken line in fig. 9 (b). As shown in fig. 9(a) to 9(c), the field effect transistor 90 is an enhancement type FET. n-type doped silicon is used as the source layer 91 and the drain layer 92. p-type doped silicon is used as the channel layer 93. The material of the gate dielectric layer 94 is silicon dioxide and/or a material such as HfO by thermal oxidation₂、ZrO₂、HfZrO₂And the like. A thin layer of n-type silicon is used as the semiconducting gate layer 95. Alternatively, other n-type semiconductors may be used as the semiconductor gate layer 95, such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂、WSe₂、WS₂Black phosphorus, CNT, and the like. A p-type semiconductor layer 96 is provided over the n-type semiconductor layer 95. The material of the p-type semiconductor layer 96 may be the same as the semiconductor gate layer 95, which helps reduce surface scattering of carriers inside the semiconductor gate layer 95. The material of the semiconductor layer 96 may also be other semiconductors such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, Si, Ge,MoS₂、WSe₂、WS₂black phosphorus, CNT, and the like. The n-type semiconductor gate layer 95 and the p-type semiconductor layer 96 are connected to the gate electrode 97. The gate electrode 97 may be heavily doped n-type silicon or other heavily doped n-type semiconductor or metal. Although in the figure the field effect transistor 90 is an n-type field effect transistor, by switching the doping type of all the semiconductors in the figure between n-type and p-type, the field effect transistor 90 can be changed to a p-type field effect transistor with semiconducting gate, which also has an inherent overvoltage protection capability.

Fig. 10 is a side view of a third example of the field effect transistor according to the first embodiment of the present invention. The field effect transistor 100 is an enhancement mode n-type HEMT based on AlGaN/GaN HEMT technology. The field effect transistor 100 includes a source layer 101, a drain layer 102, a channel layer 103, a gate dielectric layer 104, a semiconducting gate layer 105, a barrier layer 107, a nucleation/buffer layer 108, and a passivation layer 109. The source layer 101 and the drain layer 102 may be Ti/Al/Ni/Au, which may form ohmic contact with the channel layer 103. The channel layer 103 may be GaN. The gate dielectric layer 104 may be AlN or SiN_x、Al₂O₃And the like. Semiconductor gate layer 105 is an n-type semiconductor such as Si, Ge, SiGe, ZnO, IGZO, GaAs, GaN, SiC, MoS₂CNTs, etc. The barrier layer 107 may be AlGaN, which may also include an AlN spacer layer and a GaN cap layer. The nucleation/buffer layer 108 may be AlN, GaN, AlGaN, or the like. The passivation layer 109 may be AlN or SiN_x. Due to spontaneous polarization of the channel layer 103 and the barrier layer 107, a two-dimensional electron gas (2DEG) is formed in the channel layer 103 near the interface between the channel layer 103 and the barrier layer 107. Below the semiconducting gate layer 105, a portion of the barrier layer 107 is recessed to fabricate an enhancement device.

Fig. 11(a) is a side view of a fourth example of the field effect transistor according to the first embodiment of the present invention; fig. 11(b) is a top view of a fourth example of the field effect transistor according to the first embodiment of the present invention. As shown in fig. 11(a) and 11(b), the field effect transistor 110 is a depletion type n-type HEMT based on the AlGaN/GaN HEMT technology. The field effect transistor 110 includes a source layer 111, a drain layer 112, a channel layer 113, a semiconducting gate layer 115, and a gate electrode layer,A barrier layer 117 and a nucleation/buffer layer 118. The source layer 111 and the drain layer 112 may be Ti/Al/Ni/Au, and may form ohmic contact with the channel layer 113. The channel layer 113 may be GaN. The semiconducting gate layer 115 may be a layered two-dimensional semiconductor, such as MoS₂、WSe₂、WS₂Black phosphorus, and the like. The barrier layer 117 may be AlGaN, and the barrier layer 117 may further include an AlN spacer layer and a GaN cap layer. The nucleation/buffer layer 118 may be AlN, GaN, AlGaN, or the like.

FIG. 12(a) shows MoS in a single layer₂The AlGaN/GaN HEMT 110 as a semiconductor gate has a simulated electron density distribution in the gate width direction. FIG. 12(b) shows MoS in a single layer₂The gate width direction simulated potential distribution of AlGaN/gan hemt 110 as a semiconductor gate. The semiconducting gate has a depletion threshold voltage of 2V and the semiconducting gate electrode is biased to 10V. According to simulations, at large forward gate bias, the semiconducting gate is depleted. The effective gate voltage is clamped to the depletion threshold voltage of SG, and excessive gate bias is borne by the semiconducting gate at the channel edge.

FIG. 13(a) shows the transfer curve and gate leakage for an AlGaN/GaN HEMT fabricated with a Ni/Au metal gate. FIG. 13(b) shows MoS in a single layer₂Transfer curve and gate leakage for AlGaN/GaN HEMTs as semiconducting gates. AlGaN/GaN HEMTs were fabricated on AlGaN/GaN heterostructures grown on 4 inch (111) Si substrates. The epitaxial structure consists of a 4 μm GaN buffer/transition layer and a 23.5nm barrier layer (comprising 1.5nm AlN, 20nm AlGaN and 2nm GaN cap). Then growing a single layer of MoS on the sapphire substrate by a modified wet transfer method₂The membrane was transferred to the sample. In implementing SG, such as MoS employed₂The layered two-dimensional material of (a) has several important benefits, such as the feasibility of transferring high quality two-dimensional material crystals on different gate dielectrics and good controllability of the two-dimensional material layer thickness on the SG depletion threshold voltage.

Fig. 14(a) shows the output characteristics of an AlGaN/GaN HEMT having a Ni/Au gate. FIG. 14(b) shows MoS in a single layer₂An AlGaN/GaN HEMT as a semiconductor gate has output characteristics. MG-HEMT and SG-HThe comparison between EMTs shows that there is no loss of drive current for the SG-HEMTs.

FIG. 15(a) shows the subthreshold swing for AlGaN/GaN HEMTs with Ni/Au metal gates and with MoS₂The subthreshold swing of the AlGaN/GaN HEMTs of the semiconducting gates were compared. FIG. 15(b) OFF-STATE BREAK TO AIGaN/GaN HEMT WITH NI/Au METAL GATE AND WITH MOS₂Off-state breakdown of AlGaN/GaN HEMTs of semiconducting gates were compared. Having a MoS₂A semiconducting gate AlGaN/GaN HEMT can effectively turn the HEMT on and off without sacrificing the sub-threshold swing. For SG-HEMTs, subthreshold swings as low as 63mV/dec and 10 can be obtained⁹High on-off current ratio. Furthermore, SG does not affect the breakdown voltage.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.