阅读说明：本技术 一种具有p型埋层的双沟道高耐压氮化镓场效应晶体管 (Double-channel high-voltage-resistance gallium nitride field effect transistor with P-type buried layer ) 是由 王颖 费新星 包梦恬 于成浩 于 2019-10-30 设计创作，主要内容包括：本发明公开了一种具有P型埋层的双沟道高耐压氮化镓场效应晶体管,P型埋层位于缓冲层中，所述第二势垒层和第二沟道层相接触形成二维电子气并与漏极相连，所述漏场板位于钝化层上并向栅极延伸，栅场板位于钝化层上并向漏极延伸。本发明提工作于关态高压时，第二势垒层与第二沟道层形成二维电子气与漏极相连，在栅漏之间引入了新的峰值电场，降低了漏极场板的的峰值电场，P型埋层的加入可以降低栅极场板处的峰值电场使栅漏之间的电场分布更加均匀，进一步的改善了栅漏之间的电场分布，并且P型埋层还降低了器件的泄漏电流，最终使该结构器件相对于传统的场板AlGaN/GaN绝缘栅场效应晶体管，耐压特性上有明显的改善。(The invention discloses a double-channel high-voltage-resistance gallium nitride field effect transistor with a P-type buried layer, wherein the P-type buried layer is positioned in a buffer layer, a second barrier layer is in contact with a second channel layer to form two-dimensional electron gas and is connected with a drain electrode, a drain field plate is positioned on a passivation layer and extends towards a grid electrode, and a grid field plate is positioned on the passivation layer and extends towards the drain electrode. When the structure device works at an off-state high voltage, the second barrier layer and the second channel layer form two-dimensional electron gas which is connected with the drain electrode, a new peak electric field is introduced between the grid and the drain electrode, the peak electric field of the drain electrode field plate is reduced, the peak electric field at the grid electrode field plate can be reduced by adding the P-type buried layer, so that the electric field distribution between the grid and the drain electrode is more uniform, the electric field distribution between the grid and the drain electrode is further improved, the leakage current of the device is also reduced by the P-type buried layer, and finally, the voltage resistance of the structure device is obviously improved compared with that of a traditional field plate AlGaN/GaN insulated grid field effect transistor.)

1. A double-channel high-voltage-resistance gallium nitride field effect transistor with a P-type buried layer comprises a source electrode (301), a drain electrode (302), a drain field plate (303), a grid electrode (304), a grid field plate (305), a grid dielectric layer (306), a passivation layer (307), a first barrier layer (308), a first channel layer (309), a buffer layer (310), a second barrier layer (311), a second channel layer (312), a P-type buried layer (313) and a substrate (314); characterized in that the P-type buried layer (313) is positioned in the buffer layer (310) and has a thickness of H_PLength of W_pA distance L from the source (301)_SP(ii) a A distance T from an interface between the channel layer (309) and the barrier layer (308)_PWherein the channel layer (309) is disposed over the buffer layer (310); the second barrier layer (311) and the second channel layer (312) are located in the buffer layer (310), the second barrier layer (3)11) Contacting with a second channel layer (312) to form a two-dimensional electron gas and connecting with the drain (302), a second barrier layer (311) disposed above the second channel layer (312), the second barrier layer (311) being spaced from the interface between the channel layer (309) and the barrier layer (308) by a distance T_PThe second barrier layer (311) has a thickness H_LBLength of W_LBThe second channel layer (312) has a thickness H_LCLength of W_LC(ii) a The drain field plate (303) is positioned on the passivation layer (307) and extends towards the direction of the grid electrode (304) and has a length L_dfp(ii) a The gate field plate (305) is positioned on the passivation layer (307) and extends towards the drain electrode (302) and has a length L_gfp(ii) a The buffer layer (310) is doped with C or Fe with a doping concentration of 1 × 10¹⁶—2×10¹⁷cm^-3Thickness of T_buffer(ii) a The distance between the source electrode (301) and the drain electrode (302) is L_sdIn the range of 0 to 20 μm; the first barrier layer (308) is arranged above the channel layer (309), the passivation layer (307) is arranged above the first barrier layer (308), the outer side face of the grid electrode (304) except the top is provided with the grid dielectric layer (306), the grid dielectric layer (306) is arranged in the passivation layer (307) and the first barrier layer (308), the source electrode (301) is arranged on one side of the passivation layer (307) and the first barrier layer (308), and the drain electrode (302) is arranged on the other side of the passivation layer (307) and the first barrier layer (308).

2. The double-channel high-withstand-voltage gallium nitride field-effect transistor with the P-type buried layer as claimed in claim 1, characterized in that: a P-type buried layer (313) under the gate field plate and having a doping concentration in the range of 1 × 10¹⁶—1×10¹⁹cm^-3Length range of 0 μm<W_p≤L_sdThickness range of 0 μm<H_P<T_bufferThe distance range from the source (301) is 0 μm<L_SP≤L_sd-W_p(ii) a The distance from the interface between the channel layer (309) and the barrier layer (310) is in the range of 0 [ mu ] m<T_P<T_buffer-H_P。

3. The method of claim 1, wherein said double channel high withstand voltage GaN field effect transistor with P-type buried layerA transistor, characterized by: the second barrier layer (311) and the second channel layer (312) are located below the channel layer, and the doping concentration range of the second barrier layer (311) is 1 multiplied by 10¹⁶—1×10¹⁹cm^-3Length range of 0 μm<W_LB≤L_sd-W_pThickness range of 0 μm<H_LB<T_bufferThe doping concentration range of the second channel layer (312) is 1 multiplied by 10¹⁵—1×10²⁰cm^-3Length range of 0 μm<W_LC≤L_sd-W_pThickness range of 0 μm<H_LC<T_buffer。

4. The double-channel high-withstand-voltage gallium nitride field-effect transistor with the P-type buried layer as claimed in claim 1, characterized in that: the length range of the drain field plate (303) is 0 mu m<L_dfp<5 μm; the length range of the gate field plate (305) is 0 mu m<L_gfp<10μm。

Technical Field

The invention relates to a power device for high withstand voltage of a semiconductor, in particular to a double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor with a P-type buried layer and a field plate.

Background

With the development of technology, it is difficult for the conventional first-generation semiconductor and second-generation semiconductor to meet the demand of the market for the semiconductor, and the development of the third-generation semiconductor is very important. Of which gallium nitride materials are superior. Gallium nitride belongs to a wide bandgap material, and has excellent performances of high critical breakdown electric field, high electron mobility, high temperature resistance, irradiation resistance and the like. Has wide application prospect under the conditions of high pressure, high frequency, high temperature, radiation environment and the like.

The GaN material and the AlGaN material can form an AlGaN/GaN heterojunction, and a two-dimensional electron gas can be formed below a heterojunction interface. The electron concentration of the two-dimensional electron gas can reach 10¹⁹cm^-3Orders of magnitude, which results in GaN devices with lower on-resistance and lower power consumption in device applications. Theoretically, GaN devices can have very high breakdown voltage due to high critical breakdown field, but actually, due to leakage current and non-uniform electric field distribution, the breakdown voltage of GaN devices can not reach its theoretical value. Research on GaN power devices has been conducted by various national research institutes in recent years.

The research of the GaN power device mainly focuses on reducing the leakage current at the time of high drain voltage and optimizing the peak electric field at the gate (without field plate structure) or the gate field plate (with field plate structure), so as to solve the two problems, and the power characteristics of the device can be obviously improved under the condition of not damaging the two-dimensional electron gas of the GaN device. However, there is still a large promotion space for the distribution of electric field in the GaN device with field plate structure, so it is necessary to improve the device design on this structure to further improve the power characteristics of GaN power device.

Disclosure of Invention

The invention provides a double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor with a P-type buried layer and a field plate, aiming at the problems of the conventional GaN power device.

The technical scheme adopted by the invention is as follows:

the invention is provided withThe double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor comprises a source electrode, a drain field plate, a grid electrode, a gate field plate, a gate dielectric layer, a passivation layer, a barrier layer, a channel layer, a buffer layer, a P-type buried layer, a second barrier layer, a second channel layer and a substrate; the P-type buried layer is arranged in the buffer layer and has a thickness of H_PLength of W_pA distance L from the source_SP(ii) a A distance T from an interface between the channel layer and the barrier layer_PWherein the channel layer is disposed over the buffer layer; the second barrier layer and the second channel layer are arranged in the buffer layer, the second barrier layer is in contact with the second channel layer to form two-dimensional electron gas and is connected with the drain electrode, the second barrier layer is arranged above the second channel layer, and the distance between the second barrier layer and the interface between the channel layer and the barrier layer is T_PThe thickness of the second barrier layer is H_LBLength of W_LBThe thickness of the second channel layer is H_LCLength of W_LC(ii) a The drain field plate is positioned on the passivation layer and extends towards the direction of the grid electrode, and the length of the drain field plate is L_dfp(ii) a The gate field plate is positioned on the passivation layer and extends towards the drain electrode direction, and the length of the gate field plate is L_gfp(ii) a The buffer layer is doped with C or Fe with a doping concentration of 1 × 10¹⁶—2×10¹⁷cm^-3Thickness of T_buffer(ii) a The distance between the source electrode and the drain electrode is L_sdIn the range of 0 to 20 μm; the first barrier layer is arranged above the channel layer, the passivation layer is arranged above the first barrier layer, the outer side face of the grid except the top is provided with the grid dielectric layer, the grid dielectric layer is arranged in the passivation layer and the first barrier layer, the source electrode is arranged on one side of the passivation layer and the first barrier layer, and the drain electrode is arranged on the other side of the passivation layer and the first barrier layer. The drain field plate and the grid field plate can modulate the electric field between the grids and the drains, fully optimize the electric field distribution between the grids and the drains and improve the withstand voltage of the device. The second barrier layer and the second channel layer form two-dimensional electron gas on the buffer layer, and the electric field between the gate and the drain can be further optimized. The P-type buried layer can reduce the peak electric field at the gate field plate and improve the breakdown voltage of the device.

Further, the channelThe layer is doped with C or Fe in a concentration of 1 × 10¹⁶—2×10¹⁷cm^-3Thickness of H_ucIn the range of 0 to 1 μm.

Further, a buffer layer below the channel layer and doped with C or Fe with a concentration of 5 × 10¹⁷—1×10¹⁹cm^-3Thickness of H_bufferIn the range of 0 to 4 μm.

Further, the distance between the drain and the gate is L_gdThe range is 3-20 μm.

Further, the P-type buried layer is arranged in the buffer layer and has a doping concentration range of 1 × 10¹⁶—1×10¹⁹cm^-3。

Further, the length of the P-type buried layer is W_pIn the range of 0 μm<W_p≤L_sd，

Further, the distance between the source electrode and the P-type buried layer is L_spIn the range of 0 μm<L_SP≤L_sd-W_p；。

Further, the thickness H of the P-type buried layer_PIn the range of 0 μm<H_P<T_buffer

Further, the distance T between the P-type buried layer and the interface between the barrier layer and the channel layer_PIn the range of 0 μm<T_P<T_buffer-H_P。

To better implement the invention, further, the gate field plate length L_gfpIn the range of 0 μm<L_gfp<10μm。

To better implement the invention, further, the length L of the leakage field plate_dfpIn the range of 0 μm<L_dfp<5μm；

To better implement the present invention, a second barrier layer 311 and a second channel layer 312 are located below the channel layer, and the second barrier layer 311 has a doping concentration ranging from 1 × 10¹⁶—1×10¹⁹cm^-3Length range of 0 μm<W_LB≤L_sd-W_pThickness range of 0 μm<H_LB<T_bufferThe doping concentration range of the second channel layer 312 is 1 × 10¹⁵—1×10²⁰cm^-3Length range of 0 μm<W_LC≤L_sd-W_pThickness range of 0 μm<H_LC<T_buffer。

Compared with the prior art, the invention has the following advantages and beneficial effects:

the second barrier layer and the second channel layer form two-dimensional electron gas in the buffer layer, so that the electric field distribution between the gate and the drain is more uniform. The P-type buried layer is positioned below the gate field plate, so that the peak electric field at the gate field plate can be reduced, and the electric field distribution between the gate and the drain is further optimized. Thereby greatly improving the voltage resistance of the device.

Drawings

Fig. 1 is a schematic structural diagram of a conventional field plate insulated gate AlGaN/GaN field effect transistor.

Fig. 2 is a schematic structural diagram of a field plate insulated gate AlGaN/GaN field effect transistor with only double channels.

Fig. 3 is a schematic structural view of a double-channel withstand-voltage AlGaN/GaN insulated gate field effect transistor having a P-type buried layer and a field plate.

Fig. 4 is a comparison graph of the channel lateral electric field distribution curves when the above three transistors break down.

Fig. 5 is a comparison graph of the breakdown curves of the leakage currents when the above three transistors break down.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is specifically described below with reference to the accompanying drawings.

The invention relates to a double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor with a P-type buried layer and a field plate, which comprises a source electrode 301, a drain electrode 302, a drain field plate 303, a gate electrode 304, a gate field plate 305, a gate dielectric layer 306, a passivation layer 307, a barrier layer 308, a channel layer 309, a buffer layer 310, a second barrier layer 311, a second channel layer 312, a P-type buried layer 313 and a substrate 314, as shown in FIG. 3.

Fig. 1 is a schematic structural diagram of a conventional field plate insulated gate AlGaN/GaN field effect transistor, which can be used as one of the comparative devices of the present invention, and includes: a source 101, a drain 102, a drain field plate 103, a gate 104, a gate field plate 105, a gate dielectric layer 106, a passivation layer 107, a barrier layer 108, a channel layer 109, a buffer layer 110, and a substrate 114. It can be seen that, compared to the present invention, it does not include the P-type buried layer and the double channel structure.

Fig. 2 is a schematic structural diagram of a field plate insulated gate AlGaN/GaN field effect transistor with only dual channels, which can be used as a second comparison device of the present invention, and includes: compared with the structure proposed by the present invention, it does not include a p-type buried layer, and compared with the conventional field plate insulated gate AlGaN/GaN field effect transistor structure in fig. 1, it can be seen that there are one more second barrier layer 211 and one more second channel layer 212, and both are connected to the drain electrode, as shown in the present invention, the structure proposed by the present invention does not include a p-type buried layer.

Fig. 3 is a schematic structural diagram of a double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor having a P-type buried layer and a field plate according to the present invention, which includes a source electrode 301, a drain electrode 302, a drain field plate 303, a gate electrode 304, a gate field plate 305, a gate dielectric layer 306, a passivation layer 307, a first barrier layer 308, a first channel layer 309, a buffer layer 310, a second barrier layer 311, a second channel layer 312, a P-type buried layer 313, and a substrate 314. One more second barrier layer 311, one more second channel layer 312, and one more P-type buried layer 313 than in fig. 1, and one more P-type buried layer 313 than in fig. 2.

By comparing the breakdown characteristics of the structure of fig. 1, the structure of fig. 2 and the structure of the present invention through simulation, the advantages and effects that can be obtained by the present invention can be clearly seen. Fig. 4 is a comparison graph of the lateral electric field distribution curves of the channel during breakdown when the three transistors all adopt the same parameters, and it can be seen that, after the P-type buried layer 313 is added, the peak electric fields at the gate field plate of the conventional field plate insulated gate AlGaN/GaN field effect transistor and the field plate insulated gate AlGaN/GaN field effect transistor with the double channel are obviously reduced, and the electric fields between the gates and the drains are increased to a certain extent. Further exerts the high critical breakdown electric field characteristic of the GaN material, thereby improving the power characteristic of the device.

The improvement of the obtained voltage withstanding effect can be seen from fig. 5, the breakdown voltage of the conventional field plate insulated gate AlGaN/GaN field effect transistor is only 1547V, the field plate insulated gate AlGaN/GaN field effect transistor with double channels is promoted to 1994V, and the voltage withstanding of the double-channel voltage withstanding AlGaN/GaN insulated gate field effect transistor with the P-type buried layer and the field plate proposed by the present invention is obviously enhanced to 2373V. Meanwhile, as can be seen from the comparison of drain-source currents, the double-channel insulated gate AlGaN/GaN field effect transistor with the P-type buried layer and the field plate has obviously reduced leakage current compared with the conventional field plate insulated gate AlGaN/GaN field effect transistor and the field plate insulated gate AlGaN/GaN field effect transistor with the double channels. The double-channel withstand voltage AlGaN/GaN insulated gate field effect transistor with the P-type buried layer and the field plate can effectively improve withstand voltage and reduce device leakage current.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.