阅读说明：本技术 液晶面板以及液晶显示装置
(Liquid crystal panel and liquid crystal display device
) 是由 森永润一 于 2018-07-09 设计创作，主要内容包括：实现一种可抑制由线缺陷引起的生产率下降且可获得高像素开口率的液晶面板。在栅极线(22)与下层源极线(26)交叉的交叉部形成有栅极线开口部(42)，下层源极线(26)与上层源极线(29)通过形成于栅极线开口部(42)的接触孔(45)进行连接。(A liquid crystal panel is realized which can suppress a decrease in productivity caused by a line defect and can obtain a high pixel aperture ratio. A gate line opening (42) is formed at the intersection where the gate line (22) and the lower source line (26) intersect, and the lower source line (26) and the upper source line (29) are connected by a contact hole (45) formed in the gate line opening (42).)
1. A liquid crystal panel is provided with:
a first substrate; and
a second substrate having a first surface and a second surface,
liquid crystal is sandwiched between the first substrate and the second substrate,
the first substrate includes:
a plurality of first wirings;
a second wiring intersecting the plurality of first wirings; and
a third wiring disposed on a layer different from the second wiring and disposed in parallel with the second wiring,
an opening is formed in at least one of all the intersections where the plurality of first wirings and the second wirings intersect,
the second wiring and the third wiring are connected through a contact hole formed in the opening.
2. The liquid crystal panel according to claim 1,
the contact hole is formed near the center of the opening.
3. The liquid crystal panel according to claim 1,
the plurality of first wirings include gate lines,
the second wiring and the third wiring are a first source line and a second source line, respectively.
4. The liquid crystal panel according to claim 1,
the plurality of first wirings include an auxiliary capacitance line,
the second wiring and the third wiring are a first source line and a second source line, respectively.
5. The liquid crystal panel according to claim 1,
the plurality of first wirings include gate lines and auxiliary capacitance lines arranged in parallel with the gate lines,
the second wiring and the third wiring are a first source line and a second source line,
the opening portion includes: a gate line opening formed at an intersection of the gate line and the first source line; and an auxiliary capacitance line opening portion formed at an intersection of the auxiliary capacitance line and the first source line.
6. The liquid crystal panel according to any one of claims 1 to 5,
further provided with: a pixel electrode formed at the same layer as the third wiring.
7. The liquid crystal panel according to claim 6,
the third wiring includes the same material as the pixel electrode.
8. The liquid crystal panel according to any one of claims 1 to 7,
a light shielding film is disposed on the second substrate at a position facing the opening.
9. The liquid crystal panel according to any one of claims 1 to 8,
a common electrode is disposed on the liquid crystal side of the third wiring with an insulating film interposed therebetween.
10. The liquid crystal panel according to claim 9,
the common electrode is disposed at a position facing the opening.
11. The liquid crystal panel according to claim 9 or 10,
the common electrode includes a slit facing the pixel electrode.
12. A liquid crystal display device is characterized in that,
a liquid crystal panel according to any one of claims 1 to 11.
Technical Field
The present invention relates to a liquid crystal panel and a liquid crystal display device.
Background
When a line defect such as a disconnection or a leakage between wirings occurs during the production of the liquid crystal panel, the productivity of the liquid crystal panel is lowered. If these line defects exist at one portion of the liquid crystal panel, the liquid crystal panel is determined to be defective. In a high-definition panel and a large-sized panel, since the number of wirings is large, it is particularly difficult to improve productivity.
The reason for the occurrence of line defects is mainly a design relationship. The source line (data line) is often designed to be a thin line in order to secure the aperture ratio of the pixel and to cope with the occurrence of crosstalk. This makes it highly likely that the source line will be disconnected during the manufacture of the liquid crystal panel. The interlayer insulating film disposed between the source line and the gate line is often designed to be a thin film in order to achieve constant TFT characteristics. This makes it easy to cause an insulating short circuit between layers, such as a source line-gate line short circuit. The breaking and short-circuiting prevent the liquid crystal panel from being qualified.
Patent document 1 discloses a liquid crystal display device having a data line and a redundant data line formed on the data line with an insulating film interposed therebetween, and the data line and the redundant data line are connected via a contact hole.
Disclosure of Invention
Technical problem to be solved by the invention
In the liquid crystal display device of patent document 1, since the contact hole is formed in the vicinity of the pixel opening, there is a possibility that a display failure may occur. Further, since the contact hole impairs the flatness of the pixel, alignment failure of the liquid crystal occurs, and there is a concern that light leakage or the like may occur.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a liquid crystal panel which can suppress a decrease in productivity due to a line defect and can obtain a high pixel aperture ratio.
Means for solving the problems
A liquid crystal panel according to an embodiment of the present invention includes: a first substrate; and a second substrate between which a liquid crystal is sandwiched, the first substrate including: a plurality of first wirings; a second wiring intersecting the plurality of first wirings; and a third wiring disposed on a different layer from the second wiring and disposed parallel to the second wiring, wherein an opening is formed in at least one of all intersections where the plurality of first wirings and the second wiring intersect, and the second wiring and the third wiring are connected through a contact hole formed in the opening.
Effects of the invention
According to an aspect of the present invention, a reduction in productivity due to a line defect can be suppressed and a high pixel aperture ratio can be obtained.
Drawings
Fig. 1 is a block diagram showing a configuration of a main part of a liquid crystal panel according to a first embodiment of the present invention.
Fig. 2 is a plan view showing a detailed configuration of a pixel in a plan view.
Fig. 3 is a plan view showing a configuration of a pixel electrode in plan view.
Fig. 4 is a cross-sectional view showing a cross section of a-a' portion shown in fig. 2 in the liquid crystal panel.
Fig. 5 is a cross section showing a cross section of a portion B-B' shown in fig. 2 in the liquid crystal panel.
Fig. 6 is a flowchart illustrating a flow of a process for forming a gate line and the like on an array substrate.
Fig. 7 is a diagram showing a current path in a case where a disconnection occurs in the lower source line.
Fig. 8 is a diagram showing an example in which a pinhole is formed in a lower source line but a short circuit is not generated between an upper source line and a gate line.
Fig. 9 is a diagram showing an example in which a pinhole is formed in a lower source line, and thus a short circuit is generated between the upper source line and a gate line.
Fig. 10 is a diagram illustrating a first example of a method for repairing a liquid crystal panel in a case where a short circuit occurs.
Fig. 11 is a diagram illustrating a second example of a method for repairing a liquid crystal panel when a short circuit occurs.
Fig. 12 is a diagram showing an orientation unstable region around a contact hole.
Fig. 13 is a plan view illustrating a liquid crystal panel according to a second embodiment of the present invention.
Fig. 14 is a plan view showing a pixel electrode in a plan view.
Fig. 15 is a diagram illustrating the alignment of the liquid crystal when a voltage is applied to the pixel electrode.
Fig. 16 is a plan view showing a configuration of a liquid crystal panel according to a third embodiment of the present invention.
Fig. 17 is a plan view showing a configuration of a pixel electrode constituting a liquid crystal panel in a plan view.
Fig. 18 is a cross-sectional view showing a first example of a cross-section of a portion a-a' shown in fig. 17 in the liquid crystal panel.
Fig. 19 is a cross-sectional view showing a second example of a cross-section of a portion a-a' shown in fig. 17 in the liquid crystal panel.
Fig. 20 is a diagram illustrating the alignment of liquid crystal when a voltage is applied to the pixel electrode.
Fig. 21 is a plan view showing a configuration of a liquid crystal panel according to a fourth embodiment of the present invention.
Fig. 22 is a plan view showing a configuration of a pixel electrode in a plan view.
Fig. 23 is a cross-sectional view showing a first example of a cross-section of a portion a-a' shown in fig. 22 in the liquid crystal panel.
Fig. 24 is a cross-sectional view showing a second example of a cross-section of a portion a-a' shown in fig. 22 in the liquid crystal panel.
Fig. 25 is a diagram illustrating the alignment of liquid crystal when a voltage is applied to the pixel electrode.
Fig. 26 is a plan view showing a configuration of a liquid crystal panel according to a fifth embodiment of the present invention.
Fig. 27 is a plan view showing a configuration of a pixel electrode in a plan view.
Fig. 28 is a plan view showing a configuration of the common electrode in plan view.
Fig. 29 is a cross-sectional view showing a cross section of a-a' portion shown in fig. 26 in the liquid crystal panel.
Fig. 30 is a flowchart for explaining the flow of processing for forming gate lines and the like on the array substrate.
Fig. 31 is a diagram illustrating the alignment of liquid crystal when a voltage is applied to the pixel electrode.
Detailed Description
[ first embodiment ]
A first embodiment according to the present invention will be described below with reference to fig. 1 to 4.
(Structure of liquid Crystal Panel 1)
Fig. 1 is a block diagram showing a configuration of a main part of a liquid crystal panel 1 according to a first embodiment of the present invention. As shown in the figure, the liquid crystal panel 1 includes: a gate driver 11, a source driver 12, a plurality of gate lines 22 (first wirings), a plurality of lower source lines 26 (second wirings, first source lines), and a plurality of upper source lines 29 (third wirings, second source lines). The gate lines 22 are arranged in the horizontal direction in the display region 13, and the lower source lines 26 and the upper source lines 29 are arranged in the vertical direction perpendicular to the gate lines 22 in the display region 13. The upper source line 29 is arranged in parallel with the lower source line 26. Each intersection region 14 where the corresponding gate line 22 intersects the lower source line 26 (upper source line 29) forms a pixel 15. The pixel 15 is configured by three sub-pixels, which are configured by a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel (G). This enables the liquid crystal panel 1 to perform color display. The gate driver 11 is connected to the gate lines 22, and outputs a gate signal to the gate lines 22. The source driver 12 is connected to the lower source line 26, and outputs a source signal (data signal) to the lower source line 26.
Fig. 2 is a plan view showing a detailed configuration of the pixel 15 in plan view. As shown in the figure, a pixel opening 41, a gate line opening 42, and an auxiliary capacitance line opening 43 are formed in the pixel 15. The pixel opening 41 is disposed at a position facing the pixel electrode 30. The pixel electrode 30 is a transparent conductive film such as ITO or IZO. The gate line opening 42 is formed at each intersection of the plurality of gate lines 22 and the lower source line 26. The auxiliary capacitance line opening 43 is disposed at each intersection of the plurality of auxiliary capacitance lines 23 and the lower source line 26.
Fig. 3 is a plan view showing a configuration of the pixel electrode 30 in plan view. As shown in the figure, the pixel electrode 30 is configured as a so-called integral electrode.
Fig. 4 is a cross-sectional view showing a cross section of a-a' portion shown in fig. 2 in the liquid crystal panel 1. Fig. 5 is a cross-sectional view showing a cross section of the portion B-B' shown in fig. 2 in the liquid crystal panel 1. As shown in these figures, the liquid crystal panel 1 includes: an array substrate 21 (first substrate), a gate line 22, an auxiliary capacitance line 23, a first interlayer insulating film 24, a semiconductor layer 25, a lower source line 26, a drain electrode 27, a second interlayer insulating film 28, an upper source line 29, a pixel electrode 30, a liquid crystal 31, a common electrode 32, a color filter 33, a black matrix 34 (light shielding film), and a counter substrate 35 (second substrate). The common electrode 32 is a transparent conductive film such as ITO or IZO.
A gate line 22 and an auxiliary capacitance line 23 are disposed on the array substrate 21. The gate lines 22 are arranged to extend in the horizontal direction. The auxiliary capacitance line 23 is arranged in parallel with the gate line 22. The first interlayer insulating film 24 is disposed so as to cover the gate line 22 and the auxiliary capacitance line 23. The semiconductor layer 25, the lower source line 26, and the drain electrode 27 are disposed on the first interlayer insulating film 24. The semiconductor layer 25 is formed with TFTs. The TFT is a means for controlling a signal of the pixel 15, and is disposed in the vicinity of an intersection of the gate line 22 and the lower source line 26.
The second interlayer insulating film 28 is disposed so as to cover a part of the lower source line 26, the opening of the semiconductor layer 25, and a part of the drain electrode 27. The upper source line 29 is disposed on the second interlayer insulating film 28. A contact hole 45 (first contact hole) is formed in the gate line opening portion 42, and a contact hole 45 (second contact hole) is also formed in the auxiliary capacitance line opening portion 43. The upper source line 29 is connected to the lower source line 26 through a contact hole 45. The lower source line 26 and the upper source line 29 are disposed at positions facing each other. Although not shown in fig. 4 and 5, an alignment film is formed on each inner surface of the liquid crystal panel 1 facing the liquid crystal 31.
A pixel contact hole 44 is formed at an arbitrary position in each pixel opening 41, and the pixel electrode 30 and the drain electrode 27 are connected through the pixel contact hole 44.
A color filter 33 and a black matrix 34 are disposed on the counter substrate 35. A common electrode 32 is disposed on the color filter 33. The liquid crystal 31 is disposed inside the liquid crystal panel 1 and sandwiched between the array substrate 21 and the counter substrate 35.
The pixel signal is input to the drain electrode 27 through the semiconductor layer 25. As a result, the signal potential of the pixel electrode 30 which is electrically connected to the drain electrode 27 through the pixel contact hole 44 is determined. The liquid crystal 31 sandwiched between the common electrode 32 and the pixel electrode 30 is aligned based on the potential of the pixel signal. The pixel transmission amount of light irradiated from a backlight (not shown) disposed on the back surface side of the liquid crystal panel 1 is controlled by the orientations of the respective polarizing plates on the array substrate 21 side and the counter substrate 35 side and the liquid crystal 31.
(Process flow)
Fig. 6 is a flowchart illustrating the flow of processing for forming gate lines and the like on the array substrate 21. When the flow shown in the figure is started, first, the gate line 22 is formed on the surface of the array substrate 21 (step S1). Next, the first interlayer insulating film 24 is formed so as to cover the gate line 22 (step S2). Next, the semiconductor layer 25 is formed on the first interlayer insulating film 24 (step S3). Next, the lower source line 26 and the drain electrode 27 are formed in the same layer as the semiconductor layer 25 (step S4). Next, the second interlayer insulating film 28 is formed so as to cover the lower source line 26 and the like (step S5). Next, an upper source line 29 is formed over the second interlayer insulating film 28 (step S6). Next, the pixel electrode 30 is formed on the same layer as the upper source line 29 (step S7).
The wiring material of the upper source line 29 may be any Al-based or Cu-based material that can reduce the resistance of the upper source line 29. The upper source line 29 and the pixel electrode 30 may be formed simultaneously using the same material so as not to increase the number of masks and the number of manufacturing steps in manufacturing the liquid crystal panel 1.
In the manufacture of the liquid crystal panel 1, the contact hole 45 and the pixel portion contact hole 44 can be formed in the same photolithography step. Therefore, in the method of manufacturing the liquid crystal panel 1, it is not necessary to add a new step for forming the contact hole 45.
(Current Path 52)
Fig. 7 is a diagram showing a current path 52 in a case where a disconnection 51 occurs in the lower source line 26. As shown in the drawing, in the liquid crystal panel 1, the lower source line 26 and the upper source line 29 are connected to each other through two contact holes 45. Thus, the liquid crystal panel 1 is provided with a current path 52 which is connected from the lower source line 26 to the upper source line 29 and is further connected to the lower source line 26. As shown in fig. 7, even if a disconnection 51 occurs in the lower source line 26, the current applied to the lower source line 26 flows normally through the current path 52 and reaches the semiconductor layer 25. Therefore, if disconnection does not occur in the lower source line 26 and the upper source line 29 at the same time, the liquid crystal panel 1 can be qualified.
As shown in fig. 6, the gate lines 22 are often formed in the first layer of the array substrate 21. Therefore, when a line defect occurs in the gate line 22, the gate line 22 having the line defect can be repaired by performing laser repair or photolithography again on the gate line 22 subjected to the failure determination after the patterning of the gate line 22, and the liquid crystal panel 1 can be qualified.
When the lower source line 26 has a pinhole or the like, the second interlayer insulating film 28 may be etched to the first interlayer insulating film 24 when the second interlayer insulating film 28 is etched in the etching step of the second interlayer insulating film 28 for forming the contact hole 45. When this unnecessary etching actually occurs, there is a possibility that the upper source line 29 is short-circuited with the gate line 22 or the auxiliary capacitance line 23 when the upper source line 29 is patterned.
Fig. 8 is a diagram showing an example in which a pinhole 53 is formed in the lower source line 26, but a short circuit is not generated between the upper source line 29 and the gate line 22. In the figure, the contact hole 45 is formed at a position facing the gate line 22. In this case, even if the pinhole 53 is formed in the lower source line 26, the upper source line 29 is in contact with only the array substrate 21.
Fig. 9 is a diagram showing an example in which a short 54 is generated between the upper source line 29 and the gate line 22 due to the pinhole 53 formed in the lower source line 26. In the figure, the contact hole 45 is formed at a position facing the gate line 22. In this case, when a pinhole 53 is formed in the lower source line 26, a short 54 is generated between the upper source line 29 and the gate line 22.
(repair of liquid Crystal Panel 1)
Fig. 10 is a diagram illustrating a first example of a method for repairing the liquid crystal panel 1 when the short circuit 54 occurs. In this figure, a short 54 is created between the underlying source line 26 and the gate line 22. In this case, when the gate line opening 42 is effectively formed at the intersection of the lower source line 26 and the gate line 22, if the removal object 62 near the generation portion of the short circuit 54 in the gate line 22 is cut out by a method such as laser cutting, the line defect of the liquid crystal panel 1 can be eliminated, and the liquid crystal panel 1 can be qualified.
Fig. 11 is a diagram illustrating a second example of the method for repairing the liquid crystal panel 1 when the short circuit 54 occurs. In the drawing, a short circuit 54 is generated between the lower source line 26 and the gate line 22 in the vicinity of the semiconductor layer 25. In this case, if the connection portion 63 of the semiconductor layer 25 is cut by laser dicing or the like, the line defect of the liquid crystal panel 1 can be corrected to a point defect, and the liquid crystal panel 1 can be qualified.
As shown in fig. 2 and the like, in the liquid crystal panel 1, contact holes 45 are also formed at intersections of the auxiliary capacitance lines 23 and the gate lines 22. Thus, even when a short circuit occurs between the lower source line 26 and the auxiliary capacitance line 23, the short circuit can be repaired in the same manner as the repair of the short circuit 54 between the lower source line 26 and the gate line 22. In addition, by increasing the number of contact holes 45, redundancy of the lower source lines 26 and the upper source lines 29 can be further effectively increased.
Fig. 12 is a diagram showing an unstable alignment region 64 around the contact hole 45. The alignment of the liquid crystal 31 is affected by the cross-sectional structure of the liquid crystal panel 1 and the uniformity of the alignment film. Therefore, as shown in fig. 12, it is often difficult to control the alignment of the liquid crystal 31 in the unstable alignment region 64 around the contact hole 45 recessed toward the array substrate 21. As shown in fig. 13, in the liquid crystal panel 1, the contact hole 45 is formed at an intersection (light-shielding portion) distant from the pixel opening 41, and therefore the alignment unstable region 64 is distant from the pixel opening 41. This can stably control the orientation of the liquid crystal 31 in the pixel opening 41, and thus can improve the display quality of the liquid crystal panel 1.
As described above, according to the first embodiment, it is possible to realize the liquid crystal panel 1 which can suppress a decrease in productivity due to a line defect and obtain a high pixel aperture ratio. Further, similarly to the liquid crystal panel 1, a liquid crystal display device (not shown) including the liquid crystal panel 1 also has an advantage that a high pixel aperture ratio can be obtained while suppressing a decrease in productivity due to a line defect.
(modification example)
The contact hole 45 is preferably disposed near the center of the gate line opening 42 (or the storage capacitor line opening 43). This can more effectively prevent a decrease in the pixel aperture ratio and a decrease in the display quality.
In the liquid crystal panel 1, it is not always necessary to provide the gate line openings 42 at all intersections where the plurality of gate lines 22 intersect the lower source lines 26. In other words, the gate line opening 42 may be provided at least at any one of all the intersections, and the contact hole 45 may be provided at least at any one of all the intersections. For example, the contact hole 45 may not be provided at a position where the columnar spacer for maintaining the cell thickness of the liquid crystal panel 1 is provided. In this case, since the area of the columnar spacer to be provided is reduced, the columnar spacer having sufficient strength can be provided, and the cell thickness of the liquid crystal panel 1 can be maintained normally.
[ second embodiment ]
A second embodiment according to the present invention will be described below with reference to fig. 13 to 15. In the present embodiment, the same component numbers are assigned to components common to the first embodiment, and detailed description thereof will not be repeated unless otherwise particularly required.
(Structure of liquid Crystal Panel 1B)
Fig. 13 is a plan view showing a liquid crystal panel 1B according to a second embodiment of the present invention in plan view. The liquid crystal panel 1B includes the same components as those constituting the liquid crystal panel 1 according to the first embodiment. However, the liquid crystal panel 1B and the liquid crystal panel 1 differ in the shape of the pixel electrode 30.
Fig. 14 is a plan view showing the pixel electrode 30 in a plan view. As shown in the figure, the pixel electrode 30 has a so-called fishbone shape. The liquid crystal panel 1B operates in a VA (Vertical Alignment) mode. When a voltage is applied to the liquid crystal 31 controlled by the vertical alignment film, the liquid crystal 31 is aligned so as to fall from one end of each branch portion constituting the pixel electrode 30 toward the inside of the pixel electrode 30.
(alignment direction of liquid Crystal 31)
Fig. 15 is a diagram illustrating the alignment of the liquid crystal 31 when a voltage is applied to the pixel electrode 30. As shown in the figure, the pixel electrode 30 is divided into four regions 71 to 74. When a voltage is applied to the liquid crystal 31, the liquid crystal 31 corresponding to the regions 71 to 74 is aligned so as to fall down in different alignment directions 81 to 84 toward the inside of the pixel electrode 30. In the liquid crystal panel 1B, the orientation of the liquid crystal 31 is controlled in four different directions, so that the viewing angle dependence of the liquid crystal 31 can be reduced, and uniform display can be realized over a wide viewing angle range.
In the cross region 85 which is the main portion of the pixel electrode 30, the liquid crystals 31 collide with each other in different orientations, and therefore, the liquid crystal panel 1B often forms a dark line. The dark line is a portion where sufficient light transmittance cannot be obtained because control of the liquid crystal 31 is difficult. In the second embodiment, the contact hole 45 is provided in the pixel ineffective region 86 which is an intersection of the cross region 85 and the upper source line 29. This can suppress a decrease in the aperture ratio of the pixel 15.
In the liquid crystal panel 1B, the alignment of the liquid crystal 31 can be stabilized by PSA treatment or the like. The PSA process applied to the liquid crystal panel 1B is a process of sealing a liquid crystal material containing a monomer in the liquid crystal panel 1B and irradiating ultraviolet rays or the like while applying a voltage to the pixels 15 to promote polymerization of the liquid crystal 31 at the interface of the alignment film. Thus, in the liquid crystal mode in which the liquid crystal 31 is aligned using the vertical alignment film, an initial alignment having a constant tilt angle can be imparted to the liquid crystal 31. As a result, the alignment of the liquid crystal 31 is stabilized without being lost, and the display quality is improved. Also, the response speed and transmittance of the display are improved.
[ third embodiment ]
A third embodiment according to the present invention will be described below with reference to fig. 16 to 20. In the present embodiment, members common to the other embodiments are given the same reference numerals, and detailed description thereof will not be repeated unless otherwise particularly required.
(Structure of liquid Crystal Panel 1C)
Fig. 16 is a plan view showing a configuration of a liquid crystal panel 1C according to a third embodiment of the present invention in plan view. Fig. 17 is a plan view showing a configuration of the pixel electrode 30 constituting the liquid crystal panel 1C in plan view. The liquid crystal panel 1C includes at least the same components as those constituting the liquid crystal panel 1 according to the first embodiment. However, the liquid crystal panel 1C and the liquid crystal panel 1 differ in the shape of the pixel electrode 30. The liquid crystal panel 1C has slits 91 formed in the pixel electrodes 30 in accordance with an MVA (multi-domain Vertical Alignment) mode. The liquid crystal panel 1C further includes an alignment controller 92 formed on the same layer as the common electrode 32.
Fig. 18 is a cross-sectional view showing a first example of a cross-section of a portion a-a' shown in fig. 17 in the liquid crystal panel 1C. Fig. 19 is a cross-sectional view showing a second example of a cross-section of a portion a-a' shown in fig. 17 in the liquid crystal panel 1C. The alignment controller 92 may be a protrusion made of resin as shown in fig. 18, or may be a slit formed in the common electrode 32 as shown in fig. 19. In either configuration, the alignment controller 92 has a function of controlling the alignment of the liquid crystal 31 to which a voltage is applied.
(alignment direction of liquid Crystal 31)
Fig. 20 is a diagram illustrating the alignment of the liquid crystal 31 when a voltage is applied to the pixel electrode 30. When a voltage is applied to the liquid crystal 31, the liquid crystal 31 is aligned in any of different alignment directions 95 to 98 from the slit 91 toward the alignment controller 92 depending on the position where the liquid crystal 31 is disposed. The electric field generated at the edge of the slit 91 of the pixel electrode 30 is engaged with the control direction of the liquid crystal 31 by the alignment controller 92, whereby the alignment of the liquid crystal 31 is stabilized. By stably controlling the orientation of the liquid crystal 31 in the liquid crystal panel 1C in four different directions, the viewing angle dependence of the liquid crystal 31 can be reduced. This makes it possible to realize the liquid crystal panel 1C capable of performing uniform display in a wide viewing angle range.
In the liquid crystal panel 1C operating in the MVA mode, as shown in fig. 20, the alignment directions of the liquid crystals 31 are changed by 90 ° between the upper half region and the lower half region of the pixel electrode 30. Thus, the boundary portion between the upper half region and the lower half region of the pixel electrode 30 is often a dark line 94 where the orientations of the liquid crystal 31 collide with each other. The dark line 94 is a portion where sufficient light transmittance cannot be obtained because control of the liquid crystal 31 is difficult. In the third embodiment, the contact hole 45 is provided in the pixel ineffective area which is the intersection of the dark line 94 and the upper source line 29. This can suppress a decrease in the aperture ratio of the pixel 15.
In the liquid crystal panel 1C, as in the second embodiment, the alignment of the liquid crystal 31 can be stabilized by PSA treatment or the like.
[ fourth embodiment ]
A fourth embodiment according to the present invention will be described below with reference to fig. 21 to 25. In the present embodiment, members common to the other embodiments are given the same reference numerals, and detailed description thereof will not be repeated unless otherwise particularly required.
(Structure of liquid Crystal Panel 1D)
Fig. 21 is a plan view showing a configuration of a liquid crystal panel 1D according to a fourth embodiment of the present invention in plan view. Fig. 22 is a plan view showing a configuration of the pixel electrode 30 in plan view. The liquid crystal panel 1D includes at least the same components as those constituting the liquid crystal panel 1 according to the first embodiment. However, the liquid crystal panel 1D and the liquid crystal panel 1 differ in the shape of the pixel electrode 30. The liquid crystal panel 1D corresponds to a CPA (Continuous flame Alignment) mode, and a slit 101 parallel to the gate line 22 is formed in the pixel electrode 30. The pixel electrode 30 is divided into 5 octagonal partial electrodes. The liquid crystal panel 1D further includes an alignment controller 102 formed on the same layer as the common electrode 32.
Fig. 23 is a cross-sectional view showing a first example of a cross-section of a portion a-a' shown in fig. 22 in the liquid crystal panel 1D. Fig. 24 is a cross-sectional view showing a second example of a cross-section of a portion a-a' shown in fig. 22 in the liquid crystal panel 1D. The alignment controller 102 may be a resin protrusion formed on the common electrode 32 as shown in fig. 23, or may be a slit formed in the common electrode 32 as shown in fig. 24. In either structure, the alignment controller 102 has a function of controlling the alignment of the liquid crystal 31 to which a voltage is applied.
(alignment direction of liquid Crystal 31)
Fig. 25 is a diagram illustrating the alignment of the liquid crystal 31 when a voltage is applied to the pixel electrode 30. When a voltage is applied to the liquid crystal 31, the liquid crystal 31 is aligned in any one of a plurality of different alignment directions 103 from the edge of the pixel electrode 30 toward the alignment controller 92, depending on the position where the liquid crystal 31 is disposed. The electric field generated at the edge of the pixel electrode 30 is engaged with the control direction of the liquid crystal 31 by the alignment controller 102, whereby the alignment of the liquid crystal 31 is stabilized. By stably controlling the alignment of the liquid crystal 31 in the liquid crystal panel 1D to a plurality of different alignment directions 103, the viewing dependence of the display in the liquid crystal panel 1D can be reduced. This makes it possible to realize a liquid crystal panel 1D capable of performing uniform display over a wide viewing angle range.
In the liquid crystal panel 1D operating in the CPA mode, as in the first embodiment, contact holes 45 are formed at the intersections of the gate lines 22 and the lower source lines 26 and at the intersections of the gate lines 22 and the auxiliary capacitance lines 23, respectively. This makes it possible to share the loss portion, and thus, the light transmittance of the pixel electrode 30 can be improved.
In the liquid crystal panel 1D, as in the second embodiment, the alignment of the liquid crystal 31 can be stabilized by PSA treatment or the like.
[ fifth embodiment ]
A fifth embodiment according to the present invention will be described below with reference to fig. 26 to 31. In the present embodiment, members common to the other embodiments are given the same reference numerals, and detailed description thereof will not be repeated unless otherwise particularly required.
(Structure of liquid Crystal Panel 1E)
Fig. 26 is a plan view showing a configuration of a liquid crystal panel 1E according to a fifth embodiment of the present invention in plan view. Fig. 27 is a plan view showing a configuration of the pixel electrode 30 in plan view. Fig. 28 is a plan view showing a configuration of the common electrode 32 in plan view. The liquid crystal panel 1E includes at least the same components as those constituting the liquid crystal panel 1 according to the first embodiment. However, the liquid crystal panel 1E differs from the liquid crystal panel 1 in the alignment mode of the liquid crystal 31. The liquid crystal panel 1E corresponds to a horizontal electric field ffs (fringe field switching) mode. The shape of the pixel electrode 30 is the same as that of the first embodiment. Slits 111 are formed in the common electrode 32, and the slits 111 have a constant inclination angle with respect to the gate lines 22 and are substantially parallel to the horizontal direction (the arrangement direction of the gate lines 22).
Fig. 29 is a cross-sectional view showing a cross section of a portion a-a' shown in fig. 26 in the liquid crystal panel 1E. The liquid crystal panel 1E further includes a third interlayer insulating film 112 and a planarizing film 113. The third interlayer insulating film 112 is formed on the second interlayer insulating film 28 so as to cover the pixel electrode 30 and the upper source line 29, respectively. The third interlayer insulating film 112 is not formed on the counter substrate 35, but is formed on the third interlayer insulating film 112. A planarization film 113 is formed on the color filter 33.
(Process flow)
Fig. 30 is a flowchart illustrating the flow of processing for forming gate lines and the like on the array substrate 21. When the flow shown in the figure is started, first, the gate line 22 is formed on the surface of the array substrate 21 (step S11). Next, the first interlayer insulating film 24 is formed so as to cover the gate line 22 (step S12). Next, the semiconductor layer 25 is formed on the first interlayer insulating film 24 (step S13). Next, the lower source line 26 and the drain electrode 27 are formed in the same layer as the semiconductor layer 25 (step S14). Next, the second interlayer insulating film 28 is formed so as to cover the lower source line 26 and the like (step S15). Next, an upper source line 29 is formed over the second interlayer insulating film 28 (step S16). Next, the pixel electrode 30 is formed on the same layer as the upper source line 29 (step S17). Next, the third interlayer insulating film 112 is formed so as to cover the pixel electrode 30 and the like (step S18). Next, the common electrode 32 is formed on the third interlayer insulating film 112 (step S19). Thereby ending the flow shown in fig. 30.
(alignment direction of liquid Crystal 31)
Fig. 31 is a diagram illustrating the alignment of the liquid crystal 31 when a voltage is applied to the pixel electrode 30. When a voltage is applied to the liquid crystal 31, an electric field is generated between the pixel electrode 30 and the common electrode 32 in an electric field direction 122 intersecting with the extending direction 121 of the slit 111. The liquid crystal 31 aligned along the initial alignment axis 123 moves in such a manner as to rotate in the rotation direction 124 based on the intensity of the generated electric field. Thereby, the alignment of the liquid crystal 31 is controlled, and gray scale display in the liquid crystal panel 1E is realized.
In the liquid crystal panel 1E operating in the FFS mode, contact holes 45 are formed at intersections of the gate lines 22 and the lower source lines 26, as in the first embodiment and the like. This makes it possible to share the loss portion, and thus, the light transmittance of the pixel electrode 30 can be improved.
In the liquid crystal panel 1E, an auxiliary capacitance can be formed between the pixel electrode 30 and the common electrode 32 facing each other with the third interlayer insulating film 112 interposed therebetween. Therefore, the liquid crystal panel 1E may not include the auxiliary capacitance line 23. In the liquid crystal panel 1E without the auxiliary capacitance line 23, the alignment state of the liquid crystal 31 is different between the upper half area and the lower half area of the pixel 15. Therefore, the boundary between the upper half region and the lower half region is often a dark line region. Therefore, if the contact hole 45 is provided at a position facing the dark line region in the lower source line 26, the loss portion can be supplied, and thus, a decrease in the aperture ratio (light transmittance) of the pixel 15 can be suppressed as in the first embodiment.
[ conclusion ]
A liquid crystal panel (1) according to embodiment 1 of the present invention is a liquid crystal panel (1) including a first substrate (21) and a second substrate (35), a liquid crystal (31) being interposed between the first substrate and the second substrate, the first substrate including: a semiconductor device includes a plurality of first wirings (22), a second wiring (lower source line 26) intersecting the plurality of first wirings, and a third wiring (upper source line 29) arranged in a layer different from the second wiring and parallel to the second wiring, wherein an opening (gate line opening 42) is formed in at least one of all intersections where the plurality of first wirings and the second wiring intersect, and the second wiring and the third wiring are connected through a contact hole (45) formed in the opening.
According to the structure, a decrease in productivity due to line defects can be suppressed and a high pixel aperture ratio can be obtained.
A liquid crystal panel according to mode 2 of the present invention is the liquid crystal panel according to mode 1, wherein the contact hole is formed in a vicinity of a center of the opening.
According to the structure, the reduction of the pixel aperture ratio and the reduction of the display quality can be more effectively prevented.
In the liquid crystal panel according to mode 3 of the present invention, in mode 1, the plurality of first wirings include gate lines (22), and the second wirings and the third wirings are first source lines (lower source lines 26) and second source lines (upper source lines 29), respectively.
In the liquid crystal panel according to aspect 4 of the present invention, in aspect 1, the plurality of first wirings include an auxiliary capacitance line (23), and the second wirings and the third wirings are a first source line (lower source line 26) and a second source line (upper source line 29), respectively.
A liquid crystal panel according to aspect 5 of the present invention is the liquid crystal panel according to aspect 1, wherein the plurality of first wirings include a gate line (22) and an auxiliary capacitance line (23) arranged parallel to the gate line, the second wirings and the third wirings are a first source line (lower source line 26) and a second source line (upper source line 29), respectively, and the opening portion includes: a gate line opening (42) formed at the intersection of the gate line and the first source line, and an auxiliary capacitance line opening (43) formed at the intersection of the auxiliary capacitance line and the first source line.
A liquid crystal panel according to mode 6 of the present invention is characterized by further including, in addition to any of modes 1 to 5, a pixel electrode (30) formed on the same layer as the third wiring.
In the liquid crystal panel according to mode 7 of the present invention, in mode 6, the third wiring is made of the same material as the pixel electrode.
According to the structure, the manufacturing method of the liquid crystal panel can be simplified.
A liquid crystal panel according to aspect 8 of the present invention is the liquid crystal panel according to any one of aspects 1 to 7, wherein a light shielding film (black matrix 34) is disposed at a position of the second substrate facing the opening.
A liquid crystal panel according to mode 9 of the present invention is characterized in that, in any of the modes 1 to 8, a common electrode (32) is disposed on the liquid crystal side of the third wiring with an insulating film (second interlayer insulating film 28) interposed therebetween.
A liquid crystal panel according to mode 10 of the present invention is characterized in that, in mode 9, the common electrode is disposed at a position facing the opening.
A liquid crystal panel according to mode 11 of the present invention is characterized in that, in addition to mode 9 or 10, the common electrode includes a slit (91) facing the pixel electrode.
A liquid crystal display device according to mode 12 of the present invention is characterized by including the liquid crystal panel according to any of modes 1 to 11.
According to the above-described structure, a liquid crystal display device in which a reduction in productivity due to a line defect is suppressed and a high pixel aperture ratio can be obtained can be realized.
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in the respective different embodiments are also included in the technical scope of the present invention. By combining the technical means disclosed in the respective embodiments, new technical features can be formed.
Description of the reference numerals
1. 1B, 1C, 1D, 1E liquid crystal panel;
11 a gate driver;
12 a source driver;
13 a display area;
14 an intersection part;
15 pixels;
21 an array substrate;
22 gate lines;
23 auxiliary capacitance lines;
24 a first interlayer insulating film;
25TFT；
26 a lower source line;
27 a drain electrode;
28 a second interlayer insulating film;
29 upper source line;
30 pixel electrodes;
31 a liquid crystal;
32 a common electrode;
33 a color filter;
34 a black matrix;
35 a counter substrate;
41 pixel opening parts;
42 a gate line opening part;
43 auxiliary capacitance line opening part;
44 pixel portion contact holes;
45 contact holes;
51, breaking the wire;
52 a current path;
53 pinholes;
54 short-circuiting;
62 removing the object;
63 a connecting part;
64 orientation unstable regions;
region 71;
81. 95, 103 directions;
85 cross area;
an 86 pixel inactive area;
91. 101, 111 slits;
92. 102 an orientation control body;
94 dark lines;
112 a third interlayer insulating film;
113 a planarization film;
121 in the direction of extension;
122 direction of electric field;
123 an initial orientation axis;
124 direction of rotation
