阅读说明：本技术 集成有金属-氧化物-金属(mom)电容器的芯片上共面波导(cpw)传输线 (On-chip coplanar waveguide (CPW) transmission line integrated with metal-oxide-metal (MOM) capacitor ) 是由 成海涛 金章 于 2018-06-14 设计创作，主要内容包括：一种共面波导可以包括在第一互连层级处在第一接地平面与第二接地平面之间延伸的第一传输线。共面波导还可以包括在第二互连层级处的屏蔽层。屏蔽层可以包括耦合到第一接地平面的第一组导电指。第一组导电指可以与耦合到第二接地平面的第二组导电指相互交叉。仅电介质层可以在第一组导电叉指与第二组导电叉指之间。第一接地平面、第二接地平面、电介质层和屏蔽层可以形成电容器。(A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shield layer at the second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers coupled to a second ground plane. Only the dielectric layer may be between the first set of conductive fingers and the second set of conductive fingers. The first ground plane, the second ground plane, the dielectric layer, and the shield layer may form a capacitor.)

1. A coplanar waveguide, comprising:

a first transmission line extending between the first ground plane and the second ground plane at a first interconnect level; and

a shield layer at a second interconnect level, the shield layer comprising a first set of conductive fingers coupled to the first ground plane and interdigitated with a second set of conductive fingers coupled to the second ground plane, and only a dielectric layer between the first and second sets of conductive fingers, the first ground plane, the second ground plane, the dielectric layer, and the shield layer comprising a capacitor.

2. Coplanar waveguide according to claim 1, wherein said first interconnect level is different from said second interconnect level.

3. A coplanar waveguide according to claim 1, further comprising a second transmission line between the first transmission line and one of the first and second ground planes.

4. Coplanar waveguide according to claim 1, wherein said coplanar waveguide is on a chip or on a Printed Circuit Board (PCB).

5. A coplanar waveguide according to claim 1, wherein said first set of conductive fingers are coupled to said first ground plane by a first set of vias and said second set of conductive fingers are coupled to said second ground plane by a second set of vias.

6. Coplanar waveguide according to claim 1, wherein said shielding layer comprises traces of metal or polysilicon.

7. Coplanar waveguide according to claim 1, wherein said capacitor comprises a metal-oxide-metal (MOM) capacitor.

8. The coplanar waveguide of claim 1, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

9. A method for fabricating a coplanar waveguide, comprising:

fabricating a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level;

fabricating a first set of shield layer fingers interdigitated with a second set of shield layer fingers at a second interconnect level, wherein only a dielectric layer is between the first set of shield layer fingers and the second set of shield layer fingers;

electrically coupling the first set of shield layer fingers to the first ground plane with a first set of vias; and

electrically coupling the second set of shield layer fingers to the second ground plane with a second set of vias.

10. The method of claim 9, further comprising fabricating a second transmission line between the first transmission line and one of the first ground plane and the second ground plane.

11. The method of claim 9, in which the coplanar waveguide is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

12. A coplanar waveguide, comprising:

a first transmission device extending between the first ground plane and the second ground plane at a first interconnect level; and

a shield layer at a second interconnect level, the shield layer comprising a first set of conductive fingers coupled to the first ground plane and interdigitated with a second set of conductive fingers coupled to the second ground plane, and only a dielectric layer between the first and second sets of conductive fingers, the first ground plane, the second ground plane, the dielectric layer, and the shield layer comprising a capacitor.

13. Coplanar waveguide according to claim 12, wherein said first interconnection level is different from said second interconnection level.

14. Coplanar waveguide according to claim 12, further comprising second transmission means between said first transmission means and one of said first ground plane and said second ground plane.

15. Coplanar waveguide according to claim 14, wherein said first transmission means and said second transmission means transmit differential signals.

16. Coplanar waveguide according to claim 12, wherein said coplanar waveguide is on a chip or on a Printed Circuit Board (PCB).

17. Coplanar waveguide according to claim 12 wherein said first set of conductive fingers is coupled to said first ground plane by a first set of vias and said second set of conductive fingers is coupled to said second ground plane by a second set of vias.

18. Coplanar waveguide according to claim 12, wherein said shielding layer comprises traces of metal or polysilicon.

19. Coplanar waveguide according to claim 12, wherein said capacitor comprises a metal-oxide-metal (MOM) capacitor.

20. The coplanar waveguide of claim 12, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held Personal Communication Systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

Technical Field

The present disclosure relates generally to wireless communication systems, and more particularly to on-chip coplanar waveguide (CPW) transmission lines integrated with metal-oxide-metal (MOM) capacitors.

Background

Electrical interconnections for active devices may exist at each level of the system hierarchy, ranging from the lowest system level to the highest system level. For example, an interconnect layer may connect different devices together on an integrated circuit. As integrated circuits become more complex, more interconnect layers provide electrical connections between devices. Recently, the number of interconnect levels of a circuit has increased dramatically due to the large number of devices currently interconnected in modern electronic equipment. The increased number of interconnect levels for supporting the increased number of components involves a more complex process.

These interconnect layers may provide transmission line structures for interconnecting Integrated Circuit (IC) devices in high frequency circuit designs. For example, high frequency circuit designs may use coplanar waveguides as transmission lines to support Radio Frequency (RF) through millimeter wave frequencies. These high frequency designs may enable millimeter wave communication systems that can replace and/or supplement microstrips with coplanar waveguides to carry extremely high frequency radio signals.

Conventional coplanar waveguide circuits include conductors fabricated between two ground planes. The ground plane and conductors may be fabricated on the surface of a dielectric substrate or other similar circuit material. This configuration is referred to as a ground-signal-ground (GSG) transmission line structure. That is, coplanar waveguides include planar transmission line structures consisting of various conductor arrays arranged in the same geometric plane.

The coplanar waveguide includes its main ground in the form of a wide strip adjacent to the active conductor. These transmission line structures may use ground conductors that are coplanar with the active signal conductors to provide a signal return path. The signal return path may be on the same interconnect (e.g., metallization) layer as the active conductor. Unfortunately, this arrangement, while improving performance, reduces the number of available interconnects because the signal return lines occupy routing area.

Disclosure of Invention

A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The coplanar waveguide may further include a shield layer at the second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers coupled to a second ground plane. Only the dielectric layer may be between the first set of conductive fingers and the second set of conductive fingers. The first ground plane, the second ground plane, the dielectric layer, and the shield layer may form a capacitor.

A method for fabricating a coplanar waveguide may include fabricating a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The method may also include fabricating a first set of shield layer fingers interdigitated with a second set of shield layer fingers at a second interconnect level. Only the dielectric layer may be between the first set of shield fingers and the second set of shield fingers. The method may also include electrically coupling the first set of shield layer fingers to the first ground plane with the first set of vias. The method may also include electrically coupling a second set of shield layer fingers to a second ground plane with a second set of vias.

A coplanar waveguide may include a first transmission device. The first transmission means may extend between the first ground plane and the second ground plane at a first interconnect level. The coplanar waveguide may further include a shield layer at the second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane. The first set of conductive fingers may be interdigitated with a second set of conductive fingers coupled to a second ground plane. Only the dielectric layer may be between the first set of conductive fingers and the second set of conductive fingers. The first ground plane, the second ground plane, the dielectric layer, and the shield layer may form a capacitor.

Additional features and advantages of the disclosure will be described hereinafter. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

Drawings

For a more complete understanding of this disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawing.

Fig. 1 is a schematic diagram of a Radio Frequency (RF) front end (RFFE) module employing passive devices.

Fig. 2A and 2B illustrate a conventional terrestrial-signal-terrestrial (GSG) transmission line structure.

Fig. 3 is a cross-section illustrating an Integrated Circuit (IC) device including an interconnect stack containing a metal-oxide-metal (MOM) capacitor structure.

Fig. 4A and 4B illustrate a coplanar waveguide transmission line structure with a capacitor according to aspects of the present disclosure.

Fig. 5A and 5B illustrate coplanar waveguide transmission line structures with capacitors in accordance with aspects of the present disclosure.

Fig. 6 is a process flow diagram illustrating a method for integrating a coplanar waveguide transmission line structure with a capacitor in accordance with an aspect of the present disclosure.

Fig. 7 is a block diagram illustrating an exemplary wireless communication system in which configurations of the present disclosure may be advantageously employed.

FIG. 8 is a block diagram of a design workstation illustrating circuit, layout, and logic design for semiconductor components according to one configuration.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details in order to provide a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

As used herein, the use of the term "and/or" is intended to mean an "inclusive or" and the use of the term "or" is intended to mean an "exclusive or". As described herein, the term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration," and is not necessarily to be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used throughout this specification refers to a "connection," whether directly or indirectly through an intermediate connection (e.g., a switch), whether electrical, mechanical, or otherwise, and is not necessarily limited to a physical connection. Additionally, the connection may be such that the objects are permanently connected or releasably connected. The connection may be made through a switch. As used herein, the term "proximate" as used throughout the specification means "adjacent, very close, immediately adjacent, or proximate". As described herein, the term "on … …" used throughout the specification refers to "directly on … …" in certain configurations, and "indirectly on … …" in other configurations.

Electrical interconnections for active devices may exist at each level of the system hierarchy, ranging from the lowest system level to the highest system level. In particular, the interconnect layer may connect different devices together on an Integrated Circuit (IC). As integrated circuits become more complex, more interconnect layers provide electrical connections between these devices. Recently, the number of interconnect levels of circuitry has increased dramatically due to the large number of devices currently interconnected in modern mobile Radio Frequency (RF) equipment. The increased number of interconnect levels for supporting the increased number of components involves a more complex process.

These interconnect layers may provide transmission line structures for interconnecting IC devices in high frequency circuit designs. These high frequency circuit designs may use coplanar waveguides as transmission lines to support RF through millimeter wave frequencies. For example, high frequency designs may implement millimeter wave communication systems that can replace and/or supplement microstrips with coplanar waveguides to carry extremely high frequency radio signals.

Conventional coplanar waveguide circuits include conductors fabricated between two ground planes. The ground plane and conductors may be fabricated on the surface of a dielectric substrate or other similar circuit material. This configuration is referred to as a ground-signal-ground (GSG) or ground-signal-Ground (GSSD) transmission line structure. That is, coplanar waveguides include planar transmission line structures consisting of various conductor arrays arranged in the same geometric plane.

The coplanar waveguide includes its main ground in the form of a wide strip adjacent to the active conductor. These transmission line structures use ground conductors that are coplanar with the signal conductors to provide signal return paths on the same interconnect (e.g., metallization) layer as the active conductors. Unfortunately, this arrangement, while ensuring optimum performance, reduces the number of interconnections that can be provided since the signal return lines occupy valuable routing area in mobile RF devices.

The passive devices in the mobile RF device may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, metal-insulator-metal (MIM), poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures. Capacitors are typically passive components used to store charge in integrated circuits. For example, parallel plate capacitors are typically made using plates or structures that are conductive with insulating material between the plates. The storage or capacitance of a given capacitor depends on the materials of the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is typically a dielectric material.

These parallel plate capacitors may occupy a large area on a semiconductor chip because many designs place the capacitors on the substrate of the chip. Unfortunately, this approach takes up a significant amount of substrate area, which reduces the available area for active devices. Another approach is to create vertical structures, which can be referred to as Vertical Parallel Plate (VPP) capacitors. The VPP capacitor structure can be created by stacking interconnect layers on a chip.

VPP capacitor structures, however, have lower capacitance storage or lower "density" because these structures do not store a large amount of charge. In particular, the size of the interconnect and via level interconnect traces used to fabricate the VPP capacitor may be very small. The spacing between interconnect lines and via layer conductive traces in a VPP structure is limited by design rules, which typically result in a large area required to achieve some desired capacitance for such structures. Although described as "vertical," these structures may be in any direction substantially perpendicular to the surface of the substrate, or at other angles that are not substantially parallel to the substrate.

The MOM capacitor is an example of a VPP capacitor. MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. In particular, MOM capacitors can be high quality capacitors in semiconductor processing without incurring the expense of additional processing steps relative to other capacitor structures. MOM capacitor structures achieve capacitance by using the fringe capacitance created by the set of fingers. That is, MOM capacitors utilize lateral capacitive coupling between plates formed by metallization layers and routing traces.

Various aspects of the present disclosure integrate a ground-signal-ground (GSG) or ground-signal-ground (GSSG) transmission line structure with a capacitor (e.g., MOM capacitor). The process flow for fabricating these MOM capacitors may include a front-end-of-line (FEOL) process, an intermediate-end-of-line (MOL) process, and a back-end-of-line (BEOL) process. It should be understood that the term "layer" includes films and, unless otherwise specified, should not be construed as indicating a vertical or horizontal thickness. As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange increases the degree of confidence.

As described above, the back-end-of-line interconnect layer may refer to a conductive interconnect layer (e.g., metal one (M1), metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to a front-end-of-line active device of the integrated circuit. The back-end-of-line interconnect layer may be electrically coupled to an intermediate-line interconnect layer used, for example, to connect M1 to an Oxide Diffusion (OD) layer of the integrated circuit. A back-end-of-line first via (V2) may connect M2 to M3 or other back-end-of-line interconnect layers.

On-chip transmission lines may be used for interconnect and power transfer in millimeter wave Radio Frequency Integrated Circuits (RFICs). Unfortunately, these on-chip transmission lines occupy a significant portion of the on-chip area, since the signal lines are between the ground lines. According to aspects of the present disclosure, the region for shielding the signal line is used to form a capacitor (e.g., MOM capacitor). That is, the unused area occupied for shielding the signal line is reused to form a capacitor while also shielding the transmission line. The ground line remains well connected at RF frequencies and isolated at lower frequencies by a capacitor.

A coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The waveguide further includes a shield layer at a second interconnect level. The shielding layer may include a first set of conductive fingers coupled to the first ground plane and interdigitated with a second set of conductive fingers coupled to the second ground plane. The dielectric layer may be between the first set of fingers and the second set of fingers. A dielectric layer without additional conductive features is located between the fingers. The first ground plane, the second ground plane, the dielectric layer, and the shield layer may form a capacitor.

Fig. 1 is a schematic diagram of a Radio Frequency (RF) front end (RFFE) module 100 employing passive devices including a capacitor 116 that may be integrated with a coplanar waveguide transmission line. The RF front end module 100 includes a power amplifier 102, a duplexer/filter 104, and a Radio Frequency (RF) switch module 106. The power amplifier 102 amplifies the signal to a certain power level for transmission. The duplexer/filter 104 filters the input/output signal according to various parameters including frequency, insertion loss, rejection, or other similar parameters. Additionally, the RF switch module 106 may select certain portions of the input signal to pass on to the rest of the RF front end module 100.

The Radio Frequency (RF) front end module 100 also includes tuner circuitry 112 (e.g., first tuner circuitry 112A and second tuner circuitry 112B), a duplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuitry 112 (e.g., the first tuner circuitry 112A and the second tuner circuitry 112B) includes components such as a tuner, a portable data input terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuitry 112 may perform impedance tuning (e.g., Voltage Standing Wave Ratio (VSWR) optimization) for the antenna 114. The RF front-end module 100 also includes a passive combiner 108 coupled to a Wireless Transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuitry 112A and the second tuner circuitry 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides the information to a modem 130 (e.g., a Mobile Station Modem (MSM)). The modem 130 provides the digital signal to an Application Processor (AP) 140.

As shown in fig. 1, a duplexer 190 is located between the tuner components of the tuner circuitry 112 and the capacitor 116, inductor 118, and antenna 114. A duplexer 190 may be placed between the antenna 114 and the tuner circuitry 112 to provide high system performance from the RF front-end module 100 to a chipset including the wireless transceiver 120, the modem 130, and the application processor 140. The duplexer 190 also performs frequency domain multiplexing on the high-band frequencies and the low-band frequencies. After duplexer 190 performs its frequency multiplexing function on the input signal, the output of duplexer 190 is fed to an optional LC (inductor/capacitor) network including capacitor 116 and inductor 118. The LC network may provide additional impedance matching components for the antenna 114 when desired. Then, a signal having a specific frequency is transmitted or received by the antenna 114. Although a single capacitor and inductor are shown, multiple components are also contemplated.

Fig. 2A and 2B are schematic diagrams of a conventional coplanar waveguide transmission line structure of a ground-signal-ground (GSG) configuration. Representatively, fig. 2A shows a coplanar waveguide transmission line structure 200 including an active conductor 220 between two ground planes 210. The two ground planes 210 and the active conductor 220 may be fabricated on the surface of a dielectric substrate or other similar circuit material (not shown). This configuration is referred to as a ground-signal-ground (GSG) transmission line structure. That is, the coplanar waveguide includes a planar transmission line structure composed of various conductor arrays in the same geometric plane and shielded by, for example, the shielding layer 230. The shield layer 230 may be coupled to the two ground planes 210 by vias 240.

Fig. 2B shows a 3D view 250 of a conventional coplanar waveguide including a main ground in the form of a wide strip (e.g., 210) adjacent to an active conductor (e.g., 220). These transmission line structures use ground conductors that are coplanar with the signal conductors to provide signal return paths on the same interconnect (e.g., metallization) layer as the active conductors. Unfortunately, this arrangement, while ensuring high performance, reduces the number of interconnects that can be provided because the signal return lines occupy routing area.

As further shown in fig. 2A, the shield layer 230 coupled to the two ground planes 210 by the vias 240 also occupies valuable space in mobile Radio Frequency (RF) devices. On-chip transmission lines such as coplanar waveguide transmission line structure 200 may be used for interconnection and power transmission in millimeter wave Radio Frequency Integrated Circuits (RFICs). Unfortunately, these on-chip transmission lines occupy a significant portion of the on-chip area when the signal lines are between ground lines. According to aspects of the present disclosure, the shielding layer 230 may be reconfigured to incorporate passive devices, such as capacitors, as shown in fig. 3.

Capacitors are widely used in analog integrated circuits. Fig. 3 is a block diagram illustrating a cross-section of an analog Integrated Circuit (IC) device 300 including an interconnect stack 310. The interconnect stack 310 of the IC device 300 includes a plurality of conductive interconnect layers (e.g., M1, … …, M9, M10) located on a semiconductor substrate (e.g., a diced silicon wafer) 302. The semiconductor substrate 302 supports a metal-oxide-metal (MOM) capacitor 360. In this example, MOM capacitor 360 is formed in the M3 and M4 interconnect layers. The MOM capacitor 360 is formed of lateral conductive fingers of different polarities using the conductive interconnect layers (e.g., M3 and M4) of the interconnect stack 310. A dielectric (not shown) is between the conductive fingers. In aspects of the present disclosure, only the dielectric layer is between the conductive fingers.

In this example, the MOM capacitor 360 is formed within a lower conductive interconnect layer (e.g., M1-M4) of the interconnect stack 310. The lower conductive interconnect layer of the interconnect stack 310 has a smaller interconnect width and space. For example, for a signal line, the dimensions of the lower conductive interconnect layer may have a width and space that is at least 10 times smaller than the top conductive interconnect layer. The smaller interconnect width and space of the lower conductive interconnect layer enables the formation of MOM capacitors with increased capacitance density. As shown in fig. 3, MOM capacitor 360 utilizes lateral (intralevel) capacitive coupling 340 between fingers (e.g., 350, 370) formed by standard metallization of conductive interconnects (e.g., wires and vias).

In aspects of the present disclosure, a coplanar waveguide may include a first transmission line extending between a first ground plane and a second ground plane at a first interconnect level. The waveguide further includes a shield layer at a second interconnect level. The shielding layer may include a first set of conductive fingers (e.g., 350-1, 350-2, 350-3) coupled to the first ground plane and interdigitated with a second set of conductive fingers (e.g., 370-1, 370-2) coupled to the second ground plane. A dielectric material is located between the fingers. The first ground plane, the second ground plane, and the shielding layer may form a MOM capacitor. The MOM capacitor may also provide shielding for the transmission line. The MOM capacitor in the shielding layer of the transmission line structure is further described in fig. 4A and 4B.

Fig. 4A and 4B illustrate a coplanar waveguide transmission line structure with a capacitor according to aspects of the present disclosure. For example, the coplanar waveguide transmission line structure may be a ground-signal-ground (GSG) transmission line structure.

Referring to fig. 4A, the coplanar waveguide transmission line structure 400 includes a capacitor 440. According to aspects, the coplanar waveguide transmission line structure 400 may be on a chip or on a Printed Circuit Board (PCB). The coplanar waveguide transmission line structure 400 may include a signal line 420 (e.g., a first transmission line) extending between ground planes 410 (e.g., a first ground plane 410-1 and a second ground plane 410-2). For example, the signal line 420 may transmit an RF signal, and may be fabricated at an upper interconnect layer (e.g., metal 7(M7) or metal 8 (M8)). The transmission of RF signals through the upper interconnect layers (e.g., M7/M8) ensures reduced RF signal loss and improved RF signal integrity.

According to aspects of the present disclosure, the coplanar waveguide transmission line structure 400 may further include a shield layer 430. For example, shield layer 430 may include conductive traces (e.g., metal or polysilicon). The shielding layer 430 may include a first set of conductive fingers 432 interdigitated with a second set of conductive fingers 434. In this example, the shield layer 430 is fabricated at a lower interconnect layer (e.g., metal 1(M1) or intermediate process (MOL) interconnect layer (M0)). The first set of conductive fingers 432 is coupled to the first ground plane 410-1. Additionally, a second set of conductive fingers 434 is coupled to the second ground plane 410-2. In this example, each of the first set of conductive fingers 432 and the second set of conductive fingers 434 extends across the signal line 420.

In accordance with additional aspects of the present disclosure, a dielectric layer (not shown) may be between the first set of conductive fingers 432 and the second set of conductive fingers 434 that cross each other to form the capacitor 440. The conductive fingers 432 may be coupled to the first ground plane 410-1 through a first set of vias (not shown). Additionally, the second set of conductive fingers 434 may be coupled to the second ground plane 410-2 by a second set of vias (not shown). For example, the vias may be fabricated at an interconnect level below the ground plane 410, such as at the same level as the first and second sets of conductive fingers 432, 434 (e.g., via 1(V1) or via 0 (V0)).

According to aspects of the present disclosure, the ground plane 410 (e.g., 410-1, 410-2), the dielectric layer, and the shield layer 430 may form a capacitor 440. For example, the capacitor 440 may be a MOM (metal-oxide-metal) capacitor formed in the shielding layer 430 of the RF signal path. The capacitor 440 at the shield layer 430 may also provide shielding for the signal line 420. The ground plane 410 may remain well connected at RF frequencies while maintaining isolation at lower frequencies through the capacitor 440.

Fig. 4B shows a 3D view of the coplanar waveguide transmission line structure 400 of fig. 4A. As described above, the coplanar waveguide transmission line structure 400 may include signal lines 420 between ground planes 410 (e.g., 410-1, 410-2). The signal lines 420 may be at a first interconnect level (e.g., M7/M8). The shield layer 430 may be at a second interconnect level (e.g., M1/M0) below the first interconnect level. The capacitor 440 may be formed from the first set of conductive fingers 432 and the second set of conductive fingers 434 that cross each other to capture fringe capacitance.

Fig. 5A and 5B illustrate coplanar waveguide transmission line structures with capacitors in accordance with aspects of the present disclosure. For example, the coplanar waveguide transmission line structure may be a ground-signal-ground (GSSG) transmission line structure.

Referring to fig. 5A, a coplanar waveguide transmission line structure 500 includes a capacitor 540, according to aspects of the present disclosure. For example, the coplanar waveguide transmission line structure 500 may include a first signal line 520 (e.g., a first transmission line) and a second signal line 522 (e.g., a second transmission line) between ground planes 510 (e.g., a first ground plane 510-1 and a second ground plane 510-2). The first signal line 520 and the second signal line 522 may be used for differential signals. The shield layer 530 may include a first set of conductive fingers 532 and a second set of conductive fingers 534. In this configuration, the first set of conductive fingers 532 is coupled to the first ground plane 510-1. Additionally, the second set of conductive fingers 534 are coupled to the second ground plane 510-2, and each conductive finger may extend beyond both the first signal line 520 and the second signal line 522.

Fig. 5B shows a 3D view of the coplanar waveguide transmission line structure 500 of fig. 5A. According to aspects of the present disclosure, the first signal line 520 and the second signal line 522 may be at a first interconnect level (e.g., M7/M8). The shield layer 530 may be at a second interconnect level (e.g., M1/M0) below the first interconnect level. A capacitor 540 (e.g., a MOM capacitor) may be formed from the first set of conductive fingers 532 interdigitated with the second set of conductive fingers 534. In this configuration, the capacitor 540 may be wider than the capacitor 440 shown in fig. 4A and 4B because the first and second sets of conductive fingers 532, 534 extend farther beyond both the first and second signal lines 520, 522 relative to the first and second ground planes 510-1, 510-2, respectively. According to aspects of the present disclosure, more than two signal lines may be included. For example, a third signal line may be included in addition to the first signal line 520 and the second signal line 522.

An on-chip transmission line including a MOM capacitor in a shielding layer may enable millimeter wave Radio Frequency Integrated Circuit (RFIC) applications for interconnects to transfer power. According to aspects of the present disclosure, a MOM capacitor is formed in a region of a shielding layer for shielding a signal line. These capacitors serve the dual purpose of storing energy and shielding the signal lines. The ground line remains well connected at RF frequencies, while isolation is maintained at lower frequencies by the MOM capacitor.

Fig. 6 is a process flow diagram illustrating a method 600 for fabricating a coplanar waveguide in accordance with an aspect of the present disclosure. In block 602, a first transmission line extending between a first ground plane and a second ground plane is fabricated at a first interconnect level, e.g., as shown in fig. 4A-5B. In block 604, a first set of shield layer fingers is fabricated at a second interconnect level and interdigitated with a second set of shield layer fingers. The first and second sets of shield layer fingers may be first and second sets of conductive fingers 432, 434 as shown in fig. 4A and 4B. A dielectric material may be deposited between the fingers. In block 606, a first set of shield layer fingers is electrically coupled to the first ground plane through the first set of vias. In block 608, a second set of shield layer fingers is electrically coupled to the second ground plane through the second set of vias.

According to another aspect of the present disclosure, a coplanar waveguide is described. In one configuration, the coplanar waveguide includes a first transmission device and a second transmission device. In one configuration, the first transmission means may be, for example, a first signal line 520 as shown in fig. 5A and 5B. In one configuration, the second transmission means may be, for example, a second signal line 522 as shown in fig. 5A and 5B. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means.

Fig. 7 is a block diagram illustrating an example wireless communication system 700 in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration, FIG. 7 shows three remote units 720, 730, and 750 and two base stations 740. It will be appreciated that a wireless communication system may have many more remote units and base stations. Remote units 720, 730, and 750 include IC devices 725A, 725B, and 725C that include the disclosed coplanar waveguides. It will be appreciated that other devices may also include the disclosed coplanar waveguides, such as base stations, switch devices, and network devices. Fig. 7 shows forward link signals 780 from the base stations 740 to the remote units 720, 730, and 750 and reverse link signals 790 from the remote units 720, 730, and 750 to base stations 740.

In fig. 7, remote unit 720 is shown as a mobile telephone, remote unit 730 is shown as a portable computer, and remote unit 750 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held Personal Communication Systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or a combination thereof. Although FIG. 7 shows remote units in accordance with aspects of the disclosure, the disclosure is not limited to these exemplary shown units. Aspects of the present disclosure may be applicable to many devices that include the disclosed coplanar waveguides.

Fig. 8 is a block diagram of a design workstation showing the circuit, layout and logic design for a semiconductor component, such as the coplanar waveguide disclosed above. The design workstation 800 includes a hard disk 801, the hard disk 801 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 800 also includes a display 802 to facilitate the design of the circuit 810 or coplanar waveguide 812. The storage medium 804 is provided for tangibly storing a design of the circuit 810 or coplanar waveguide 812. The design of circuit 810 or coplanar waveguide 812 may be stored on storage medium 804 in a file format such as GDSII or GERBER. The storage medium 804 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Further, the design workstation 800 includes a drive 803 for accepting input from the storage medium 804 or writing output to the storage medium 804.

The data recorded on the storage medium 804 may specify a logic circuit configuration, pattern data for a lithography mask, or mask pattern data for a serial write tool such as e-beam lithography. The data may also include logic verification data, such as timing diagrams or network circuits associated with logic simulation. Providing data on the storage medium 804 facilitates the design of the circuit 810 or coplanar waveguide 812 by reducing the number of processes used to design semiconductor wafers.

For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. As used herein, the term "memory" refers to long term, short term, volatile, nonvolatile, or other types of memory and is not to be limited to a particular type of memory or number of memories, or type of media upon which memory is stored.

If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer readable media encoded with a data structure and computer readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage media may be a available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media which can be used to store desired program code in the form of instructions or data structures and which can be accessed by a computer; disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In addition to being stored on a computer-readable medium, the instructions and/or data may also be provided as signals on a transmission medium included in the communication device. For example, the communication device may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. For example, relational terms such as "above" and "below" are used with respect to a substrate or an electronic device. Of course, if the substrate or electronic device is inverted, the upper side becomes the lower side, and vice versa. Additionally, if oriented laterally, above and below may refer to the sides of the substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding configurations described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store specified program code means in the form of instructions or data structures and which can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the invention is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.