阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 赵南奎 金锡勋 姜明一 慎居明 李承勋 李正允 崔珉姬 崔正鍲 于 2019-07-03 设计创作，主要内容包括：一种半导体器件包括：在衬底上沿第一方向延伸的有源鳍；沿第二方向延伸并与有源鳍交叉的栅电极；在栅电极的两个侧壁上的栅极间隔层；以及在栅电极的至少一侧的有源鳍的凹陷区域中的源极/漏极区域。源极/漏极区域可以包括基层,该基层与有源鳍接触并且具有在凹陷区域的内侧壁上在第一方向上彼此相对的内端和外端。源极/漏极区域可以包括基层上的第一层。第一层可以包括浓度高于基层中包括的锗(Ge)的浓度的锗(Ge)。基层的外端可以与第一层接触,并且可以具有在平面上朝向栅电极的外部凸出的形状。(A semiconductor device includes: an active fin extending in a first direction on a substrate; a gate electrode extending in the second direction and crossing the active fin; gate spacers on both sidewalls of the gate electrode; and a source/drain region in the recessed region of the active fin on at least one side of the gate electrode. The source/drain region may include a base layer contacting the active fin and having inner and outer ends opposite to each other in the first direction on an inner sidewall of the recess region. The source/drain regions may include a first layer on the base layer. The first layer may include germanium (Ge) having a higher concentration than that included in the base layer. The outer end of the base layer may be in contact with the first layer, and may have a shape protruding toward the outside of the gate electrode on a plane.)

1. A semiconductor device, comprising:

a substrate;

an active fin on the substrate, the active fin extending along a first direction, the active fin including a recessed region;

a gate electrode on the substrate, the gate electrode crossing the active fin such that the recessed region of the active fin is on at least one side of the gate electrode, the gate electrode extending in a second direction, the gate electrode including a sidewall;

a gate spacer on the sidewalls of the gate electrode; and

source/drain regions in the recessed region of the active fin,

the source/drain region includes a base layer in contact with the active fin and a first layer on the base layer,

the base layer includes inner and outer ends opposite to each other in the first direction,

the base layer is located on the inner side wall of the recessed region,

the first layer includes germanium (Ge) at a concentration higher than a concentration of germanium (Ge) in the base layer,

the outer end of the base layer is in contact with the first layer, and

the outer end of the base layer has a shape protruding outward in a plane toward the outside of the gate electrode.

2. The semiconductor device of claim 1, wherein at least a portion of the inner end of the base layer is located below the gate electrode.

3. The semiconductor device of claim 1, wherein

The first layer has an inner end and an outer end opposite to each other in the first direction on an inner side wall of the recess region, and

the outer end of the first layer has a region protruding outward from the gate electrode in a plane.

4. The semiconductor device of claim 3, wherein at least a portion of the inner end of the first layer is located below the gate spacer layer.

5. The semiconductor device of claim 1, wherein the base layer and at least a portion of the first layer are located below the gate spacer layer on an inner sidewall of the recessed region.

6. The semiconductor device of claim 1, wherein the base layer is formed of silicon (Si).

7. The semiconductor device of claim 1, wherein an outer end of the base layer is not defined by a crystallographic plane of the active fin.

8. The semiconductor device of claim 1, wherein the first layer is a silicon germanium (SiGe) layer comprising germanium (Ge) in a range of 20 at.% to 40 at.%.

9. The semiconductor device of claim 1, wherein

The source/drain region further comprises a second layer on the first layer,

the second layer fills the recessed region, and

the second layer includes germanium (Ge) at a higher concentration than germanium (Ge) in the first layer.

10. The semiconductor device of claim 1, wherein the inner end of the base layer comprises a region extending perpendicular to the upper surface of the substrate.

11. The semiconductor device of claim 1, wherein the base layer comprises germanium (Ge) at a higher concentration than germanium (Ge) in the active fin.

12. The semiconductor device of claim 1, wherein the base layer comprises boron (B) or gallium (Ga) at a higher concentration than germanium (Ge) in the active fin.

13. The semiconductor device of claim 1, wherein the base layer has a thickness in a range of 3nm to 5 nm.

14. The semiconductor device of claim 1, wherein

The gate electrode includes a first side and a second side opposite the first side,

the source/drain regions are located at both the first and second sides of the gate electrode,

a length from an outer end of the base layer on one side to an outer end of the base layer on the other side along a center of the active fin in the second direction is greater than a length from the outer end of the base layer on one side to the outer end of the base layer on the other side along an edge of the active fin in the second direction.

15. The semiconductor device of claim 1, wherein

The source/drain regions have a first width in the second direction and a second width in the second direction,

the first width is in a region adjacent the gate electrode,

the second width is in a region spaced apart from the gate spacer layer, and

the second width is greater than the first width.

16. The semiconductor device of claim 1, further comprising:

contact plugs on the source/drain regions, wherein

The contact plug is connected to the source/drain region.

17. A semiconductor device, comprising:

a substrate;

an active fin on the substrate, the active fin extending in one direction on the substrate, the active fin including a recessed region;

a gate electrode on the substrate, the gate electrode extending and intersecting the active fin such that a recessed region of the active fin is located on at least one side of the gate electrode; and

a source/drain region in the recessed region of the active fin, the source/drain region comprising a first layer and a second layer having different concentrations of germanium (Ge),

an end portion of the first layer, in which the first layer is in contact with the second layer located on an inner side wall of the recess region, has a region protruding toward an outside of the gate electrode in a plane.

18. The semiconductor device of claim 17, wherein

An end portion of the active fin defined by the recess region has a region protruding toward an outside of the gate electrode in a plane.

19. The semiconductor device of claim 17, further comprising:

a base layer under the first layer, wherein

The base layer is in contact with the active fin, and

the base layer includes germanium (Ge) at a concentration lower than that included in the first layer.

20. The semiconductor device of claim 19, wherein an end portion of the base layer where the base layer contacts the active fin located on an inner sidewall of the recess region has a region recessed in a plane toward an outside of the gate electrode.

21. A semiconductor device, comprising:

a substrate;

an active fin on the substrate, the active fin extending in one direction on the substrate, the active fin including a recessed region;

a gate electrode on the substrate, the gate electrode extending and intersecting the active fin such that a recessed region of the active fin is located on at least one side of the gate electrode; and

an epitaxial layer in the recessed region of the active fin,

at least one of an end portion of the active fin and an end portion of the epitaxial layer, which is defined by the recess region in at least one side of the gate electrode, has a region protruding toward an outside of the gate electrode in a plane.

22. The semiconductor device of claim 21, wherein

The end portion of the active fin has a region recessed toward the outside of the gate electrode in a plane, and

the end portion of the epitaxial layer has a region protruding toward the outside of the gate electrode in a plane.

23. The semiconductor device of claim 21, further comprising:

a first layer and a second layer on the epitaxial layer in the recessed region, wherein

The first layer and the second layer have different concentrations of germanium (Ge), and

the epitaxial layer, the first layer and the second layer form a source/drain region.

24. The semiconductor device of claim 23, wherein the epitaxial layer comprises germanium (Ge) at a concentration lower than a concentration of germanium (Ge) in the first layer.

25. The semiconductor device of claim 21, wherein the epitaxial layer is silicon (Si).

Technical Field

The present inventive concept relates to semiconductor devices.

Background

As the demand for high performance, high speed, and/or versatility of semiconductor devices has increased, the integration degree of semiconductor devices has increased. When manufacturing a semiconductor device corresponding to a high integration trend of the semiconductor device, the semiconductor device may include a pattern having a fine width or a fine separation distance. In addition, in order to adjust the operating characteristics due to the size reduction of a planar metal oxide semiconductor fet (mosfet), a semiconductor device including a FinFET having a channel with a three-dimensional structure has been developed.

Disclosure of Invention

An aspect of the inventive concept is to provide a semiconductor device having improved electrical characteristics.

According to an aspect of the inventive concept, a semiconductor device includes: a substrate; an active fin on a substrate, the active fin extending along a first direction, the active fin including a recessed region; a gate electrode on the substrate, the gate electrode crossing the active fin such that a recess region of the active fin is located on at least one side of the gate electrode, the gate electrode extending in a second direction, the gate electrode including a sidewall; a gate spacer on sidewalls of the gate electrode; and source/drain regions in the recessed region of the active fin. The source/drain region may include a base layer in contact with the active fin and a first layer on the base layer. The base layer may include inner and outer ends opposite to each other in the first direction. The base layer may be located on an inner sidewall of the recess region. The first layer may include germanium (Ge) having a higher concentration than that included in the base layer, and an outer end of the base layer may be in contact with the first layer. The outer end of the base layer may have a shape protruding outward in a plane toward the outside of the gate electrode.

According to an aspect of the inventive concept, a semiconductor device includes: a substrate; an active fin on a substrate, the active fin extending in one direction on the substrate, the active fin including a recessed region; a gate electrode on the substrate, the gate electrode extending and crossing the active fin such that a recessed region of the active fin is located on at least one side of the gate electrode; and source/drain regions located in the recessed region of the active fin. The source/drain regions may include first and second layers having different concentrations of germanium (Ge). An end portion of the first layer, in which the first layer may be in contact with the second layer located on an inner sidewall of the recess region, may have a region protruding toward an outside of the gate electrode on a plane.

According to an aspect of the inventive concept, a semiconductor device includes: a substrate; an active fin on a substrate, the active fin extending in one direction on the substrate, the active fin including a recessed region; a gate electrode on the substrate, the gate electrode extending and crossing the active fin such that a recessed region of the active fin is located on at least one side of the gate electrode; and an epitaxial layer in the recessed region of the active fin. At least one of the end of the active fin and the end of the epitaxial layer may have a region protruding toward the outside of the gate electrode on a plane. The ends of the active fin may be defined by recessed regions in at least one side of the gate electrode.

Drawings

The above and other aspects, features and other effects of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan view illustrating a semiconductor device according to an example embodiment;

fig. 2A to 2D are sectional views illustrating a semiconductor device according to example embodiments;

fig. 3 is a partially enlarged plan view illustrating a semiconductor device according to an example embodiment;

fig. 4A and 4B are cross-sectional views illustrating a portion of a semiconductor device according to example embodiments;

fig. 5A to 6B are plan and sectional views illustrating a semiconductor device according to example embodiments;

fig. 7A and 7B are a plan view and a sectional view illustrating a semiconductor device according to an example embodiment;

fig. 8 is a plan view illustrating a semiconductor device according to an example embodiment;

fig. 9A and 9B are a plan view and a sectional view illustrating a semiconductor device according to an example embodiment;

fig. 10A and 10B are a plan view and a sectional view illustrating a semiconductor device according to an example embodiment;

fig. 11A to 20B are diagrams illustrating a process sequence of a method of manufacturing a semiconductor device according to an example embodiment;

fig. 21A to 23B are diagrams illustrating a process sequence of a method of manufacturing a semiconductor device according to an example embodiment;

FIG. 24 is a circuit diagram of an SRAM cell including a semiconductor device according to an example embodiment;

fig. 25 is a block diagram showing an electronic apparatus including a semiconductor device according to an example embodiment; and

fig. 26 is a schematic diagram of a system including a semiconductor device according to an example embodiment.

Detailed Description

Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 is a plan view illustrating a semiconductor device according to an example embodiment.

Fig. 2A to 2D are sectional views illustrating a semiconductor device according to example embodiments. Fig. 2A to 2D show cross sections of the semiconductor device of fig. 1 taken along the lines IIa-IIa ', IIb-IIb', IIc-IIc ', and IId-IId'. For ease of illustration, only some components of the semiconductor device are shown in fig. 1-2D.

Referring to fig. 1 to 2D, the semiconductor device 100 may include a substrate 101, an active fin 105, an element isolation layer 110, source/drain regions 150, a gate structure 160, and an interlayer insulating layer 190. The gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, and gate spacers 166. The semiconductor device 100 may include a FinFET element — a transistor in which the active fin 105 has a fin structure. The FinFET element may include transistors that cross each other based on the location of the active fin 105 and the gate structure 160. For example, the transistor may be a PMOS transistor.

The substrate 101 may have an upper surface extending in the X-direction and the Y-direction. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may comprise silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like.

The element isolation layer 110 may define an active fin 105 in the substrate 101. The element isolation layer 110 may be formed using, for example, a Shallow Trench Isolation (STI) process. According to example embodiments, the element isolation layer 110 may include a region extending deeper toward a lower portion of the substrate 101 between the active fins 105. The element isolation layer 110 may have a curved upper surface having a level that becomes higher toward the active fin 105, but the shape of the upper surface of the element isolation layer 110 is not limited thereto. The element isolation layer 110 may be formed of an insulating material. The element isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

The active fin 105 may be defined by the element isolation layer 110 in the substrate 101, and may extend in a first direction (e.g., an X direction). The active fin 105 may have a structure of an active fin protruding from the substrate 101. The upper end of the active fin 105 may protrude from the upper surface of the element isolation layer 110 by a desired (and/or alternatively, a predetermined) amount. The active fin 105 may be formed from a portion of the substrate 101 and may include an epitaxial layer grown from the substrate 101. Meanwhile, a portion of the active fin 105 on the substrate 101 may be recessed on both sides of the gate structure 160, and the source/drain region 150 may be disposed on the recessed active fin 105. Accordingly, as can be seen by comparing fig. 2C and 2D, active fin 105 may have a relatively high height below gate structure 160. According to an example embodiment, active fin 105 may include impurities.

The source/drain regions 150 may be disposed on recessed regions RC in both sides of the gate structure 160 and/or adjacent to both sides of the gate structure 160, in which each active fin 105 is recessed. The recess region RC extends in the X direction between the gate structures 160, and may have inner sidewalls at both ends in the X direction and a bottom surface between the inner sidewalls. The source/drain region 150 may be provided as a source region or a drain region of a transistor. The upper surface of the source/drain region 150 may be located at the same or similar height level as the lower surface of the gate structure 160, as shown in fig. 2A. Meanwhile, according to example embodiments, the relative heights of the source/drain regions 150 and the gate structure 160 may be variously changed. For example, the source/drain region 150 may have the form of a raised source/drain in which the upper surface is located higher than the lower surface of the gate structure 160 (specifically, the gate electrode 165).

As shown in fig. 2D, the source/drain region 150 may have a pentagonal or similarly shaped cross-section taken in the Y-direction. Meanwhile, in example embodiments, the source/drain region 150 may have various shapes, for example, one of a polygonal shape, a circular shape, and a rectangular shape. Further, the source/drain region 150 may have a cross section taken in the X direction with a flat upper surface, as shown in fig. 2A, and may have a circular shape, an elliptical shape, or the like below the upper surface. Meanwhile, in example embodiments, the above shape may be variously changed according to a distance between adjacent gate structures 160, a height of the active fin 105, and the like.

The source/drain region 150 may include a base layer 151 and first to fifth layers 152, 153, 154, 155, and 156 sequentially stacked in the recess region RC. The base layer 151 and the first to fifth layers 152, 153, 154, 155, and 156 may include silicon (Si), and may have different concentrations of germanium (Ge). Meanwhile, in example embodiments, the number of layers transformed into the source/drain region 150 may be variously changed.

For example, the base layer 151 is formed of only silicon (Si), or may further include germanium (Ge). When the base layer 151 includes germanium (Ge), the concentration of germanium (Ge) may be lower than that in each of the first to fifth layers 152, 153, 154, 155, and 156 and may be higher than that in the active fin 105. For example, the concentration of germanium (Ge) in the base layer 151 may be equal to or less than 20 at.%. In the present specification, the concentration of germanium (Ge) refers to an atomic concentration (atomic percentage). The base layer 151 may further include a doping element such as boron (B) or gallium (Ga). In this case, the concentration of the doping element may be lower than the concentration of the doping element in each of the first to fifth layers 152, 153, 154, 155, and 156 and may be higher than the concentration of the doping element in the active fin 105.

In the first to fourth layers 152, 153, 154 and 155, the concentration of germanium (Ge) may increase upward. The first layer 152 includes germanium (Ge) having a first concentration, the second layer 153 includes germanium (Ge) having a second concentration higher than the first concentration, the third layer 154 includes germanium (Ge) having a third concentration higher than the second concentration, and the fourth layer 155 may include germanium (Ge) having a fourth concentration higher than the third concentration. For example, the first concentration is in the range of 20 at.% to 40 at.%, the second concentration is in the range of 35 at.% to 55 at.%, the third concentration is in the range of 45 at.% to 65 at.%, and the fourth concentration is in the range of 50 at.% to 70 at.%. Further, in the first to fourth layers 152, 153, 154, and 155, the concentration of a doping element such as boron (B) or gallium (Ga) may also be increased upward. The fifth layer 156 may include germanium (Ge) at a concentration lower than that in the fourth layer 155, or may not include germanium (Ge). For example, according to example embodiments, the fifth layer 156 may be formed of silicon (Si), and may further include impurities other than silicon (Si).

The base layer 151 and the first to fifth layers 152, 153, 154, 155, and 156 may have the same thickness or different thicknesses. For example, the base layer 151 and the fifth layer 156 may have a relatively thin thickness, and the third layer 154 may be formed to be relatively thick. The base layer 151 may have a thickness, for example, in the range of 3nm to 5 nm.

At least one region of base layer 151 is located under gate electrode 165, and at least one region of first layer 152 may be located under gate spacer layer 166. In plane, the base layer 151 may have a region protruding outward from the gate electrode 165. This will be described in more detail below with reference to fig. 3 to 4B.

The gate structure 160 may be disposed over the active fin 105 to extend in one direction (e.g., the Y direction) while crossing the active fin 105. A channel region of a transistor may be disposed in active fin 105, intersecting gate structure 160. The gate structure 160 may include a gate dielectric layer 162, a gate electrode 165, and a gate spacer 166.

The gate dielectric layer 162 may be disposed between the active fin 105 and the gate electrode 165, and may be disposed to cover a lower surface and both side surfaces of the gate electrode 165. Alternatively, in some example embodiments, the gate dielectric layer 162 may be formed only on the lower surface of the gate electrode 165. The gate dielectric layer 162 may include an oxide, nitride, or high-k material. A high-k material may refer to a material having a higher dielectric constant than silicon oxide (SiO)₂) A dielectric material of the dielectric constant of the film. The high-k material may be provided as alumina (Al)₂O₃) Tantalum oxide (Ta)₂O₃) Titanium oxide (TiO)₂) Yttrium oxide (Y)₂O₃) Zirconium oxide (ZrO)₂) Zirconium silicon oxide (ZrSi)_xO_y) Hafnium oxide (HfO)₂) Hafnium silicon oxide (HfSi)_xO_y) Lanthanum oxide (La)₂O₃) Lanthanum aluminum oxide (LaAl)_xO_y) Lanthanum hafnium oxide (LaHf)_xO_y) Hafnium aluminum oxide (HfAl)_xO_y) And praseodymium oxide (Pr)₂O₃) One kind of (1).

The gate electrode 165 may include a conductive material, and may include, for example, a metal nitride (e.g., a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film), and/or a metal material (e.g., aluminum (Al), tungsten (W), molybdenum (Mo), etc.), or a semiconductor material (e.g., doped polysilicon). The gate electrode 165 may include a multi-layer structure such as two or more layers. According to example embodiments, a capping layer may be further disposed over the gate electrode 165, and the lower surface and the side surface of the capping layer may be surrounded by the gate electrode 165 and the gate spacer 166, respectively.

Gate spacers 166 may be disposed on both side surfaces of the gate electrode 165. Gate spacers 166 may allow source/drain regions 150 to be isolated from gate electrode 165. According to an example embodiment, the gate spacer layer 166 may have a multi-layer structure. The gate spacer 166 may be formed of at least one of oxide, nitride, and oxynitride, and particularly, a low-k film.

An interlayer insulating layer 190 may be disposed to cover the upper surfaces of the element isolation layer 110, the source/drain region 150, and the gate structure 160. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low-k material. The material of the interlayer insulating layer 190 may be different from that of the gate spacer 160.

Fig. 3 is a partially enlarged plan view illustrating a semiconductor device according to an example embodiment. In fig. 3, the "C" region of fig. 1 is enlarged and shown.

Fig. 4A and 4B are cross-sectional views illustrating a portion of a semiconductor device according to example embodiments. Fig. 4A and 4B show cross-sections of the semiconductor device of fig. 3 taken along lines a-a 'and B-B', respectively.

First, referring to fig. 3, the active fin 105, the source/drain region 150 disposed in the recess region RC of the active fin 105, and the gate structure 160 are illustrated. In detail, in fig. 3, the arrangement of the base layer 151 and the first to fifth layers 152, 153, 154, 155, and 156 forming the source/drain region 150 on a plane is shown in detail.

The recess region RC of the active fin 105 is formed to extend downward from the gate structure 160 between the gate structures 160, and an end of the recess region RC in the X direction may be located below the gate structure 160. The end of the recess region RC may have a shape recessed outward from the gate structure 160. In other words, the end of the recess region RC may have a shape in which the width increases from the lower portion of the gate structure 160 toward the side surface or sidewall of the gate structure 160.

The base layer 151 is disposed at the lowermost portion of the recess region RC, and may be disposed to contact the inner sidewalls and the bottom surface of the recess region RC. Accordingly, the inner end 151E1 of the base layer 151 may have a shape that is concave outward in a similar manner as the end of the depression region RC. In the present specification, in the description of the source/drain region 150, "end portion" is used as a term indicating a point on the inner sidewall of the recess region RC which is in contact with other vertical layers. In the description of the end portions, a portion closer to the center of the gate structure 160 or the gate electrode 165 in the X direction is referred to as "inner side", and a portion farther from the center is referred to as "outer side". The outer end 151E2 of the base layer 151 may have a shape protruding outward from the gate structure 160 or the gate electrode 165. According to an example embodiment, a portion of outer end 151E2 of base layer 151 may coincide with a crystal plane of active fin 105. However, even in this case, the surface grown in the X direction from the base layer 151 may not be formed of facets (facets) formed along the crystal plane, and the facets may have at least a relaxed form. For example, when the upper surface of the substrate 101 or the active fin 105 is the <100> direction, the base layer 151 may be formed of not only a cut surface such as a {111} cut surface in the <110> direction corresponding to the X direction.

The first layer 152 may be disposed on the base layer 151, and the inner end 152E1 of the first layer 152 may be substantially the same as the outer end 151E2 of the base layer 151. Accordingly, the inner end 152E1 of the first layer 152 may have a shape that protrudes outward from the gate structure 160 or the gate electrode 165. The outer end 152E2 of the first layer 152 may also have a shape protruding outward from the gate structure 160 or the gate electrode 165, and the surface in the X direction may not be formed by a tangent. The first layer 152 is formed on the base layer 151 having no cut surface, and thus may have no cut surface. Accordingly, the uniformity of the thickness in the recess region RC may be improved. At least a portion of base layer 151 and first layer 152 may be planarly disposed below gate spacer layer 166.

The second layer 153 may be disposed on the first layer 152, and may have an outer end of a shape protruding toward an outer region of the gate electrode 165. However, the position of the outer end is not limited thereto. The width of the second layer 153 in the Y direction may be similar to or greater than the width of the first layer 152. The third to fifth layers 154, 155, and 156 may be sequentially disposed on the second layer 153, and in example embodiments, the relative positional relationship of the second to fifth layers 153, 154, 155, and 156 may be variously changed.

Referring to fig. 4A and 4B, of inner end 151E1 of base layer 151, the outermost portion EC shown in fig. 4A closest to the center of gate electrode 165 in the X direction may be located below gate electrode 165. Further, at least a portion of the first layer 152 may be located below the gate spacer 166. On the inner sidewalls of the recess region RC, the inner end 151E1 of the base layer 151 and the inner end 152E1 of the first layer 152 may have a region extending perpendicular to the upper surface of the substrate 101. Alternatively, on the inner sidewall of the recess region RC, the inner side surface of the base layer 151 and the inner side surface of the first layer 152 may have a region extending perpendicular to the upper surface of the substrate 101.

The length L1 of the active fin 105 shown in fig. 4A at the center of the active fin 105 in the Y direction may be shorter than the length L2 of the active fin 105 shown in fig. 4B in the edge. A spacing distance D1 between the side surface of the gate electrode 165 and the outermost portion EC of the base layer 151 at the center of the active fin 105 between the source/drain regions 150 in the Y direction may be greater than a spacing distance D2 at the edges. Further, a length L3 between outer ends 151E2 of the two base layers 151 at both sides of the gate electrode 165 shown in fig. 3 and 4A at the center of the active fin 105 in the Y direction may be greater than a length L4 between the outer ends 151E2 shown in fig. 3 and 4B at the edges.

At least a portion of the second to fifth layers 153, 154, 155 and 156 may be positioned under the gate spacer 166, but is not limited thereto. The base layer 151 and each of the first and second layers 152 and 153 may have a uniform thickness in the recess region RC or may have different thicknesses according to regions. The third layer 154 may have a relatively thick thickness compared to the other layers. The fourth layer 155 and the fifth layer 156 may be disposed in a region adjacent to the upper surface of the source/drain region 150, and may have a relatively thin thickness compared to other layers.

The first layer 152 has no cut surface. Therefore, the upper layer including the second layer 153 formed over the first layer 152 may have improved thickness uniformity as compared with the case of being formed over the cut surface. When the first layer 152 has a cut surface, the second layer 153 may be formed relatively thick on the bottom surface of the recess region RC. However, according to example embodiments, the thickness on the sidewalls of the active fin 105 may not be significantly different from the thickness on the bottom surface of the recessed region RC for the second layer 153 and may be substantially uniform.

The first to third layers 152, 153, and 154 may be used to apply stress to a channel region of the transistor. Therefore, according to an example embodiment, the layer including the first layer 152 and the second layer 153 is formed to have a uniform thickness, and the inner side surface of the base layer 151 and the inner side surface of the first layer 152 have a region perpendicular to the upper surface of the substrate 101. Accordingly, stress is uniformly transferred to the channel region, and thus electrical characteristics of the semiconductor device, such as resistance of the channel region, Drain Induced Barrier Lowering (DIBL) characteristics, and the like, may be improved. Further, the volume of the third layer 154 can be relatively increased, for example, as compared with the case where the formation is formed over the cut surface. When the third layer 154 serves as a main layer for applying stress to the channel region, if the volume of the third layer 154 is increased, stress can be sufficiently applied to the channel region.

Fig. 5A to 6B are a plan view and a sectional view illustrating a semiconductor device according to example embodiments. In fig. 5A to 6B, regions corresponding to those in fig. 3 and 4A are shown.

Referring to fig. 5A and 5B, in the source/drain region 150a of the semiconductor device 100a, the outermost portion EC of the base layer 151 may be located below or outside the interface between the gate electrode 165 and the gate dielectric layer 162. For example, the outermost portion EC of the base layer 151 may be located under the gate dielectric layer 162. At least a portion of the first layer 152 may be located under the gate spacer 166. At least a portion of the second to fifth layers 153, 154, 155 and 156 may be positioned under the gate spacer 166, but is not limited thereto. In an example embodiment, the third to fifth layers 154, 155 and 156 may not be positioned under the gate spacer 166.

Referring to fig. 6A and 6B, in the source/drain region 150B of the semiconductor device 100B, the first layer 152 may include a region located outside of a lower portion of the gate spacer 166 on the sidewall of the active fin 105. In other words, in plan, the outer end 152E2 of the first layer 152 may be located outside compared to the gate spacer 166. Therefore, the second to fifth layers 153, 154, 155, and 156 may not be located under the gate spacer layer 166 on the sidewalls of the active fin 105.

In a manner similar to that described with reference to fig. 5A through 6B, in example embodiments, the positions of the inner end 151E1 of the base layer 151, the positions of the inner end 152E1 and the outer end 152E2 of the first layer 152, and the like may be variously changed.

Fig. 7A and 7B are a plan view and a sectional view illustrating a semiconductor device according to example embodiments. In fig. 7A and 7B, regions corresponding to those in fig. 3 and 4A are shown.

Referring to fig. 7A and 7B, in a different manner from the example embodiment of fig. 1 through 4B, the source/drain region 150c of the semiconductor device 100c may not include the base layer 151. The source/drain region 150c may be formed of the first to fifth layers 152, 153, 154, 155, and 156. In addition, the end of the recess region RCa of the active fin 105 may have a shape protruding outward from the gate structure 160 on a plane. In other words, the end of the recess region RCa may have a shape in which the width decreases toward the sidewall of the gate structure 160. As described above, when the end of the recess region RCa has a shape protruding outward from the gate structure 160, the electrical characteristics of the semiconductor device 100c can be ensured even if the source/drain region 150c does not include the base layer 151.

The first layer 152 may be disposed in the recess region RCa to contact the active fin 105. At least a portion of the first layer 152 may be located under the gate spacer 166. However, the position of the first layer 152 is not limited thereto. For example, in an example embodiment, the first layer 152 may be positioned under the gate electrode 165. The inner end 152E1 and the outer end 152E2 of the first layer 152 may have a shape protruding outward from the gate structure 160 or the gate electrode 165. The end of the second layer 153 may have an outwardly convex shape.

Fig. 8 is a plan view illustrating a semiconductor device according to an example embodiment. In fig. 8, regions corresponding to the regions in fig. 3 are shown.

Referring to fig. 8, in a different manner from the example embodiment of fig. 1 through 4B, the source/drain region 150d of the semiconductor device 100d may not include the base layer 151. The source/drain region 150d may be formed of first to fifth layers 152, 153, 154, 155, and 156. Further, an end of the recess region RCb of the active fin 105 may have a shape substantially parallel to a sidewall of the gate structure 160 in a plane. As described above, when the end of the recess region RCb has a shape extending flat in the Y direction of the gate structure 160, the electrical characteristics of the semiconductor device 100d can be ensured even if the source/drain region 150d does not include the base layer 151.

The first layer 152 may be disposed in the recess region RCb to contact the active fin 105. At least a portion of the first layer 152 may be located under the gate spacer 166. However, the position of the first layer 152 is not limited thereto. For example, in an example embodiment, the first layer 152 may be positioned under the gate electrode 165. The inner end 152E1 of the first layer 152 may have a line shape that is substantially parallel to the sidewalls of the gate structure 160. Outer end 152E2 of first layer 152 may have a shape that protrudes outward from gate structure 160 or gate electrode 165. However, according to an example embodiment, the outer end 152E2 of the first layer 152 may have a line shape that is substantially parallel to the sidewalls of the gate structure 160.

Fig. 9A and 9B are a plan view and a sectional view illustrating a semiconductor device according to example embodiments. Fig. 9B shows a cross-section of the semiconductor device of fig. 9A taken along lines IId1-IId1 'and IId2-IId 2'.

Referring to fig. 9A and 9B, the semiconductor device 100e may include a substrate 101 having a first region I and a second region II, first and second active fins 105A and 105B, an element isolation layer 110, first and second source/ drain regions 150A and 150B, a gate structure 160, and an interlayer insulating layer 190. In the semiconductor device 100e, the PMOS transistor may be disposed in the first region I, and the NMOS transistor may be disposed in the second region II.

The first and second active fins 105A and 105B may be disposed in the first and second regions I and II, respectively, and may include impurities having different conductive types. According to an example embodiment, the gate structure 160 may have different structures in the first and second regions I and II. For example, the material and work function of gate electrode 165 can be different.

The first and second source/ drain regions 150A and 150B may be disposed in the first and second regions I and II, respectively. The first source/drain region 150A and the second source/drain region 150B may be formed of semiconductor materials having different conductivity types. For example, the first source/drain region 150A may include silicon germanium (SiGe) doped with p-type impurities, and the second source/drain region 150B may include silicon (Si) doped with n-type impurities. The second source/drain region 150B may not include germanium (Ge). The description of the source/drain region 150 described with reference to fig. 2 to 4B may be similarly applied to the first source/drain region 150A. The second source/drain region 150B may be formed of a single layer, or may include a plurality of regions including doping elements having different concentrations.

As shown in fig. 9B, the first source/drain region 150A and the second source/drain region 150B may have different shapes in cross-section. For example, the first source/drain region 150A may have a pentagonal shape or a shape similar thereto, and the second source/drain region 150B may have a hexagonal shape or a shape similar thereto.

Fig. 10A and 10B are a plan view and a sectional view illustrating a semiconductor device according to example embodiments. Fig. 10B shows a cross section of the semiconductor device of fig. 10A taken along line IId-IId'.

Referring to fig. 10A and 10B, in a semiconductor device 100f, source/drain regions 150f may be connected or merged with each other on two active fins 105 to form a single source/drain region 150 f. However, the number of active fins 105 disposed under the single source/drain region 150f connected as described above is not limited to the number shown in the drawings, and may be variously changed in example embodiments.

For example, in the source/drain region 150f, the base layer 151 and the first and second layers 152 and 153 may be disposed on each active fin 105, and the third to fifth layers 154, 155, and 156 may have a connection form on two active fins 105. Accordingly, the planar arrangement of the base layer 151 and the first and second layers 152 and 153 may be the same as that according to the example embodiment of fig. 1 to 4B.

Fig. 11A to 20B are diagrams illustrating a process sequence of a method of manufacturing a semiconductor device according to an example embodiment. In fig. 11A to 20B, a method for manufacturing the semiconductor device described above with reference to fig. 1 to 2D will be described.

Referring to fig. 11A and 11B, the substrate 101 is patterned to form an active fin 105 and a device isolation layer 110.

First, a mask layer for patterning the substrate 101 is formed on the substrate 101, and the substrate 101 is anisotropically etched using the mask layer to form the trench TI. The trench TI may be formed in a region other than the active fin 105. The trench TI has a high aspect ratio and thus may have a width that narrows downward. Accordingly, the active fin 105 may have an upwardly narrowing shape.

Then, an operation of filling the trench TI with an insulating material and planarizing may be performed. Then, the insulating material filling the trench TI is partially removed, and thus the active fin 105 may protrude from the element isolation layer 110. The above operation may be performed using, for example, a wet etching process. Accordingly, the active fin 105 may protrude from an upper portion of the element isolation layer 110 by a desired (and/or alternatively, a predetermined) height, and the protruding height may be variously changed in example embodiments.

Referring to fig. 12A and 12B, a sacrificial gate structure 170 may be formed in the active fin 105 and the element isolation layer 110.

The sacrificial gate structure 170 may be a sacrificial layer formed in a region where the gate dielectric layer 162 and the gate electrode 165 as shown in fig. 1 are disposed through a subsequent operation. The sacrificial gate structure 170 may be patterned to have a shape of a line extending in the Y direction while crossing the active fin 105.

The sacrificial gate structure 170 may include first and second sacrificial layers 172 and 174 and a mask pattern layer 176 that are sequentially stacked. The mask pattern layer 176 may be a hard mask layer remaining after the first sacrificial layer 172 and the second sacrificial layer 174 are patterned. The first sacrificial layer 172 and the mask pattern layer 176 may be insulating layers, and the second sacrificial layer 174 may be a conductive layer, but example embodiments are not limited thereto. For example, the first sacrificial layer 172 may include silicon oxide, the second sacrificial layer 174 may include polysilicon, and the mask pattern layer 176 may include silicon nitride. According to example embodiments, the number of layers and the material of the layers forming the sacrificial gate structure 170 may be variously changed.

Referring to fig. 13A and 13B, a gate spacer 166 may be formed on a side surface of the sacrificial gate structure 170.

Spacer-forming material is deposited to a uniform thickness along the upper and/or side surfaces of the active fin 105, the element isolation layer 110, and the sacrificial gate structure 170, and then the spacer-forming material may be anisotropically etched to form the gate spacer layer 166.

The gate spacer 166 may be formed of an insulating material. For example, the gate spacer 166 may be formed of a low dielectric constant material, and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In example embodiments, the gate spacer layer 166 may have a structure in which a plurality of films are stacked. Spacers may also be formed on the side surfaces of active fin 105 during the formation of gate spacers 166.

Referring to fig. 14A and 14B, the active fin 105 is recessed between the sacrificial gate structures 170 to form a recessed region RC.

The already exposed active fins 105 are recessed from the upper surface of the active fins 105 to a desired (and/or alternatively, predetermined) depth between the sacrificial gate structures 170 to form recessed regions RC. For example, the recess process may be performed by sequentially applying a dry etching process and a wet etching process. Thus, active fins 105 may have a lower level between sacrificial gate structures 170 compared to the level of active fins 105 under sacrificial gate structures 170.

The recessed region RC may extend toward the lower portions of the gate spacer 166 and the sacrificial gate structure 170. Accordingly, a recessed region RC may be formed over the extension region in the active fin 105 compared to the space between the gate spacers 166. In the recess region RC, the end in the X direction may be located below the gate spacer 166 and the sacrificial gate structure 170 in plane, and may have a shape recessed outward from the sacrificial gate structure 170. According to example embodiments, both ends of the upper surface of the recess region RC are located under the gate spacer 166 or the sacrificial gate structure 170, and thus may include an undercut region.

Alternatively, after the provision of the recess region RC, an operation of curing the recess surface of the active fin 105 may be performed using a separate operation. Further, the operation of implanting impurities into the active fin 105 may be performed before or after the recess operation. An impurity implantation operation may be performed using the sacrificial gate structure 170 and the gate spacer 166 as a mask.

Referring to fig. 15A and 15B, a base layer 151 of the source/drain region 150 may be disposed in the recess region RC.

For example, base layer 151 may be grown from active fin 105 using a Selective Epitaxial Growth (SEG) process. The base layer 151 may be, for example, a silicon (Si) layer. Alternatively, the base layer 151 may be, for example, a silicon germanium (SiGe) layer. In this case, the base layer 151 may include germanium (Ge) having a concentration lower than that of germanium (Ge) in the first layer 152 to be formed on the base layer 151. Base layer 151 may further include a doping element such as boron (B), and the concentration of the doping element in base layer 151 may be higher than the concentration of the doping element in active fin 105. The doping element may be doped in situ during the growth of the base layer 151 or may be implanted separately after growth.

The base layer 151 may be formed on the entire surface of the recess region RC, and the outermost portion EC may be located under the sacrificial gate structure 170. The distance between the sacrificial gate structures 170, the width of the active fins 105, etc., the shape on the plane of the inner end 151E1 where the base layer 151 contacts the active fins 105 on the inner sidewall of the recess region RC may be variously changed according to the etching conditions. In this case, however, the inner end 151E1 may have a shape that is generally concave outward from the sacrificial gate structure 170. The base layer 151 may have an outer end 151E2 located on an inner sidewall of the recess region RC as shown by a dotted line in fig. 15A, and the outer end 151E2 may have a convex curved shape without a cut surface.

Referring to fig. 16A and 16B, a first layer 152 may be formed on the base layer 151 of the source/drain region 150.

The first layer 152 may be formed using, for example, an SEG process. The first layer 152 may be, for example, a silicon germanium (SiGe) layer. For example, when the base layer 151 is a silicon germanium (SiGe) layer, the first layer 152 may include germanium (Ge) having a higher concentration than that of germanium (Ge) in the base layer 151. The first layer 152 may also include a doping element such as boron (B).

The first layer 152 may be formed on a surface of the base layer 151 in the recess region RC, and an outermost portion in planar contact with the base layer 151 may be located under the gate spacer 166. The inner end 152E1 of the first layer 152 may have a shape that generally protrudes outward from the sacrificial gate structure 170. The first layer 152 is formed on the base layer 151 having no tangent plane, and thus even the outer end 152E2 not in contact with the base layer 151 may have a convex shape without a tangent plane.

Referring to fig. 17A and 17B, second to fifth layers 153, 154, 155, and 156 are formed on the first layer 152, and thus source/drain regions 150 may be provided.

The second to fifth layers 153, 154, 155, and 156 may be formed using, for example, an SEG process. The second to fourth layers 153, 154 and 155 may be, for example, silicon germanium (SiGe) layers, and the fifth layer 156 may be a silicon (Si) layer. In the second to fourth layers 153, 154 and 155, the concentration of germanium (Ge) may sequentially increase. The second to fifth layers 153, 154, 155, and 156 may further include a doping element such as boron (B). In the second to fourth layers 153, 154 and 155, the concentration of the doping element may be sequentially increased.

The second layer 153 may be formed on the surface of the first layer 152, and the third layer 154 may be formed relatively thick so as to mainly fill the recess region RC. The fourth layer 155 and the fifth layer 156 may be formed relatively thin on the surface of the recess region RC.

The source/drain region 150 may have a width in the Y direction in a plane between the sacrificial gate structures 170 greater than a width under the sacrificial gate structures 170, and may have an area of increased width.

Referring to fig. 18A and 18B, an interlayer insulating layer 190 is formed over the sacrificial gate structure 170, the gate spacer 166, the element isolation layer 110, and the source/drain region 150, and the first sacrificial layer 172 and the second sacrificial layer 174 may be removed therefrom.

After depositing an insulating material to cover the sacrificial gate structure 170, the gate spacer 166, the device isolation layer 110, and the source/drain region 150, the upper surface of the second sacrificial layer 174 is exposed through a planarization process, and thus an interlayer insulating layer 190 may be provided. Accordingly, the mask pattern layer 176 of the sacrificial gate structure 170 may be removed in this operation. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low-k material.

Then, the first sacrificial layer 172 and the second sacrificial layer 174 of the sacrificial gate structure 170 are selectively removed with respect to the element isolation layer 110 and the active fin 105 located thereunder, and thus an opening GR exposing the element isolation layer 110 and the active fin 105 may be provided. The removing operation of the first and second sacrificial layers 172 and 174 may be at least one of a dry etching process and a wet etching process.

Referring to fig. 19A and 19B, a gate dielectric layer 162 and a gate electrode 165 are formed in the opening GR, thereby finally forming a gate structure 160.

The gate dielectric layer 162 may be formed substantially conformally along the sidewalls and lower surface of the opening GR. The gate dielectric layer 162 may include an oxide, nitride, or high-k material. The gate electrode 165 may be formed to fill the space within the gate dielectric layer 162. Gate electrode 165 may comprise a metal or semiconductor material.

After the gate dielectric layer 162 and the gate electrode 165 are formed, a material remaining on the interlayer insulating layer 190 may be removed therefrom using a planarization process such as a Chemical Mechanical Polishing (CMP) process.

Referring to fig. 20A and 20B, the interlayer insulating layer 190 is patterned to form a contact hole, and a conductive material may be embedded in the contact hole to form the contact plug 180.

First, an upper insulating layer 195 may be further formed on the interlayer insulating layer 190 and the gate structure 160. Then, a separate mask layer such as a photoresist pattern may be formed, and the interlayer insulating layer 190 and the upper insulating layer 195 may be removed from both sides of the gate structure 160, and thus a contact hole may be provided. The lower surface of the contact hole may allow at least a portion of the source/drain region 150 to be recessed.

Then, a conductive material is deposited in the contact hole, and thus a contact plug 180 electrically connected to the source/drain region 150 may be provided. Impurities may be implanted into the lower portion of the contact hole to reduce contact resistance prior to depositing the conductive material. Accordingly, the impurity concentration in a region adjacent to the lower end of the contact plug 180 may be increased as compared to the impurity concentration after the source/drain region 150 is formed. In example embodiments, the shape and arrangement of the contact plugs 180 may be variously changed.

Fig. 21A to 23B are diagrams illustrating a process sequence of a method of manufacturing a semiconductor device according to an example embodiment. In fig. 21A to 23B, a method for manufacturing the semiconductor device described above with reference to fig. 7A and 7B will be described.

Referring to fig. 21A and 21B, the active fin 105 is recessed between the sacrificial gate structures 170 to form a recessed region RCa.

First, the operations described above with reference to fig. 11A to 13B are performed in the same manner, and thus the active fin 105, the sacrificial gate structure 170, and the gate spacer 166 may be provided.

The exposed active fins 105 are then recessed between the sacrificial gate structures 170 to a desired (and/or alternatively, a predetermined) depth from the upper surface of the active fins 105 to form recessed regions RCa. For example, the recess process may be performed using a dry etching process and/or a wet etching process. A recessed region RCa may extend in the active fin 105 towards the lower portion of the gate spacer 166 and the sacrificial gate structure 170. In the recess region RCa, the end in the X direction may be located below the gate spacer layer 166 in a plane and may have a shape protruding outward from the sacrificial gate structure 170. However, in the recess region RCa, according to an example embodiment, the position of the end in the X direction on the plane may be changed, and the position may be located under the sacrificial gate structure 170.

Referring to fig. 22A and 22B, the first layer 152 of the source/drain region 150 may be disposed in the recess region RCa.

For example, the first layer 152 may be grown from the active fin 105 using an SEG process. The first layer 152 may be, for example, a silicon germanium (SiGe) layer. The first layer 152 may also include a doping element such as boron (B).

The first layer 152 may be formed on the entire surface of the recess region RCa, and the outermost portion EC may be located under the gate spacer 166. The inner end 152E1 of the first layer 152 in contact with the active fin 105 may have a shape that generally projects outwardly from the sacrificial gate structure 170 in plan view according to the shape of the recessed region RCa. The first layer 152 may have an outer end 152E2 (shown by an alternate long and short dash line in fig. 22A) located on an inner sidewall of the recessed region RCa, and the outer end 152E2 may have a convexly curved shape without a cut surface.

Referring to fig. 23A and 23B, second to fifth layers 153, 154, 155, and 156 are formed on the first layer 152, and thus source/drain regions 150c may be provided.

The second to fifth layers 153, 154, 155, and 156 may be provided using a process similar to that described above with reference to fig. 17A and 17B. Accordingly, the source/drain regions 150c including the first to fifth layers 152, 153, 154, 155, and 156 may be provided.

Fig. 24 is a circuit diagram of an SRAM cell including a semiconductor device according to an example embodiment.

Referring to fig. 24, in the SRAM cell, a single SRAM cell may be formed of first and second driving transistors TN1 and TN2, first and second load transistors TP1 and TP2, and first and second access transistors TN3 and TN 4. In this case, the sources of the first and second driving transistors TN1 and TN2 may be connected to the ground voltage line Vss, and the sources of the first and second load transistors TP1 and TP2 may be connected to the power voltage line Vdd.

The first driving transistor TN1 formed of an NMOS transistor and the first load transistor TP1 formed of a PMOS transistor may form a first inverter, and the second driving transistor TN2 formed of an NMOS transistor and the second load transistor TP2 formed of a PMOS transistor may form a second inverter. According to various example embodiments, at least a portion of the first and second load transistors TP1 and TP2 may include a semiconductor device as described above with reference to fig. 1-10B.

Output terminals of the first and second inverters may be connected to sources of the first and second access transistors TN3 and TN 4. Further, the first inverter and the second inverter may be connected to each other while the input terminal and the output terminal cross to form a single latch circuit. In addition, the drains of the first access transistor TN3 and the second access transistor TN4 may be connected to the first bit line BL and the second bit line/BL.

Fig. 25 is a block diagram illustrating an electronic apparatus including a semiconductor device according to an example embodiment.

Referring to fig. 25, an electronic device 1000 according to an example embodiment may include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.

The communication unit 1010 may include a wired/wireless communication module, such as a wireless internet module, a local communication module, a Global Positioning System (GPS) module, or a mobile communication module. The wired/wireless communication module included in the communication unit 1010 may be connected to an external communication network based on various communication standards to transmit and receive data.

The input unit 1020 may include a mechanical switch, a touch screen, a voice recognition module, etc., as a module provided to a user to control the operation of the electronic apparatus 1000. In addition, the input unit 1020 may further include a mouse or a finger mouse device operated based on a trackball or a laser pointer, and may further include various sensor modules enabling a user to input data.

The output unit 1030 may output information processed by the electronic device 1000 in an audio format or a video format, and the memory 1040 may store a program or data for processing or controlling the processor 1050. The output unit 1030 may include at least one of a speaker, an antenna, a connection structure (e.g., a terminal, a microUSB, etc.), and the like, for outputting information to the electronic device. The processor 1050 can send instructions to the memory 1040 to store data to the memory 1040 or retrieve data from the memory 1040, depending on the desired operation.

The memory 1040 may be embedded in the electronic device 1000 or may communicate with the processor 1050 through an additional interface. When the memory 1040 communicates with the processor 1050 through an additional interface, the processor 1050 may store data in the memory 1040 or retrieve data from the memory 1040 through various interface standards such as Secure Digital (SD), Secure Digital High Capacity (SDHC), secure digital extended capacity (SDXC), micro SD, Universal Serial Bus (USB), and the like.

The processor 1050 controls the operation of each component included in the electronic device 1000. The processor 1050 may perform control and processing associated with voice calls, video calls, data communications, etc., or may perform control and processing for multimedia replication and management. The processor 1050 may also process an input inputted by a user through the input unit 1020 and output the result thereof through the output unit 1030. Further, as described above, the processor 1050 can store data required to control the operation of the electronic device 1000 in the memory 1040 or retrieve the data from the memory 1040. At least one of the processor 1050 and the memory 1040 may include a semiconductor device as described above with reference to fig. 1-10B, according to various example embodiments.

Fig. 26 is a schematic diagram of a system including a semiconductor device according to an example embodiment.

Referring to fig. 26, the system 2000 may include a controller 2100, an input/output (I/O) device 2200, a memory 2300, and an interface 2400. The system 2000 may be a mobile system, or a system that transmits or receives information. The mobile system may be a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a wireless telephone, a mobile telephone, a digital music player, a memory card, etc.

The controller 2100 may be used to execute programs and control the system 2000. The controller 2100 may be, for example, a microprocessor, digital signal processor, microcontroller, or similar device.

The I/O device 2200 may be used to input or output data to the system 2000. The system 2000 may be connected to an external device (e.g., a personal computer or a network) using the I/O device 2200 to communicate data with the external device. The I/O device 2200 may be, for example, a key, a keyboard, or a display.

The memory 2300 may store code and/or data for the operation of the controller 2100 and/or may store data processed by the controller 2100.

The interface 2400 may be a data transmission path between the system 2000 and other external devices. The controller 2100, the I/O device 2200, the memory 2300, and the interface 2400 may communicate with each other using a bus 2500.

At least one of the controller 2100 and the memory 2300 may include a semiconductor device as described above with reference to fig. 1 through 10B according to various example embodiments.

As described above, according to example embodiments of the inventive concepts, the structure and shape of the source/drain regions are controlled, and thus a semiconductor device having improved electrical characteristics may be provided.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the disclosure as defined by the appended claims.