阅读说明：本技术 功率半导体器件 (Power semiconductor device ) 是由 埃迪·黄 尼古拉斯·A·M·科佩尔 马特加兹·罗兹曼 斯蒂芬·D·伍德 章剑峰 于 2019-07-23 设计创作，主要内容包括：本发明提供一种功率半导体器件,包括：具有单极传导结构和双极传导结构的半导体衬底、第一端子和第二端子。单极传导结构包括第一传导类型的第一区、第二区和第三区,其中,第二区的掺杂浓度低于第一区和第三区的掺杂浓度。双极传导结构包括形成在与第一传导类型相反的第二传导类型的第四区和第二区之间的P-N结、第一端子和第二端子。单极传导结构可操作以提供第一传导路径。双极传导结构可操作以提供第二传导路径。第一传导路径在功率半导体器件的导通状态期间,以第一频率接通和断开,并且第二传导路径在第一传导路径的断开阶段期间,以高传导率模式操作,和在第一传导路径的导通阶段期间,以低传导率模式操作。(The invention provides a power semiconductor device, comprising: a semiconductor substrate having a unipolar conductive structure and a bipolar conductive structure, a first terminal, and a second terminal. The unipolar conductive structure includes a first region, a second region, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than a doping concentration of the first region and the third region. The bipolar conductive structure includes a P-N junction, a first terminal, and a second terminal formed between a fourth region and a second region of a second conductivity type opposite the first conductivity type. The unipolar conductive structure is operable to provide a first conductive path. The bipolar conductive structure is operable to provide a second conductive path. The first conduction path is switched on and off at a first frequency during an on-state of the power semiconductor device, and the second conduction path operates in a high conductivity mode during an off-phase of the first conduction path and in a low conductivity mode during an on-phase of the first conduction path.)

1. A power semiconductor device comprising:

a semiconductor substrate, comprising:

a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and

a bipolar conductive structure including a P-N junction formed between a fourth region of a second conductivity type opposite to the first conductivity type and the second region;

a first terminal; and

a second terminal;

wherein the unipolar conductive structure is operable to provide a first conductive path between the first terminal and the second terminal using the first region, the second region, and the third region;

wherein the bipolar conductive structure is operable to provide a second conductive path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region, and the third region;

wherein the first conductive path is configured to be switched on and off at a first frequency with application of a control signal during an on-state of the power semiconductor device, and the second conductive path is configured to operate in a high conductivity mode during an off-phase of the first conductive path and in a low conductivity mode during an on-phase of the first conductive path.

2. The power semiconductor device of claim 1, wherein second region is configured to receive conductivity modulation due to carrier injection from the fourth region into the second region when the second conductive path operates in a high conductivity mode.

3. The power semiconductor device according to claim 1 or 2, wherein the first conductive path is parallel to the second conductive path.

4. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is operable to have an on state during which current flows between the first and second terminals using at least one of the first and second conductive paths, and an off state during which current does not flow between the first and second terminals.

5. The power semiconductor device according to any one of the preceding claims,

the power semiconductor device is a synchronous rectifier,

the power semiconductor device is capable of operating in an on-state when a voltage of a first polarity is applied between the first and second terminals, an

The power semiconductor device is capable of operating in an off state when a voltage of a second polarity, opposite to the first polarity, is applied between the first and second terminals.

6. A power semiconductor device according to any preceding claim, wherein the duration of the on-phase of the first conduction path is configured to be longer than the duration of the off-phase of the first conduction path during an on-state of the power semiconductor device.

7. A power semiconductor device according to claim 2 or any one of claims 3 to 6 when dependent on claim 2, wherein the duration of the on-phase of the first conduction path in at least one cycle of the control signal is shorter than the duration of disappearance of a portion of the injected carriers by recombination with majority carriers of the second region.

8. A power semiconductor device according to any preceding claim, wherein, in use, the first and second terminals are configurable to connect to an AC voltage of a second frequency, wherein the first frequency is higher than the second frequency, so as to rectify the AC voltage.

9. The power semiconductor device of claim 6 wherein the first frequency is at least two times higher than the second frequency.

10. A power semiconductor device according to any preceding claim, wherein the unipolar conductive structure comprises a Metal Oxide Semiconductor (MOS) gate structure, and wherein the MOS gate structure comprises a channel region of the second conductivity type disposed between the first and second regions, and a gate electrode for generating an electric field in the channel region to invert the conductivity type of the channel region to form a conductive channel between the first and second regions.

11. The power semiconductor device of claim 10 wherein a portion of the fourth region proximate the P-N junction has a higher doping concentration than the channel region.

12. A power semiconductor device according to claim 10 or 11, wherein the gate electrode is configured to receive the control signal to switch the conduction channel on and off to switch the first conduction path on and off.

13. The power semiconductor device of claim 10 or 11, further comprising a switch connectable between the first terminal and the first region, and wherein the switch is configured to receive the control signal to switch the first conduction path on and off.

14. A power semiconductor device according to any one of claims 1 to 9, wherein the first region is in direct contact with the second region, and the power semiconductor device further comprises a switch connectable between the first terminal and the first region, and the switch is configured to receive a control signal to switch on and off the first conduction path.

15. A power semiconductor device according to claim 13 or 14, wherein the switch is a low voltage switch.

16. A power semiconductor device according to any one of claims 13 to 15, wherein the switch is formed on a further semiconductor substrate separate from the semiconductor substrate.

17. The power semiconductor device of any preceding claim, wherein: the fourth region includes a plurality of fourth sub-regions spaced apart from one another, wherein at least some of the fourth sub-regions are operatively connected to the first terminal and form P-N junctions with the second region.

18. The power semiconductor device of claim 17 when dependent on claim 5, wherein: the fourth sub-regions are spaced apart from each other by a distance configured such that, upon application of a voltage of a second polarity to the first and second terminals, depletion regions within the second region corresponding to P-N junctions of adjacent fourth sub-regions collectively pinch off the first conduction path.

19. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from each other and the at least one first sub-region is provided between adjacent ones of the fourth sub-regions.

20. The power semiconductor device of any of claims 17 to 19, further comprising a trench disposed within the second region, wherein at least one of the fourth sub-regions is disposed adjacent to at least one wall of the trench.

21. The power semiconductor device of claim 20 further comprising a metallization contact electrically connected to at least one of the fourth sub-regions, wherein the metallization contact is operatively connected to the first terminal and at least a portion of the metallization contact is disposed within the trench.

22. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from each other, and the at least one first sub-region is provided within one of the fourth sub-regions and has a boundary substantially aligned with a boundary of one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.

23. A method of operating a power semiconductor device, the power semiconductor device comprising:

a semiconductor substrate comprising:

a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and

a bipolar conductive structure including a P-N junction formed between a fourth region of a second conductivity type opposite to the first conductivity type and the second region;

a first terminal; and

a second terminal;

the method comprises the following steps:

providing a first conductive path between the first terminal and the second terminal using the first region, the second region, and the third region;

applying a control signal to switch on and off the first conduction path at a first frequency during an on-state of the power semiconductor device; and

providing a second conductive path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region, and the third region; wherein the content of the first and second substances,

the second conduction path operates in a high conductivity mode during an off-phase of the first conduction path, wherein the second conduction path operates in a low conductivity mode during an on-phase of the first conduction path during an on-state of the power semiconductor device.

Technical Field

The present invention relates to a power semiconductor device. More particularly, but not exclusively, the invention relates to synchronous rectifiers for power electronics applications.

Background

Power semiconductor devices are semiconductor devices used for power electronics applications. Such devices are also referred to as power devices. Typically, power devices have a voltage rating in excess of 20V (i.e., the potential difference that the device must withstand in the OFF state between its main terminals) and conduct in excess of 100mA during its ON state. More commonly, the rating of the power device is higher than 60V and higher than 1A. These values make power devices very different from low voltage devices, which typically operate at voltages below 5V and conduct currents typically below 1mA, more typically in the μ a or below μ a range. Another difference between power devices and other types of devices, such as low voltage or Radio Frequency (RF) devices, is that power devices operate primarily on large signals and operate like switches. Exceptions are found in high voltage or power amplifiers, which comprise dedicated power transistors primarily for linear operation. It is not uncommon for a power semiconductor device to carry a current on the order of about 10A to 3000A in its on-state and to block a voltage on the order of about 100V to 10000V in its off-state. Commonly used power semiconductor devices include power diodes, thyristors, Bipolar Junction Transistors (BJTs), power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and Insulated Gate Bipolar Transistors (IGBTs).

Power semiconductor devices are commonly used as switches or rectifiers in power electronics applications. A rectifier is a device that converts Alternating Current (AC), which periodically reverses direction, into Direct Current (DC), which flows in only one direction. To accomplish this, when a voltage of a particular polarity is applied across the rectifier, the rectifier generally operates in an on state, allowing current to flow through the rectifier in a direction corresponding to the polarity of the voltage, and when a voltage of an opposite polarity (i.e., a reverse bias voltage) is applied across the rectifier, the rectifier operates in an off state, preventing current from flowing through the rectifier. The rated voltage of the rectifier must be higher than the magnitude of the reverse bias voltage so that the rectifier will not fail at the reverse bias voltage.

P-N or schottky diodes are commonly used rectifiers. It is common to use MOSFETs as synchronous rectifiers in low voltage DC-DC converters instead of P-N or schottky diodes. Synchronous rectification means that the MOSFET is actively turned on to allow current to flow in one direction, but actively turned off to prevent current from flowing in the other direction. The P-N and schottky diodes have a knee voltage in their conduction I-V characteristics with a minimum voltage drop of about 0.7V for the P-N diode or about 0.5V for the schottky diode. In low voltage converters with output voltages less than 5V, the 0.5V to 0.7V voltage drop level of the P-N or schottky diode used as rectifier represents an unacceptable efficiency loss. The voltage drop may also be referred to as the "on-state voltage" of the rectifier. In contrast, when used as a synchronous rectifier, a MOSFET has a resistive on-state characteristic without knee voltage. If selected to have a low on-resistance (R) for a particular circuit condition_DS(on)) The on-state voltage of such a synchronous rectifier can be made as low as possible. For this reason, MOSFETs are commonly used as synchronous rectifiers in low voltage converters, which require high efficiency and low power losses.

For rectification in high voltage power electronics applications (e.g., AC power rectification), it is almost uncommon to use MOSFETs as synchronous rectifiers. This is because the on-resistance of the MOSFET increases rapidly with the rated voltage. For example, for a 250V supply rectification of 10A, to achieve a conduction state voltage well below the 0.7V conduction state voltage achievable with a P-N diode, a MOSFET rated at 600V-800V and having a conduction resistance significantly below 70m Ω is required. Such on-resistance levels can be achieved using so-called super junction structures or compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). However, SiC and GaN semiconductor devices are very expensive to manufacture. For this reason, the use of MOSFETs as synchronous rectifiers for power rectification or other high voltage power electronic applications remains limited to very specialized applications.

Therefore, there is a need for a cost-effective power semiconductor device that can be used as a rectifier in high voltage power electronic applications, and that also provides low on-state voltage and high efficiency.

It is an object of the invention to provide such a cost-effective power semiconductor device.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a power semiconductor device comprising: a semiconductor substrate, comprising: a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and a bipolar conductive structure including a P-N junction formed between a fourth region of a second conductivity type opposite to the first conductivity type and the second region; a first terminal and a second terminal. The unipolar conductive structure is operable to provide a first conductive path between the first terminal and the second terminal using at least the first region, the second region, and the third region. The bipolar conductive structure is operable to provide a second conductive path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region, and the third region. The first conductive path is configured to be switched on and off at a first frequency with application of a control signal during an on-state of the power semiconductor device, and the second conductive path is configured to operate in a high conductivity mode during an off-phase of the first conductive path and in a low conductivity mode during an on-phase of the first conductive path.

By providing a bipolar conducting structure and a unipolar conducting structure on the same semiconductor substrate, both sharing a common low-doped second region designed for achieving a high voltage rating, and by alternating conduction of a first conducting path provided by the unipolar conducting structure and a second conducting path provided by the bipolar conducting structure at a first frequency, conduction of the bipolar conducting structure during an off phase of the first conducting path allows an on-state voltage of the unipolar conducting structure to be reduced during an on phase of the first conducting path. Thus, advantageously, the device may achieve an average on-state voltage that is lower than each of the on-state voltage of the bipolar conducting structure and the original on-state voltage of the unipolar conducting structure. Therefore, the device can achieve high efficiency and low power consumption.

It is to be understood that the term "terminal" may be used interchangeably with "electrode".

It should be understood that a unipolar conductive structure refers to a semiconductor structure that uses only one type of charge carriers during electron conduction. For example, MOSFETs and schottky diodes are unipolar conductive structures. Since the charge carriers involved are majority carriers, the unipolar conduction structure may also be referred to as a majority carrier conduction structure.

The first conductive path may be a resistive conductive path.

A bipolar conduction structure refers to a semiconductor structure that uses two types of charge carriers (i.e., electrons and holes) during electron conduction. For example, Bipolar Junction Transistors (BJTs), thyristors, IGBTs, and P-N junction diodes are bipolar conducting structures. The bipolar conducting structure may also be referred to as a minority carrier conducting structure, since both majority and minority carriers are involved during conduction of the bipolar conducting structure.

The term "low conductivity mode" refers to the case where a forward bias voltage lower than the forward threshold voltage is applied across the P-N junction, and the term "high conductivity mode" refers to the case where the forward bias voltage is higher than the forward threshold voltage applied across the P-N junction. In general, the current level through the P-N junction during the low conductivity mode is much lower than the current level during the high conductivity mode. Thus, the P-N junction may also be considered to be "off during the low conductivity mode.

The second region may be configured to receive conductivity modulation due to carrier injection from the fourth region into the second region when the second conductive path operates in a high conductivity mode.

The first conductive path may be substantially parallel to the second conductive path.

This parallel arrangement allows the unipolar conductive structure to have the benefit of conductivity modulation due to the conduction of the bipolar conductive structure, without introducing the knee voltage of the bipolar conductive structure into the conduction characteristics of the overall on-state of the device.

The power semiconductor device is operable to have an on state during which current flows between the first and second terminals using at least one of the first and second conductive paths, and an off state during which current does not flow between the first and second terminals.

The power semiconductor device may be a synchronous rectifier. The power semiconductor device may be operable in an on state when a voltage of a first polarity is applied between the first and second terminals, and may be operable in an off state when a voltage of a second polarity, opposite to the first polarity, is applied between the first and second terminals.

The control signal may be synchronized with a polarity of a voltage applied between the first terminal and the second terminal.

The semiconductor substrate may be a monolithic silicon substrate. The first to fourth regions may be regions of the silicon substrate doped with different types and/or different impurity levels.

The third region may have a first surface and a second surface opposite the first surface. The second terminal may be electrically coupled to the second surface of the third region.

The second zone may be disposed on the first surface of the third zone.

The second region may have a first surface and a second surface opposite the first surface and facing the third region.

The first region may be disposed adjacent to the first surface of the second region.

The fourth zone may be disposed within the second zone. In an example, the fourth region may be disposed adjacent to the first surface of the second region. Alternatively, the fourth region may be provided around the wall of at least one trench located within the second region.

The duration of the on-phase of the first conduction path may be configured to be longer than the duration of the off-phase of the first conduction path during an on-state of the power semiconductor device.

The duration of the on-phase of the first conduction path during at least one period of the control signal may be shorter than the duration of disappearance of a part of the injected carriers by recombination with majority carriers of the second region.

The proportion of injected carriers may be a significant fraction of the injected carriers. Optionally, the fraction may have a value between 50% and 95%.

In use, the first and second terminals may be configured to be connected to an AC voltage of a second frequency in order to rectify the AC voltage, and the first frequency may be higher than the second frequency.

The first frequency may be at least two times higher than the second frequency. The first frequency may be between 10KHz and 1 MHz.

The unipolar conductive structure may include a Metal Oxide Semiconductor (MOS) gate structure. The MOS gate structure may include a channel region of the second conductivity type disposed between the first and second regions; and a gate electrode for generating an electric field in the channel region to invert a conductivity type of the channel region to form a conductive channel between the first region and the second region.

A portion of the fourth region proximate the P-N junction may have a higher doping concentration than the channel region.

The gate electrode may be configured to receive the control signal to switch the conduction channel on and off to switch the first conduction path on and off.

The power semiconductor device may further comprise a switch connectable between said first terminal and said first region. The switch may be configured to receive the control signal to turn on and off the first conduction path.

The first region may be in direct contact with the second region. The power semiconductor device may further include a switch connectable between the first terminal and the first region. The switch may be configured to receive a control signal to switch on and off the first conduction path.

The power semiconductor device may include a first electrode portion electrically connected to the fourth region, and a second electrode portion electrically connected to the first region. The term "electrode portion" is used interchangeably with the term "metallized contact". The first electrode portion may be spaced apart from the second electrode portion. The switch may be electrically connected between the first terminal and the second electrode portion. The first electrode portion may be electrically connected to the first terminal.

The switch may be a low voltage switch. It should be understood that the term "low voltage switch" means that the voltage rating of the switch (e.g., less than 20V) is lower than the voltage rating of the power semiconductor devices.

The switch may be formed on another semiconductor substrate separate from the semiconductor substrate. The semiconductor substrate and the further semiconductor substrate may be packaged in a single package.

The fourth region may include a plurality of fourth sub-regions spaced apart from each other. At least some of the fourth sub-regions may be operatively connected to the first terminal and form P-N junctions with the second region.

The fourth sub-regions may be spaced apart from each other by a distance configured such that, upon application of a voltage of a second polarity to said first and second terminals, depletion regions within the second region corresponding to P-N junctions of adjacent fourth sub-regions collectively pinch off the first conduction path.

The first region may include at least one first sub-region spaced apart from each other, and the at least one first sub-region may be disposed between adjacent sub-regions of the fourth sub-region. The at least one first sub-region may be spaced apart from adjacent sub-regions of the fourth sub-region.

The power semiconductor device may further include a trench disposed within the second region. At least one of the fourth sub-regions may be disposed adjacent to at least one wall of the trench.

The power semiconductor device may further comprise a metallization contact electrically connected to at least one of the fourth sub-regions. The metallization contact may be operatively connected to the first terminal, and at least a portion of the metallization contact may be disposed within the trench.

Alternatively, the first region may comprise at least one first sub-region spaced apart from each other, the at least one first sub-region may be disposed within one of the fourth sub-regions and have a boundary substantially aligned with a boundary of one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.

The doping concentration and the thickness of the second region may be configured such that the power semiconductor device is capable of supporting a voltage between the first terminal and the second terminal having, but not limited to, a magnitude of 600V to 800V during an off-state of the power semiconductor device.

According to a second aspect of the present invention, there is provided a method of operating a power semiconductor device comprising: a semiconductor substrate comprising: a unipolar conductive structure including a first region of a first conductivity type, a second region of the first conductivity type, and a third region of the first conductivity type, wherein a doping concentration of the second region is lower than doping concentrations of the first region and the third region; and a bipolar conductive structure including a P-N junction formed between a fourth region of a second conductivity type opposite to the first conductivity type and the second region; a first terminal and a second terminal; the method comprises the following steps: providing a first conductive path between the first terminal and the second terminal using the first region, the second region, and the third region; applying a control signal to switch on and off the first conduction path at a first frequency during an on-state of the power semiconductor device; and providing a second conductive path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region, and the third region; wherein during an off-phase of the first conductive path the second conductive path operates in a high conductivity mode and during an on-state of the power semiconductor device during an on-phase of the first conductive path the second conductive path operates in a low conductivity mode.

Any optional feature described above in relation to aspects of the invention may be applied to another of the aspects of the invention where appropriate.

It should be understood that the power semiconductor device of the present invention is suitable for use in various power electronic applications, and is not limited to use in power rectification as a synchronous rectifier.

Drawings

For a more complete understanding of the present invention, several embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which:

fig. 1 is a schematic diagram of a cross-section of a power semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram of input and output waveforms during the on-state of the power semiconductor device of fig. 1.

Fig. 3 is a schematic diagram of a cross-section of a power semiconductor device according to a second embodiment of the present invention.

Fig. 4 is a schematic diagram of a cross-section of a power semiconductor device according to a third embodiment of the present invention.

Fig. 5 is a schematic view of a partial cross-section of a power semiconductor device, which may be replaced by a partial cross-section of a third embodiment of the present invention.

Fig. 6 is a schematic diagram of a cross-section of a power semiconductor device according to a fourth embodiment of the present invention.

In the drawings, like parts are denoted by like reference numerals. Further, in each drawing, a component denoted by a reference numeral (format N-i) has the same characteristics as another portion denoted by the reference numeral N.

It is to be understood that the drawings are for illustrative purposes only and are not drawn to scale.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Fig. 1 schematically shows a cross-section of a power semiconductor device 100 according to a first embodiment of the invention. The device 100 comprises an N + silicon substrate 3. The electrode 20 is electrically coupled to the bottom surface of the substrate 3. Having a thickness t₂Has a doping concentration of about 10 (for example)¹³cm^-3To 10¹⁵cm^-3) Is provided on the top surface of the substrate 3. The N-drift region 2 may be an epitaxial layer. Thickness t₂May be on the order of tens of micrometers (μm), for example. It should be understood that the thickness t₂The particular value of (d) depends on the voltage rating of the device 100.

A P + well 4 is provided in the N-drift region 2 adjacent to the top surface of the N-drift region 2. N + region 1 is disposed in P + well 4 and is also adjacent to the top surface of N-drift region 2. The "top surface" and "bottom surface" used above may also be referred to as "first surface" and "second surface", respectively, which is opposite to the "first surface". The P + well 4 and the N + region 1 may be formed by a double diffusion process. The N-drift region 2 has a lower doping concentration than the substrate 3 and the N + region 1. Electrode 10 is electrically coupled to both N + region 1 and P + well 4.

The N + region 1, the N-drift region 2, the substrate 3 and the P + well 4 may also be referred to as the "first region", "second region", "third region" and "fourth region", respectively, of the device 100. These regions are formed by doping various impurities into silicon. Electrodes 10 and 20 may be referred to as a "first electrode" and a "second electrode," respectively, of device 100, or as a "first terminal" and a "second terminal," respectively, of device 100.

The device 100 further includes a MOS gate structure including an insulated gate 6, a channel region 5 along the top surface of the P + well 4 between the N + region 1 and the N-drift region 2, and a gate oxide layer 7 between the gate 6 and the channel region 5. The gate electrode 30 is electrically coupled to the gate electrode 6. When a positive voltage is applied between the gate electrode 30 and the first electrode 10 (i.e., the potential at the gate electrode 30 is higher than the potential at the first electrode 10), an electric field generated by the voltage passes through the oxide layer 7 and inverts the conductivity type of the channel region 5, thereby generating an N-type inversion layer (i.e., N-channel) at the interface between the P + well 4 and the oxide layer 7. The inversion layer provides a conduction channel through which current can flow between the N + region 1 and the N-drift region 2.

Accordingly, when a positive voltage is applied between the gate electrode 30 and the first electrode 10, a first conduction path P1 is provided between the first electrode 10 and the second electrode 20 via the N + region 1, the inversion channel region 5, the N-drift region 2, and the N + substrate 3.

Similar to a typical MOSFET, the first conduction path P1 uses only one type of charge carrier (i.e., electrons) for conduction. The electrons are the predominant carriers for N + region 1, back channel region 5, N-drift region 2, and N + substrate 3. Accordingly, the first conduction path P1 may also be referred to as a unipolar conduction path or a majority carrier conduction path. Thus, the N + region 1, the N-drift region 2, the N + substrate 3, the channel region 5 and the MOS gate structure together form a unipolar conductive structure.

Since the first conduction path P1 is resistive, the on-state characteristic of the unipolar conduction structure has no knee voltage. The first conduction path P1 works equally well by current flowing from the first electrode 10 to the second electrode 20, or from the second electrode 20 to the first electrode 10. On-resistance (R) of unipolar conduction structure_DS(on)) Including the resistance of the N + region 1, the resistance of the inversion channel region 5, the resistance of the N-drift region 2, and the resistance of the N + substrate 3, which are connected in series with each other.

A relatively thick and low doped N-drift region 2 is necessary for the unipolar conductive structure to block the high voltage applied between the first electrode 10 and the second electrode 20. Thus, such a low doped region has a high resistivity. The series resistance in N-drift region 2 increases with the voltage rating of device 100 and generally represents the largest contribution to the total on-resistance of first conduction path P1. At the same time, the presence of the low-doped N-drift region 2 is necessary for the device 100 to achieve a high voltage rating, and it is not feasible to embed (e.g. by a diffusion process) more impurities (e.g. phosphorus) into the drift region 2 to increase its doping concentration. Therefore, the low doped N-drift region 2 presents a challenge to reduce the voltage drop across the unipolar conduction structure during conduction of path P1.

As shown in fig. 1, a P-N junction 11 is formed along the interface between the P + well 4 and the N-drift region 2. Thus, there is also a second conduction path P2 between the first electrode 10 and the second electrode 20 via the P + well 4, the P-N junction 11, and the N-drift region 2. The first conductive path P1 and the second conductive path P2 are connected in parallel between the electrodes 10 and 20.

The P-N junction 11 may be forward biased by turning on the second conduction path by applying a positive voltage between the first electrode 10 and the second electrode 20 (i.e. the potential at the first electrode 10 is higher than the potential at the second electrode 20). Because of the diffusion of electrons and holes involved during conduction of the second conductive path P2, the second conductive path P2 may also be referred to as a bipolar conductive path or a minority carrier conductive path. Thus, the P + well 4, the P-N junction 11 and the N-drift region 2 together form a bipolar conductive structure. Due to the P-N junction 11, there is a knee voltage of about 0.7V in the conduction I-V characteristic of the bipolar conduction structure. The knee voltage is determined by the properties of the bipolar conductive structure and cannot be eliminated.

The device 100 may be used as a synchronous rectifier having an on state and an off state.

The off-state occurs when the device 100 is reverse biased (e.g., the potential at the first electrode 10 is lower than the potential at the second electrode 20). To achieve the open state, paths P1 and P2 must remain closed. Path P1 may be closed by applying a low voltage (including 0V) to gate electrode 30 such that the voltage difference between gate electrode 30 and first electrode 10 is below the threshold voltage for forming an N-channel within channel region 5 (which means that path P1 cannot be established in the off-state). When the potential at the first electrode 10 is lower than the potential at the second electrode 20, the P-N junction 11 of path P2 is naturally reverse biased, and thus path P2 is also unable to conduct current. Therefore, current cannot flow from the second electrode 20 to the first electrode 10, and the device operates in an off state.

When a positive voltage is applied between the first electrode 10 and the second electrode 20, an on state occurs. To achieve the on state, at least one of the paths P1 and P2 is commonly guided. Path P1 may be conducted by applying a relatively high voltage to gate electrode 30 such that the voltage difference between gate electrode 30 and first electrode 10 is above the threshold voltage for forming an N-channel. Further, when the potential at the first electrode 10 is higher than the potential at the second electrode 20, the P-N junction 11 of the path P2 is naturally forward biased. In this way, current may flow from the first electrode 10 to the second electrode 10 via one or both of paths P1 and P2.

The voltage applied to the gate electrode 30 is generally synchronized with the polarity of the voltage applied between the first electrode 10 and the second electrode 20. Accordingly, the on/off state of the device 100 may be changed according to a change in the polarity of the voltage applied between the first electrode 10 and the second electrode 20.

As described above, the voltage drop along path P1 may be large due to the high resistance of N-drift region 2, and path P2 suffers from a knee voltage of about 0.7V, which cannot be eliminated. In order to reduce the on-state voltage of the device 100 (i.e. the voltage drop between the second electrode 20 and the first electrode 10 during the on-state), the device 100 is controlled to dynamically increase the charge carrier concentration of the N-drift region 2, thereby reducing the resistance of the N-drift region 2 (without actually embedding or diffusing more impurities into the region 2) during the on-state of the device 100. This will be described in more detail below.

Fig. 2 shows a voltage V applied between the gate electrode 30 and the first electrode 10 during the on-state of the device 100_GSAnd an on-state voltage V generated between the second electrode 20 and the first electrode 10_ONThe waveform of (2). For illustrative purposes only, the duration of the on state is shown as t_ON。

As shown in fig. 2, during the whole period t of the on state_ONIn the meantime, instead of constantly biasing the gate 6 positive to cause the presence of the N channel, the rapid on and off (on-off) pulse V is turned on and off (turned on-off)_GSIs applied to gate electrode 30 to periodically turn on and off the N-channel in channel region 5, thereby periodically turning on and off first conduction path P1. V_GSMay be, for example, between 10kHz and 10 MHz. On/off frequency of N-channel and first conduction path P1 and V_GSAre substantially the same.

V_GSIs T, which comprises an off-phase T1 switching off the N-channel and an on-phase T2 switching on the N-channel.

During the off-phase T1, the first conductive path P1 is switched off, but the second conductive path P2 is still switched on because the potential of the first electrode 10 is higher than the potential of the second electrode. Thus, current will flow through the bipolar conductive structure along the second conductive path P2. Due to the presence of the P-N junction 11, the on-state characteristic has a knee voltage,the on-state voltage V during the off-phase T1_ONAbout 0.7V.

During the off-phase T1, minority carriers (i.e., holes in the device 100) are injected into the N-drift region 2 via conduction of the bipolar conductive structure, thereby enhancing the conductivity of the N-drift region 2. Due to the quasi-charge neutral confinement, the injected minority carriers will also lead to an increase of majority carriers (i.e. electrons) in the N-drift region 2 during the subsequent on-phase T2, as described below. In this way, the effective doping of the N-drift region 2 is temporarily increased to a level that is much higher than the actual doping concentration of the N-drift region 2, thereby reducing the resistance of the N-drift region 2. This effect is referred to as conductivity modulation of the N-drift region 2.

When the N-channel is turned on during the on-phase T2, both the first conductive path P1 and the second conductive path P2 conduct at the beginning of the on-phase T2. It will be appreciated that current will tend to flow through paths having lower resistance. Due to the conductivity modulation received by the N-drift region 2 during the off-phase T1, the instantaneous on-resistance of the first conduction path P1 has been greatly reduced from its normal level, since the largest contributor to this resistance (N-drift region 2) reduces its effective resistance due to the presence of injected minority carriers. Therefore, the current tends to flow through the first conduction path P1, and the instantaneous on-state voltage of the path P1 drops to a level much lower than the knee voltage of the path P2. As an example, V_ONIs shown as about 0.1V in fig. 2, but may vary depending on the configuration of the unipolar conductive structure and the current density flowing through path P1.

Because the instantaneous on-state voltage of path P1 is below the forward "threshold" voltage (about 0.7V) of the P-N junction 11 of path P2, conduction through path P2 will cease or enter a very low conductivity mode. It will be appreciated that if a forward bias voltage below the forward threshold voltage is applied between the P-N junctions, the P-N junctions are still able to conduct a small current (which may be on the order of or below a few mA) and are not strictly off. Thus, the term "low conductivity mode" refers to the case where the forward bias voltage is lower than the forward threshold voltage applied across the P-N junction 11, and the term "high conductivity mode" refers to the case where the forward bias voltage is higher than the forward threshold voltage applied across the P-N junction 11. In general, the current level through the P-N junction 11 during the low conductivity mode is much lower than the current level during the high conductivity mode. Thus, the P-N junction may also be considered to be turned off during the on-phase T2 and turned on during the off-phase T1.

As the on-phase T2 continues, the minority carriers injected into the N-drift region 2 start to disappear by recombination with the majority carriers within the N-drift region 2. Therefore, the effective resistance of N-drift region 2 increases during on-phase T2, which causes the on-state voltage of device 100 to gradually increase over time, as shown in fig. 2.

Typically, the minority carrier lifetime in the N-drift region 2 is such that the recombination process takes place within a few microseconds. In one example, the compounding process may take at least about 10 microseconds. It should be appreciated that the duration of the on-phase T2 is preferably shorter than the lifetime of the injected minority carriers. In another example, the duration of the on-phase T2 may be shorter than the duration of a period during which a portion of the injected carriers disappear by recombination. The portion may be a majority and may have a value of, for example, between 50% and 95%.

By switching the N-channel and the first conduction path P1 on and off at a suitable high frequency, the minority carriers injected into the N-drift region 2 during the off-phase T1 are mostly present for the entire on-phase T2, so that the on-state voltage of the path P1 remains low for the entire on-phase T2. As shown in fig. 2, the on-state voltage gradually increases as the injected carriers recombine during the on-phase T2, but before the on-state voltage significantly increases, the N-channel is closed again, so that the second conduction path P2 is turned on, thereby "replenishing" the injected carriers of the N-drift region 2. Furthermore, during the on-phase T2, the main conduction path (i.e., the first conduction path P1) is purely resistive, without any P-N junction, and therefore without knee voltage.

Fig. 2 shows that the on-phase T2 has a longer duration than the off-phase T1. The exact ratio of the off-phase T1 and the on-phase T2 can be optimized for maximum benefit. In general, the best performance can be obtained by making the off-phase T1 as short as possible, but long enough to establish a high level of conductivity modulation in the N-drift region 2, and by making the on-phase T2 as long as possible without raising the on-state voltage too much from its initial low value. In this manner, the average on-state voltage of device 100 is much lower than the knee voltage of the P-N junction (typically 0.7V). Thus, the device 100 may achieve performance comparable to that achieved by a super junction structure or a compound semiconductor, but may be fabricated in a more cost-effective manner than a super junction structure or a compound semiconductor.

It should be understood that the N-drift region 2 is preferably made of a semiconductor material having relatively high lifetime minority carriers. This allows the duration of the on-phase T2 to be extended relative to the duration of the off-phase T1. Thus, the average on-state voltage of device 100 may be further reduced to a lower level due to the very low on-state voltage provided by path P1 during the on-phase T2.

By using a low defect density silicon structure as the material of the N-drift region 2, a high lifetime of minority carriers within the N-drift region 2 can be achieved. In one example, a back-diffused uniform wafer is used as a starting material for fabricating the device 100, wherein the N-drift region 2 has been provided by the wafer and is not an epitaxial layer made by an epitaxial process on the substrate 3. The N-drift region 2 manufactured in this way has a low defect density, and therefore the minority carrier lifetime in the N-drift region 2 is relatively high. In another example, the N-drift region 2 is an epitaxial layer made by an epitaxial process, and an annealing process is performed on the epitaxial layer to reduce structural defects.

For example, the duration of the off-phase T1 may be from nanoseconds to microseconds. It has been found that there is a minimum duration of the turn-off phase T1 in order to allow the P-N junction 11 to conduct, thereby fully modulating the conductivity of the N-drift region 2. Furthermore, it has been found that extending the minimum duration may not necessarily further enhance the conductivity of the N-drift region 2. The minimum duration varies with the particular doping and thickness configuration of the device 100, the current density flowing through the device 100, the operating temperature, and other external conditions, and may generally varyTo be in the range of 0.5 to 2 microseconds. The duration of the on-phase T2 may preferably be about 5 to 15 microseconds. Generating low V_ONSignal V of_GSIs typically in the range of 80% to 95%. It should be understood that the particular numbers of time periods and duty cycles described above are merely exemplary, and that the actual operation of device 100 is in no way limited to these figures.

Fig. 2 shows the duration t of the on-state of the device 100_ONGreater than V_GSThree times the period T of (a). It should be understood that this is for illustration only, and that the duration t is_ONMay be equal to i x T, where i is a number equal to or greater than 1.

Conductivity modulation is also used for bipolar power devices (e.g. thyristors, IGBTs). However, device 100 provides an advantage over bipolar power devices in that device 100 is capable of achieving an on-state voltage that is lower than the knee voltage of the P-N junction. As described above, during the on-state of the device 100, the current flowing through the device 100 alternates between the first conductive path P1 and the second conductive path P2 at a high frequency, thereby generating an "average" on-state voltage that is lower than the 0.7V knee voltage of the P-N junction. In contrast, a bipolar power device always introduces at least one P-N junction into its current conduction path, and at least one P-N junction is connected in series with one or more other conductive elements. Therefore, the on-state voltage provided by the bipolar power device is generally equal to or higher than the 0.7V knee voltage, and it is not easy to reduce the on-state voltage below the knee voltage.

The device 100 may be used in applications where the duration of the on-state of the device 100 covers many periods of the "channel on/off" switching period T, such as 50/60Hz power supply rectification or other such low frequency applications. In a conventional mains AC-DC rectifier bridge, all current flows through two P-N diodes (acting as rectifiers) connected in series before reaching the appliance. The voltage drop in the two P-N diodes is typically at least 1.6V. If device 100 is used as a synchronous rectifier in place of each P-N diode in the power rectification, an average on-state voltage of about 0.3V can be achieved for each device 100, giving 0.6V in the two devices in series. Thus, the voltage drop is reduced by 1V in total, indicating an improvement of about 1% in the efficiency of the 110V power supply. With the widespread use of power rectification in many appliances, the potential savings in power consumption and environmental benefits are enormous if device 100 is used.

The device 100 may be used in many other power electronic applications. For example, totem-pole bridgeless Power Factor Correction (PFC) circuits typically use two low on-resistance high frequency switches, such as GaN High Electron Mobility Transistors (HEMTs) or SiC Field Effect Transistors (FETs), and two high voltage super junction MOSFETs as synchronous rectifiers. In this circuit, the super junction synchronous rectifier is switched on and off at power frequency 50/60Hz and can be replaced with device 100 to reduce cost. Since the bridgeless PFC circuit already uses a complex driving scheme from the control IC, the on-off switching of the first conduction path P1 as described above is easily implemented in the control scheme without additional cost.

In addition to power electronic applications requiring a rectifier operating at the mains frequency, or similar as outlined in the examples above, the device 100 may also be used for rectification at higher frequencies, for example in a normal PFC circuit where the switching frequency of the rectification is typically 70kHz, or in a high frequency Switched Mode Power Supply (SMPS) circuit if the on-state of the rectifier in such a circuit is long enough to have at least one complete cycle of the off-phase T1 and the on-phase T2. For example, the device 100 may be used as a high voltage synchronous rectifier in an SMPS circuit, with the P-N junction 11 serving as a freewheeling diode. In SMPS circuits, it may be beneficial to intentionally turn on the N-channel of the unipolar structure of device 100 at a time somewhat later than normal, adding a so-called "dead time" period during which the second conductive path P2 conducts, but the first conductive path P1 does not. In this way, due to the conductivity modulation received by the N-drift region 2 during the "dead time", the effective resistance of the N-drift region 2 decreases when the first conduction path P1 begins to conduct. However, when device 100 is used in an SMPS circuit, the minority carrier (i.e. holes in device 100) lifetime should preferably be controlled such that the majority of the minority carriers recombine at the end of the on-phase T2 of device 100 so as not to compromise the reverse recovery characteristics of device 100. The reverse recovery characteristic refers to the reverse recovery time of the rectifier, which is the duration of time that the rectifier is inherently required to stop current at the time of switching.

In addition to improving efficiency through lower on-state voltages, the use of device 100 as a rectifier in the above-described applications also provides the benefit of lower power consumption, allowing for the reduction or even elimination of bulky and expensive heat dissipating devices. Thus, the overall gain provided by the device 100 to the user and the environment is large.

The nominal voltage of the device 100 is the doping concentration and the thickness t of the N-drift region 2₂And its current rating is a function of the width of the N-channel provided in the channel region 5 and the size of the P-N junction 11. Thus, the doping concentration and the thickness t of the N-drift region 2 can be adjusted₂To provide the required nominal voltage. In addition, the channel width and size of the P-N junction 11 may be adjusted to allow the device 100 to conduct a desired amount of current in its on-state. Furthermore, to enhance the effect of conductivity modulation, the doping concentration of the P + well 4 near the P-N junction 11 may be increased, for example to 10¹⁶～10¹⁸cm^-3. At the same time, the doping concentration of the P + well 4 near the channel region 5 is preferably kept low (e.g., about 10)¹⁵～10¹⁶cm^-3) To avoid affecting the performance (e.g., threshold voltage) of the unipolar conductive structure. Such a two-level doping concentration of the P + well 4 may be achieved by controlled ion implantation or other suitable techniques.

The device 100 may comprise a plurality of cells connected in parallel between the electrodes 10 and 20. Regions 1 through 6, gate 16, and oxide layer 7 may form one unit of device 100. Fig. 1 shows a second cell comprising an N + region 1-2 and a P + well 4-2, which may be electrically connected (not shown) to a first electrode 10. It will be appreciated that the N + region 1-2, the P + well 4-2 work together with the N-drift region 2, the N + substrate 3, the gate 6 and the oxide layer 7 to provide a further unipolar conduction structure and an additional bipolar conduction structure and function in the same manner as described above. The device 100 may include thousands of cells in order to achieve a desired current rating. The cells share an N-drift region 2 and an N + substrate 3. All of the first conduction paths of the cell may be collectively referred to as the "first conduction path" provided by the "unipolar conduction structure" of the device. All of the second conduction paths of the cell may be collectively referred to as the "second conduction path" provided by the "bipolar conduction structure" of the device.

Fig. 3 schematically shows a cross-section of a power semiconductor device 200 according to a second embodiment of the present invention.

In the device 100, the driving pulse V is applied to the gate electrode 30_GSTo turn on and off the first conduction path P1 provided by the unipolar conduction structure. Gate drive power consumption in response to drive pulse V_GSIs increased linearly. In addition, if the device 100 has a high rated voltage (e.g., 600V to 800V), the gate electrode 30 may have a large capacitance. Therefore, it may be difficult to drive the gate electrode 30 at a high frequency because the gate capacitance is large. In addition, a large current may be required to drive the gate electrode 30, and thus power consumption for driving the gate electrode 30 may be large.

The device 200 solves this problem by providing two separate electrodes 8 and 9 in contact with the P + well 4 and the N + region 1, and by providing a low voltage switch 12 connected in series between the first electrode 10 and the electrode 9. The electrodes 8, 9 are metallized contacts that are in direct contact with the semiconductor. For example, the electrodes 8, 9 may be made of a material selected from the group of aluminum, copper, gold, titanium, or alloys thereof. By low voltage switch 12 is meant a switch having a low voltage rating that is at least lower than the voltage rating of device 200. The other elements of device 200 are identical to the corresponding elements of device 100, which have been given the same reference numerals. The switch 12 may be turned on and off under the control of a control signal (not shown).

Similar to device 100 (fig. 1), device 200 may function as a synchronous rectifier, and when a positive voltage is applied between first electrode 10 and second electrode 20, device 200 has an on-state. The gate electrode 30 is biased positive during the entire duration of the on state. That is, a high voltage (i.e., a logic '1' voltage, generally equal to the voltage level of the power supply) is constantly applied to the gate electrode 30. Therefore, an N-channel exists in the channel region 5 throughout the on-state. The switching on and off of the path P1 between the electrodes 10 and 20 during the on state is accomplished by switching the switch 12 on and off.

In particular, when the switch 12 is open, the electrode 9 is disconnected from the first electrode 10. Thus, although an N-channel exists in channel region 5, no current can flow between electrodes 10 and 20 via path P1, thus breaking path P1 through switch 12. At the same time, second conduction path P2 turns on automatically, injecting minority carriers (i.e., holes of device 200) into N-drift region 2.

When switch 12 is conductive, electrode 9 is electrically connected to first electrode 10, and thus first conduction path P1 conducts current between electrodes 10 and 20. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. At the same time, second conductive path P2 automatically opens or enters a low conductivity mode.

When device 200 is reverse biased (i.e., the potential at first electrode 10 is lower than the potential at second electrode 20), the control signal applied to switch 12 may be synchronized to switch off switch 12 such that path P1 has closed. At the same time, the P-N junction 11 of path P2 is reverse biased and is also unable to conduct current. Therefore, current cannot flow from the second electrode 20 to the first electrode 10, and the device 200 enters an off state. During the off state, the bias voltage applied to the gate electrode 30 may be removed.

Electrode 8 is directly connected to first electrode 10, so the connection between P + well 4 and first electrode 10 bypasses switch 12, allowing current to flow through second conductive path P2 during the off-phase of first conductive path P1.

The low voltage switch 12 may be a low voltage CMOS switch. A control signal for turning on and off the switch 12 may be applied to the gate of the switch 12. Such low voltage CMOS switches have very low gate capacitance and can be turned on and off at high frequencies using logic signals. It is not necessary to provide a large current for driving the switch 12. The power consumption for driving the switch 12 may be significantly lower than the power consumption for driving the gate electrode 30 of the device 100.

Switch 12 may be fabricated on the same silicon substrate as regions 1 through 5 of device 200. Alternatively, the switches may be fabricated on a separate silicon substrate, which may be packaged with the rest of the device 200 in a single package.

Fig. 3 shows a second cell of device 200, which includes N + region 1-2 and P + well 4-2, which are electrically connected to electrodes 9-2 and 8-2, respectively. It will be appreciated that electrode 9-2 may be connected to the bottom node of switch 12 so that switch 12 may switch the first conduction path of the second cell on and off. The electrode 8-2 of the second cell may be directly connected to the first electrode. The structure of the second unit is symmetrical to that of the first unit. It will therefore be appreciated that the N + region 1-2 and the P + well 4-2 work together with the N-drift region 2, the N + substrate 3, the gate 16 and the oxide layer 17 to provide a further unipolar conductive structure and a further bipolar conductive structure, which work in the same manner as described above.

Each of the devices 100 and 200 uses a gate-driven MOS structure (which includes the gate 6, the oxide layer 7 and the channel region 5) as part of a unipolar conductive structure. It should be understood that other types of unipolar conductive structures may be used, as shown in fig. 4 and 6.

Fig. 4 schematically shows a cross-section of a power semiconductor device 300 according to a third embodiment of the present invention.

The device 300 differs from the devices 100, 200 in that the N + region 1 of the device 300 is disposed outside the P + well 4 and in that the N + region 1 is in direct contact with the N-drift region 2. Thus, unless modulated (as described below), the N + region 1 is always electrically connected to the N + substrate 3 via the N-drift region 2. Since the only charge carriers involved in this electrical connection are the majority carriers (i.e., electrons) of regions 1-3, N + region 1, N-drift region 2 and N + substrate 3 form a unipolar conductive structure, which provides first conduction path P1. The device 300 does not have a gate-driven MOS structure.

Similar to device 200, P + well 4 is in contact with electrode 8, electrode 8 is directly connected to first electrode 10, and N + region 1. N + region 1 is connected to a first electrode 10 via a series connected low voltage switch 12. The P-N junction 11 formed between the P + well 4 and the N-drift region 2 provides a second conduction path P2 between the first electrode 10 and the second electrode 20.

As shown in fig. 4, device 300 includes a plurality of cells. Each cell comprises an N + region 1-i connected to the bottom end of a switch 12, a P + well 4-i, and an electrode 8-i between the P + well 4-i and the first electrode 10. The number i varies from 2 to N, N being the total number of cells. For illustrative purposes only, N is equal to 5 in fig. 4. The P + wells 4, 4-2.. 4-N are spaced apart from each other. Each of the N + regions 1, 1-2.. 1-N is disposed between adjacent P + wells. All cells share the switch 12, the N-drift region 2 and the N + substrate 3.

Similar to the devices 100, 200, the device 300 may function as a synchronous rectifier and have an on-state when a positive voltage is applied between the first electrode 10 and the second electrode 20.

During the on state, the switch 12 is switched on and off at a high frequency. When the switch 12 is open, no current can flow between the electrodes 10 and 20 via path P1, and therefore current flows only through path P2, injecting minority carriers (i.e., holes of the device 300) into the N-drift region 2. When the switch 12 is turned on, the first conduction path P1 is accordingly turned on. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. At the same time, the second conductive path P2 automatically opens or enters a low conductivity mode because the on-state voltage of path P1 is below the forward threshold voltage of P-N junction 11. In this manner, the average on-state voltage of the device 300 is reduced to a level below the knee voltage of the P-N junction 11. It will be appreciated that along path P1 the conductivity modulation received by a portion of the N-drift region 2 is due to conduction around the second conductive path in each of the first and second cells of path P1.

When device 300 is reverse biased (i.e., the potential at first electrode 10 is lower than the potential at second electrode 20), the control signal applied to switch 12 may be synchronized to switch off switch 12 such that path P1 is closed. At the same time, the P-N junctions 11, 11-2 are reverse biased and do not conduct current. Thus, the device 300 enters the off state.

Alternatively or additionally, the device 300 may be designed such that when the device 300 is reverse biased, it automatically enters the off state regardless of the control signal applied to the switch 12. In particular, when the device 300 is reverse biased, there are depletion regions on both sides of the P-N junction 11. Because the N-drift region 2 is low doped, the depletion region within the N-drift region 2 is much wider than the depletion region within the P + well 4. Similarly, the P-N junction 11-2 between the P + well 4-2 and the N-drift region 2 also has a wide depletion region within the N-drift region 2. The distance L between adjacent P + wells 4, 4-2 may be arranged such that the depletion regions within the N-drift region 2 created by the two P-N junctions 11, 11-2 contact each other. Therefore, the first conduction path P1 is pinched off by the depletion region regardless of the on/off state of the switch 12. The device 200 enters the off state because the reverse biased P-N junction 11 of path P2 is also unable to conduct current.

Fig. 4 shows that the P + well 4, 4-2.. 4-N is disposed adjacent to the top surface of the N-drift region 2 and the electrode 8, 8-2.. 8-N is in contact with the top surface of the P + well. In an alternative arrangement as shown in fig. 5, a trench 13 is provided within the N-drift region 2 adjacent the top surface of the N-drift region 2. The trench 13 has a width W and may be formed by an etching process. A P + well 4 is provided around the side walls and bottom wall of the trench 13. The P + well 4 may be formed by diffusion. The electrode 8 is in contact with the side wall and the bottom wall of the P + well 4. The electrode 8 may be formed by a sputtering process. Similar to fig. 4, the electrode 8 is in direct contact with the first electrode 10. The arrangement of trenches 13, P + wells 4 and electrodes 8 as shown in fig. 5 may be used in place of P + wells 4, 4-i and electrodes 8, 8-i in at least one cell of device 300.

As shown in fig. 4, the cross-sectional shape of the outer boundary 14 of the P + well 4 generally resembles a square. It will be appreciated that in practice, due to the nature of the diffusion process used to fabricate the P + well 4, the outer boundary 14 of the P + well 4 has a rounded corner at location 15. By introducing the trenches 13, the P + well 4 of fig. 5 can be formed by a shallow diffusion process that provides a diffusion depth that is less than the diffusion process required to fabricate the P + well 4 of fig. 4. Thus, the outer boundary 14 of the P + well 4 in fig. 5 is closer to a square shape than the outer boundary 14 of the P + well 4 in fig. 4. The "square" shape of the P + wells 4, 4-i makes it easier for the depletion region within the N-drift region 2 to engage and pinch off the first conduction path P1 as described above. Thus, by modifying device 300 using the arrangement shown in fig. 5, device 300 can quickly stop current flow when device 300 switches from its on-state to its off-state, thus achieving pinch-off of conductive path P1 with a lower reverse bias. Furthermore, the arrangement shown in FIG. 5 allows the P + wells 4, 4-i and N + regions 1, 1-i to be densely packed, thereby reducing the overall footprint of the device 300.

Fig. 6 schematically shows a cross-section of a power semiconductor device 400 according to a fourth embodiment of the present invention.

Similar to device 300, device 400 does not have a gate-driven MOS structure. However, device 400 differs from device 300 in that N + region 1 is disposed within P + well 4, and N + region 1 has a boundary substantially aligned with the boundary of P + well 4, such that N + region 1 is in direct contact with N-drift region 2. It will be appreciated that the boundary N + region 1 may protrude slightly beyond the boundary of the P + well 4 and that the device 400 functions as long as the N + region 1 is electrically connected directly to the N + substrate 3 via the N-drift region 2. No P-type channel region (similar to channel region 5 of fig. 3) is formed between N + region 1 and N-drift region 2. Since the only charge carriers participating in the electrical connection are the majority carriers (i.e., electrons) of the regions 1 to 3, the N + region 1, the N-drift region 2, and the N + substrate 3 form a unipolar conductive structure, which provides the first conduction path P1.

Similar to device 200, P + well 4 of device 400 is in contact with electrode 8, electrode 8 is directly connected to first electrode 10, and N + region 1 is in contact with electrode 9, electrode 9 being connected to first electrode 10 via a series-connected low voltage switch 12. The P-N junction 11 formed between the P + well 4 and the N-drift region 2 provides a second conduction path P2 between the first electrode 10 and the second electrode 20.

The operation of device 400 is very similar to the operation of device 300 described above. Specifically, when the device 400 is reverse biased, the depletion region within the N-drift region 2 can spread out from the boundary of the P + wells 4, 4-2 to pinch off the first conduction path P1.

Devices 300 and 400 have the following advantages: no gate-driven MOS structure or gate connection is required and therefore the device 300, 400 is simple to manufacture in that there are only two metallization contacts (i.e. electrodes 8 and 9) on the top surface of the device, which avoids the need for overlapping electrode contacts.

Furthermore, the above description of the advantages provided by device 100 and the power electronics applications in which device 100 may be used applies equally to devices 200 to 400.

It should be understood that although planar MOSFET structures with horizontal channels are used as unipolar conductive structures in the devices 100, 200, other device structures, such as trench MOS (U-MOS), may also be used. Indeed, it should be understood that there are many other equivalent device structures that may be used as unipolar conductive structures, all of which are within the scope of the present invention.

In addition, the unipolar conduction structure within device 100-400 uses electrons to conduct current. It should be understood that a unipolar conductive structure may alternatively use holes to conduct current. However, the mobility of the holes is lower than that of the electrons, and the resistivity of the first conduction path provided by the hole-based unipolar conduction structure may be higher than that provided by the electron-based unipolar conduction structure.

It should be understood that all of the doping polarities described above may be reversed and the resulting device still conform to the present invention. In the present invention, the n-type doping polarity is generally referred to as a first conductivity type, and the p-type doping polarity is referred to as a second conductivity type. However, the skilled person will be able to invert them to form the appropriate devices. The invention also covers all devices formed with reversed doping polarities. Furthermore, it should be understood that the terminals and associated contact regions of the device may be arranged out-of-plane or otherwise aligned such that the direction of the carriers is not exactly as described above, and the resulting device still conforms to the present invention.

It will be appreciated by those skilled in the art that in the foregoing description and appended claims, positional terms such as "top", "bottom", "above", "overlapping", "below", "side", "vertical", and the like, refer to conceptual illustrations of semiconductor devices, such as those shown in standard cross-sectional perspective views and the accompanying drawings. These terms are used for ease of reference, but are not limiting. Accordingly, these terms should be understood to refer to the transistor when in the orientation as shown in the drawings.

While the present invention has been described in terms of the preferred embodiments described above, it should be understood that these embodiments are illustrative only, and the claims are not limited to those embodiments. In view of the present disclosure, those skilled in the art will be able to make modifications and substitutions that are considered to be within the scope of the appended claims. Each feature disclosed or illustrated in this specification, either individually or in any appropriate combination with any other feature disclosed or illustrated herein, may be incorporated in the invention.