阅读说明：本技术 模拟数字转换器 (Analog-to-digital converter ) 是由 吴盈澄 黄诗雄 于 2018-07-26 设计创作，主要内容包括：本发明披露了一种模拟数字转换器,包含一模拟电路、一第一开关、一第二开关、一第一电容及一第二电容。模拟电路具有一第一输入端及一第二输入端,用来放大及/或比较该第一输入端及该第二输入端上的信号。第一电容的其中一端耦接该第一输入端,另一端经由该第一开关接收一输入电压。第二电容的其中一端耦接该第一输入端,另一端经由该第二开关接收一参考电压。(The invention discloses an analog-digital converter, which comprises an analog circuit, a first switch, a second switch, a first capacitor and a second capacitor. The analog circuit has a first input terminal and a second input terminal for amplifying and/or comparing signals at the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input end, and the other end receives an input voltage through the first switch. One end of the second capacitor is coupled to the first input end, and the other end receives a reference voltage through the second switch.)

1. An analog-to-digital converter comprising:

an analog circuit having a first input terminal and a second input terminal for amplifying and/or comparing signals at the first input terminal and the second input terminal;

a first switch;

a second switch;

a first capacitor, wherein one end of the first capacitor is coupled to the first input terminal, and the other end of the first capacitor receives an input voltage through the first switch; and

and a second capacitor, wherein one end of the second capacitor is coupled to the first input end, and the other end of the second capacitor receives a reference voltage through the second switch.

2. The analog-to-digital converter of claim 1, wherein the input voltage is a first input voltage, the reference voltage is a first reference voltage, the analog-to-digital converter further comprising:

a third switch;

a fourth switch;

a third capacitor, wherein one end of the third capacitor is coupled to the second input terminal, and the other end of the third capacitor receives a second input voltage through the third switch;

a fourth capacitor, wherein one end of the fourth capacitor is coupled to the second input terminal, and the other end of the fourth capacitor receives a second reference voltage through the fourth switch, and the second reference voltage is different from the first reference voltage; and

and the fifth switch is coupled between the first capacitor and the third capacitor, wherein when the fifth switch is conducted, the first capacitor and the third capacitor are electrically connected.

3. The analog-to-digital converter of claim 2, wherein when the fifth switch is turned on, the electrically connected terminals of the first capacitor and the third capacitor are floating and are not coupled or electrically connected to any voltage.

4. The analog-to-digital converter of claim 2, further comprising:

and the sixth switch is coupled between the second capacitor and the fourth capacitor, wherein when the sixth switch is switched on, the second capacitor is electrically connected with the fourth capacitor.

5. The analog-to-digital converter of claim 4, wherein when the sixth switch is turned on, the electrically connected terminals of the second capacitor and the fourth capacitor are floating and are not coupled or electrically connected to any voltage.

6. The analog-to-digital converter of claim 1, wherein the input voltage is a first input voltage, the reference voltage is a first reference voltage, the analog-to-digital converter further comprising:

a third switch;

a fourth switch;

a third capacitor, wherein one end of the third capacitor is coupled to the second input terminal, and the other end of the third capacitor receives a second input voltage through the third switch;

a fourth capacitor, wherein one end of the fourth capacitor is coupled to the second input terminal, and the other end of the fourth capacitor receives a second reference voltage through the fourth switch, and the second reference voltage is different from the first reference voltage; and

and the fifth switch is coupled between the second capacitor and the fourth capacitor, wherein when the fifth switch is switched on, the second capacitor is electrically connected with the fourth capacitor.

7. The ADC of claim 6, wherein when the fifth switch is turned on, the electrically connected terminals of the second capacitor and the fourth capacitor are floating and are not coupled or electrically connected to any voltage.

8. An analog-to-digital converter comprising:

an analog circuit having a first input terminal and a second input terminal for amplifying and/or comparing signals at the first input terminal and the second input terminal;

a first switch;

a second switch;

a third switch;

a fourth switch;

a first capacitor, wherein one end of the first capacitor is coupled to the first input end, and the other end of the first capacitor receives an input voltage through the first switch or receives a first reference voltage through the third switch; and

and a second capacitor, wherein one end of the second capacitor is coupled to the first input end, and the other end of the second capacitor receives a second reference voltage through the second switch or receives a third reference voltage through the fourth switch.

9. The analog-to-digital converter of claim 8, wherein the input voltage is a first input voltage, the analog-to-digital converter further comprising:

a fifth switch;

a sixth switch;

a seventh switch;

an eighth switch;

a third capacitor, wherein one end of the third capacitor is coupled to the second input terminal, and the other end of the third capacitor receives a second input voltage through the fifth switch or receives the first reference voltage through the seventh switch; and

and a fourth capacitor, wherein one end of the fourth capacitor is coupled to the second input terminal, and the other end of the fourth capacitor receives a fourth reference voltage through the sixth switch or receives the third reference voltage through the eighth switch.

10. The adc of claim 9, wherein the capacitance of the first capacitor is the same as the capacitance of the third capacitor, and the capacitance of the second capacitor is the same as the capacitance of the fourth capacitor.

Technical Field

The present invention relates to analog-to-digital converters (ADCs).

Background

Fig. 1 is a circuit diagram of a conventional analog-to-digital converter. The ADC 100 includes a comparator 110 and a capacitor C_pCapacitor C_nAnd switches S1a, S2a, S3a, S1b, S2b, S3 b. ADC 100 based on non-overlapping (non-overlapping) two clocks Φ₁And phi₂(as shown in fig. 2) alternately operate in the first phase and the second phase. Assuming that the circuit is operating at a high level of the clock (e.g., the switch is turned on), the first phase is a high level period of one of the clocks, and the second phase is a high level period of the other clock, and "non-overlapping" means that the two clocks are not at the high level at the same time. Clock phi₁And phi₂There are non-overlapping intervals-between times t1 and t2 and between t1 'and t 2'. Even if the clock phi₁When the falling edges of the two are substantially alignedClock phi₂I.e., t 1-t 2 and clock Φ₁Substantially aligned with the clock phi₂The falling edge of (i.e., t1 ═ t 2'), clock Φ₁And phi₂There are still two clocks that do not overlap.

Returning to fig. 1. Input voltage V_in+And an input voltage V_in-Is a differential voltage input to the ADC 100, and the voltage V_th+、V_th-、V_b2Is a reference voltage. When clock phi₁When high, the switches S1a, S3a, S1b, S3b are conductive and the switches S2a, S2b are non-conductive, so that the capacitor C is turned on_pAnd a capacitor C_nSeparately sampling input voltage V_in+And an input voltage V_in-. When clock phi₂At high, switches S2a, S2b are conductive and switches S1a, S3a, S1b, S3b are non-conductive through capacitor C_pAnd a capacitor C_nThe voltage conversion on the signal to achieve the addition or subtraction of the signals. Comparator 110 at clock phi₂Compares and/or amplifies the signals of the two input terminals of the comparator 110 when the voltage level is high to generate the output signal V_out+And V_out-. Output signal V_out+And V_out-I.e. the input voltage (V)_in+And V_in-) And (5) performing analog-digital conversion on the obtained result.

Because of the capacitance C_p(or capacitance C)_n) Alternately receives an input voltage V_in+(or input voltage V)_in-) And a reference voltage V_th+(or V)_th-) So that inter-symbol interference (ISI) (i.e., the reference voltage V) is easily generated_thInfluencing the input voltage V of the next stage_inSampling of (d). Furthermore, when the reference voltage V is_thThe common mode voltage and the input voltage V_inWhen the common mode voltages are different, the ADC 100 is easily unstable.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide an analog-to-digital converter to reduce inter-symbol interference and avoid circuit instability caused by mismatched common mode voltages.

The invention discloses an analog-digital converter, which comprises an analog circuit, a first switch, a second switch, a first capacitor and a second capacitor. The analog circuit has a first input terminal and a second input terminal for amplifying and/or comparing signals at the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input end, and the other end receives an input voltage through the first switch. One end of the second capacitor is coupled to the first input end, and the other end receives a reference voltage through the second switch.

The present invention further discloses an analog-to-digital converter, which includes an analog circuit, a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor. The analog circuit has a first input terminal and a second input terminal for amplifying and/or comparing signals at the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input end, and the other end receives an input voltage through the first switch or receives a first reference voltage through the third switch. One end of the second capacitor is coupled to the first input end, and the other end receives a second reference voltage through the second switch or a third reference voltage through the fourth switch.

Compared with the prior art, the analog-digital converter can reduce the inter-symbol interference and improve the stability.

The features, practice and effect of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 is a circuit diagram of a conventional analog-to-digital converter;

FIG. 2 shows two non-overlapping clocks Φ₁And phi₂；

FIG. 3 is a circuit diagram of an embodiment of an analog-to-digital converter according to the present invention;

FIG. 4 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention;

FIG. 5 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention;

FIG. 6 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention; and

FIG. 7 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention.

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or definition in the specification.

The present disclosure includes an analog to digital converter. Since some of the components included in the analog-to-digital converter of the present invention may be known components alone, the following description will omit details of the known components without affecting the full disclosure and feasibility of the present invention.

In the following description, one end of the capacitor-coupled comparator or amplifier is referred to as an upper plate, and one end of the capacitor-uncoupled comparator or amplifier is referred to as a lower plate. Such definitions are for convenience of description only and do not necessarily relate to "up" and "down" in actual circuitry. The first stage and the second stage may be high-level (or low-level) periods of two clocks that do not overlap, or may be high-level and low-level periods of a single clock.

FIG. 3 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention. The ADC200 includes an analog circuit 210 and a capacitor C_1a、C_2a、C_1b、C_2bAnd switches S1a, S2a, S3a, S4a, S5a, S1b, S2b, S3b, S4b, S5 b. The analog circuit 210 has two input terminals and two output terminals, and the analog circuit 210 amplifies and/or compares signals on the two input terminals. The analog circuit 210 may be an amplifier (e.g., an operational amplifier), a comparator, or a combination of an amplifier and a comparator (e.g., amplify a signal before compare). The practice of analog-to-digital converters using amplifiers and/or comparators is well known to those of ordinary skill in the art and will not be described in detail. The ADC200 alternately operates in the first phase and the second phase.

Capacitor C_1aAnd a capacitor C_2aOne of the input terminals of the analog circuit 210 is coupled to the capacitor C_1bAnd a capacitor C_2bCoupled to another input of the analog circuit 210. In some embodiments, the capacitance C_1a、C_2a、C_1b、C_2bThe upper board of (1) is directly coupled (electrically connected) to the analog circuit 210 (shown in fig. 3).

Input voltage V_in+And an input voltage V_in-Is a differential signal input to the ADC200 and typically varies over time. Reference voltage V_th+And V_th-Is substantially constant (DC bias), and V_th+Is not equal to V_th-. Input voltage V_in+Is not equal to the reference voltage V_th+And an input voltage V_in-Is not equal to the reference voltage V_th-. Reference voltage V_b3、V_b4And V_b5It is also substantially fixed and the relationship between the three is not limited. In some embodiments when reference voltage V_th+And a reference voltage V_th-When interchanging, the digital code output by the ADC200 is inverted, i.e. the output signal V_out+And an output signal V_out-And (4) interchanging.

In some embodiments, the capacitance C_1aCapacitance value of (C) and capacitance C_2aMay be equal or different, and the capacitance C_1bCapacitance value of (C) and capacitance C_2bMay be equal or unequal. Capacitor C_1aCapacitance value of (C) and capacitance C_1bHas substantially the same capacitance value, and the capacitor C_2aCapacitance value of (C) and capacitance C_2bAre substantially the same.

ADC200 has two capacitors C_1aAnd C_2a(or C)_1bAnd C_2b) Separately sampling input voltage V_in+(or V)_in-) And a reference voltage V_th+(or V)_th-) Thus the input voltage V_in+(or V)_in-) And a reference voltage V_th+(or V)_th-) The interference between symbols can be avoided, and the problem of symbol interference encountered by the conventional analog-digital converter can be solved. Furthermore, the ADC200 may be implemented by adjusting the voltage V_b3And V_b4To compensate for the input voltage V_in+(or V)_in-) The common mode voltage and the reference voltage V_th+(or V)_th-) Of common mode voltageAnd the difference value is used for improving the stability of the circuit. For example, if the input voltage V_in+(or V)_in-) Is compared with a reference voltage V_th+(or V)_th-) The common mode voltage of (2) V is larger than 0.2V, then V can be designed_b4Ratio V_b30.2 volts greater.

There are two modes of operation of the ADC 200. One end of the analog circuit 210 is taken as an example for explanation. The operation of the other end of the analog circuit 210 will be understood by those of ordinary skill in the art in view of the following description.

The first operation mode is as follows:

in the first phase, the switches S1a, S2a, S5a are conductive, and the switches S3a, S4a are non-conductive. In other words, the capacitance C is in the first stage_1aIs coupled or electrically connected to the input terminal of the analog circuit 210 and receives a reference voltage V_b5Capacitor C_1aThe lower plate receives an input voltage V_in+Capacitor C_2aIs coupled or electrically connected to the input terminal of the analog circuit 210 and receives a reference voltage V_b5Capacitor C_2aReceives a reference voltage V_th+. In the first stage, the capacitor C_1aSampling input voltage V_in+And a capacitor C_2aSampling reference voltage V_th+。

In the second phase, the switches S3a, S4a are conductive, and the switches S1a, S2a, S5a are non-conductive. In other words, the capacitance C is set during the second phase_1aThe upper plate of (a) is coupled to or electrically connected with the input terminal of the analog circuit 210 and the capacitor C_1aReceives a reference voltage V_b4Capacitor C_2aThe upper plate of (a) is coupled to or electrically connected with the input terminal of the analog circuit 210 and the capacitor C_2aReceives a reference voltage V_b3。

The capacitor C is used during the switching of the ADC200 from the first phase to the second phase_1aAnd C_2aTo realize a signal (i.e. the input voltage V) by varying the terminal voltage_in+And a reference voltage V_th+) Add or subtract. The analog circuit 210 amplifies and/or compares the signals at its two inputs in the second stage.

The second operation mode is as follows:

in the first phase, the switches S3a, S4a, S5a are conductive, and the switches S1a, S2a are non-conductive. In other words, the capacitance C is in the first stage_1aIs coupled or electrically connected to the input terminal of the analog circuit 210 and receives a reference voltage V_b5Capacitor C_1aReceives a reference voltage V_b4Capacitor C_2aIs coupled or electrically connected to the input terminal of the analog circuit 210 and receives a reference voltage V_b5Capacitor C_2aReceives a reference voltage V_b3. In the first stage, the capacitor C_1aUpper and lower plates of and capacitor C_2aBoth the upper and lower plates of (1) are in a reset state.

In the second phase, the switches S1a, S2a are conductive, and the switches S3a, S4a, S5a are non-conductive. In other words, the capacitance C is set during the second phase_1aThe upper plate of (a) is coupled to or electrically connected with the input terminal of the analog circuit 210 and the capacitor C_1aThe lower plate receives an input voltage V_in+Capacitor C_2aThe upper plate of (a) is coupled to or electrically connected with the input terminal of the analog circuit 210 and the capacitor C_2aReceives a reference voltage V_th+. The analog circuit 210 amplifies and/or compares the signals at its two inputs in the second stage.

Similar to the first operation, the capacitor C is switched during the switching of the ADC200 from the first phase to the second phase_1aAnd C_2aTo realize a signal (i.e. the input voltage V) by varying the terminal voltage_in+And a reference voltage V_th+) Add or subtract. The analog circuit 210 amplifies and/or compares the signals at its two inputs in the second stage.

FIG. 4 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention. ADC 300 is similar to ADC200, except that ADC 300 simulates the output signal V of circuit 210_out+/V_out-Instead of the reference voltage V_b5This eliminates the need for a reference voltage, making the circuitry of the ADC 300 simpler than that of the ADC 200. Generally, the analog circuit 210 is reset during the first stage, so that the output signal V is outputted_out+And an output signal V_out-Substantially equal in the first phase.

FIG. 5 illustrates the analog-to-digital conversion of the present inventionA circuit diagram of another embodiment of the device. ADC 400 is similar to ADC 300, with the difference that in ADC 400, capacitor C_1aLower plate and capacitor C_1bThe lower plate in the second stage does not receive or is coupled to the reference voltage V_b4But are electrically connected to each other through the switch S3. In other words, the switch S3 is coupled to the capacitor C_1aAnd a capacitor C_1bTo (c) to (d); more specifically, the switch S3 is coupled to the capacitor C_1aLower plate and capacitor C_1bBetween the lower plates. The on time of the switch S3 of the ADC 400 is the same as the on time of the switches S3a and S3b of the ADC 200.

In the embodiment of fig. 5, when switch S3 is turned on, capacitor C_1aAnd a capacitor C_1bThe electrically connected terminals (i.e., the lower plates of the two capacitors) are floating, i.e., not coupled or electrically connected to any voltage (including ground) provided by the inside or outside of the chip on which the ADC 400 is located. Because the capacitor C is turned on when the switch S3 is turned on_1aLower plate and capacitor C_1bThe lower plate is electrically connected and floating connected, so that the capacitor C_1aVoltage of the lower plate (i.e. capacitance C)_1bVoltage of the lower plate) is the input voltage V when the switch S3 is on_in+And an input voltage V_in-Of the common mode voltage. The ADC 400 has at least the following advantages: (1) one reference voltage (i.e., V of FIG. 4) is omitted compared to ADC 300_b4) (ii) a And (2) avoiding common mode voltage offset of the upper plate of the capacitor (such as input voltage V in the prior circuit) caused by the common mode voltage of the lower plate of the capacitor in the first stage not being equal to the common mode voltage in the second stage_in+(or V)_in-) The common mode voltage and the reference voltage V_th+(or V)_th-) May be different).

FIG. 6 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention. ADC500 is similar to ADC 300, with the difference that capacitor C is in ADC500_2aLower plate and capacitor C_2bThe lower plate in the second stage does not receive or is coupled to the reference voltage V_b3But are electrically connected to each other through the switch S4. In other words, the switch S4 is coupled to the capacitor C_2aAnd a capacitor C_2bTo (c) to (d); more specifically, the switch S4 is coupled to the capacitor C_2aLower plate and capacitor C_2bBetween the lower plates. The on time of the switch S4 of the ADC 400 is the same as the on time of the switches S4a and S4b of the ADC 200.

In the embodiment of fig. 6, when switch S4 is turned on, capacitor C_2aLower plate and capacitor C_2bThe lower plate of (a) is floating, i.e., not coupled or electrically connected to any voltage (including ground) provided by the inside or outside of the chip on which the ADC500 is located. Because the capacitor C is turned on when the switch S4 is turned on_2aLower plate and capacitor C_2bThe lower plate is electrically connected and floating connected, so that the capacitor C_2aVoltage of the lower plate (i.e. capacitance C)_2bVoltage of the lower plate) is the reference voltage V when the switch S4 is turned on_th+And a reference voltage V_th-Of the common mode voltage. The ADC500 has at least the following advantages: (1) one reference voltage (i.e., V of FIG. 4) is omitted compared to ADC 300_b3) (ii) a And (2) avoiding the common mode voltage of the upper plates of the capacitors from being shifted because the common mode voltage of the lower plates of the capacitors in the first stage is not equal to the common mode voltage in the second stage.

FIG. 7 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention. ADC 600 is a combination of ADC 400 and ADC 500. In other words, the ADC 600 eliminates the two reference voltages and further reduces the possibility of common mode voltage offset on the upper plate of the capacitor (i.e., the input of the analog circuit 210) compared to the ADC 300.

Any one of the ADCs 200-600 is a one-bit analog-to-digital converter. A plurality of ADCs 200-600 connected in series and a reference voltage V designed appropriately_th+And V_th-A multi-bit analog-to-digital converter can be realized. For example, connecting three serially can implement a two-bit adc, connecting seven serially can implement a three-bit adc, and so on.

Because the details of the implementation and variations of the present invention can be understood by those skilled in the art from the disclosure of the present invention, the repetitive description is omitted here for the sake of avoiding unnecessary detail without affecting the disclosure requirements and the implementation of the present invention. It should be noted that the shapes, sizes, proportions, and sequence of steps of the elements and steps shown in the drawings are illustrative only and not intended to limit the invention, which is understood by those skilled in the art.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

Description of the symbols

100、200、300、400、500、600 ADC

110 comparator

C_p、C_n、C_1a、C_2a、C_1b、C_2bCapacitor with a capacitor element

V_in+、V_in-Input voltage

V_th+、V_th-、V_b2、V_b3、V_b4、V_b5Reference voltage

V_out+、V_out-Output signal

210 analog circuit

S1a, S2a, S3a, S4a, S5a, S1b, S2b, S3b, S4b, S5b, S3, S4 switches.