阅读说明：本技术 一种指令流水线的预译码系统及方法 (Pre-decoding system and method of instruction pipeline ) 是由 吴汉明 朱敏 于 2019-09-02 设计创作，主要内容包括：本发明公开了一种指令流水线的预译码系统及方法,预译码系统包括：依次连接的指令流水线、指令存储器、预译码逻辑和下一级存储器,指令存储器与下一级存储器连接；预译码逻辑用于当确定从下一级存储器中取出的当前指令为转移指令时根据当前指令的地址和第一转移指令编码信息得到当前指令的第二转移指令编码信息并输出至指令存储器；指令流水线用于根据从指令存储器中取得的当前指令的第二转移指令编码信息和当前指令的地址得到当前指令的转移目标指令的地址。本发明所提供的系统及方法,避免了重复的预译码动作,可以有效减少处理器流水线前段的动态功耗。(The invention discloses a pre-decoding system and a method of an instruction assembly line, wherein the pre-decoding system comprises: the instruction pipeline, the instruction memory, the pre-decoding logic and the next-stage memory are connected in sequence, and the instruction memory is connected with the next-stage memory; the pre-decoding logic is used for obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information when the current instruction taken out from the next-level memory is determined to be the transfer instruction, and outputting the second transfer instruction coding information to the instruction memory; the instruction pipeline is used for obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory. The system and the method provided by the invention avoid repeated pre-decoding actions and can effectively reduce the dynamic power consumption of the front section of the processor pipeline.)

1. A predecoding system for an instruction pipeline, the predecoding system comprising: the system comprises an instruction pipeline, an instruction memory, predecoding logic and a next-stage memory which are connected in sequence, wherein the instruction memory is connected with the next-stage memory;

the pre-decoding logic is used for obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information when the current instruction taken out from the next-level memory is determined to be a transfer instruction, and outputting the second transfer instruction coding information to the instruction memory;

the instruction pipeline is used for obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory.

2. The system of claim 1, wherein the first branch instruction encoding information includes an instruction type and a branch offset, the second branch instruction encoding information includes a branch instruction identification, a simplified instruction type and branch target information, and the simplified instruction type includes predecoded recognized information and a branch instruction subtype;

the branch instruction identification is used for identifying whether the current instruction is a branch instruction;

the pre-decode identified information is used for identifying whether the branch instruction has already acquired corresponding second branch instruction encoding information through the pre-decode logic;

the branch target information is used for recording the address of the branch target instruction of the branch instruction;

the branch instruction subtype is used to identify the particular type of the branch instruction.

3. The instruction pipeline predecoding system of claim 2, wherein the predecoding logic is configured to:

when the current instruction is determined to be a branch instruction, calculating the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, and obtaining second branch instruction coding information of the current instruction according to the calculated address of the branch target instruction of the current instruction and the first branch instruction coding information of the current instruction.

4. The instruction pipeline predecoding system of claim 3, wherein the predecoding logic is configured to:

when the current instruction is determined to be a branch instruction, calculating to obtain the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, dividing the calculated address of the branch target instruction of the current instruction into a high section and a low section, and taking the low section as the branch target information in the second branch instruction coding information of the current instruction;

and identifying the pre-decoded identified information in the second branch instruction encoding information of the current instruction according to the value of the high-section part and the value of the address high section of the current instruction.

5. The instruction pipeline predecoding system of claim 4, wherein the predecoding logic is configured to:

when it is determined that the value of the address high segment portion of the branch target instruction of the current instruction is equal to the value of the address high segment of the current instruction, the predecoded recognized information in the second branch instruction encoding information of the current instruction is identified as recognized.

6. The instruction pipeline predecoding system of claim 2, wherein the predecoding logic is configured to:

judging whether the current instruction is a branch instruction according to the instruction type in the first branch instruction coding information of the current instruction, and identifying the branch instruction identification and the branch instruction subtype in the second branch instruction coding information of the current instruction according to the judgment result.

7. The pre-decode system of claim 5, wherein the instruction pipeline is configured to:

and determining whether to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoded identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory.

8. The pre-decode system of claim 7, wherein the instruction pipeline is configured to:

and when the pre-decoded identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory is identified, splicing the branch target information in the second branch instruction encoding information of the current instruction with the address of the current instruction in high order to obtain the address of the branch target instruction of the current instruction.

9. A pre-decoding method for an instruction pipeline, applied to the pre-decoding system of the instruction pipeline as claimed in any one of claims 1 to 8, wherein the pre-decoding method comprises:

(1) when the current instruction taken out from the next-level memory is determined to be a transfer instruction, obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information and outputting the second transfer instruction coding information to the instruction memory;

(2) and obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory.

10. The method of claim 9, wherein the first branch instruction encoding information comprises an instruction type and a branch offset, the second branch instruction encoding information comprises a branch instruction identification, a simplified instruction type and branch target information, and the simplified instruction type comprises pre-decoded identified information and a branch instruction subtype;

the branch instruction identification is used for identifying whether the current instruction is a branch instruction;

the pre-decode identified information is used for identifying whether the branch instruction has already acquired corresponding second branch instruction encoding information through the pre-decode logic;

the branch target information is used for recording the address of the branch target instruction of the branch instruction;

the branch instruction subtype is used to identify the particular type of the branch instruction.

Technical Field

The invention relates to the technical field of processors, in particular to a predecoding system and a predecoding method of an instruction pipeline.

Background

In modern processor designs, the instruction pipeline fetches instructions from a first level instruction buffer and commits the execution units for execution. And the instruction binary code stored in the first-level instruction cache is converted into a control signal after the binary code of the instruction is read by the instruction pipeline, so that the operation of each component is indicated.

In order to maintain correct instruction stream and support efficient instruction execution, a predecoding unit and a branch prediction unit are arranged in an instruction pipeline and used for detecting branch instructions existing in the instruction stream, calculating the branch direction of the branch instructions as early as possible, and updating information and adjusting the instruction stream direction timely.

Since the instructions stored in the first-level instruction cache are fetched and executed multiple times, for the branch-type instructions, the predecoding (determining the type of the branch instruction, calculating the branch direction of the program) is performed multiple times. Since most branch class instructions are identical in result of each predecoding, repeated predecoding actions can be considered redundant, and thus, the repetition of these predecoding actions causes a waste of dynamic power consumption during the operation of the processor.

Disclosure of Invention

In view of the defects in the prior art, an object of the present invention is to provide a system and a method for pre-decoding an instruction pipeline, which avoid repeated pre-decoding actions and can effectively reduce the dynamic power consumption of the front stage of the processor pipeline.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a pre-decoding system for an instruction pipeline, the pre-decoding system comprising: the system comprises an instruction pipeline, an instruction memory, predecoding logic and a next-stage memory which are connected in sequence, wherein the instruction memory is connected with the next-stage memory;

the pre-decoding logic is used for obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information when the current instruction taken out from the next-level memory is determined to be a transfer instruction, and outputting the second transfer instruction coding information to the instruction memory;

the instruction pipeline is used for obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory.

Further, a system for predecoding an instruction pipeline as described above, the first branch instruction encoding information includes an instruction type and a branch offset, the second branch instruction encoding information includes a branch instruction identification, a simplified instruction type and branch target information, the simplified instruction type includes predecoded recognized information and a branch instruction subtype;

the branch instruction identification is used for identifying whether the current instruction is a branch instruction;

the pre-decode identified information is used for identifying whether the branch instruction has already acquired corresponding second branch instruction encoding information through the pre-decode logic;

the branch target information is used for recording the address of the branch target instruction of the branch instruction;

the branch instruction subtype is used to identify the particular type of the branch instruction.

Further, a predecoding system of an instruction pipeline as described above, the predecoding logic to:

when the current instruction is determined to be a branch instruction, calculating the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, and obtaining second branch instruction coding information of the current instruction according to the calculated address of the branch target instruction of the current instruction and the first branch instruction coding information of the current instruction.

Further, a predecoding system of an instruction pipeline as described above, the predecoding logic to:

when the current instruction is determined to be a branch instruction, calculating to obtain the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, dividing the calculated address of the branch target instruction of the current instruction into a high section and a low section, and taking the low section as the branch target information in the second branch instruction coding information of the current instruction;

and identifying the pre-decoded identified information in the second branch instruction encoding information of the current instruction according to the value of the high-section part and the value of the address high section of the current instruction.

Further, a predecoding system of an instruction pipeline as described above, the predecoding logic to:

when it is determined that the value of the address high segment portion of the branch target instruction of the current instruction is equal to the value of the address high segment of the current instruction, the predecoded recognized information in the second branch instruction encoding information of the current instruction is identified as recognized.

Further, a predecoding system of an instruction pipeline as described above, the predecoding logic to:

judging whether the current instruction is a branch instruction according to the instruction type in the first branch instruction coding information of the current instruction, and identifying the branch instruction identification and the branch instruction subtype in the second branch instruction coding information of the current instruction according to the judgment result.

Further, a predecoding system of an instruction pipeline as described above, the instruction pipeline to:

and determining whether to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoded identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory.

Further, a predecoding system of an instruction pipeline as described above, the instruction pipeline to:

and when the pre-decoded identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory is identified, splicing the branch target information in the second branch instruction encoding information of the current instruction with the address of the current instruction in high order to obtain the address of the branch target instruction of the current instruction.

A method of predecoding an instruction pipeline, the predecoding method comprising:

(1) when the current instruction taken out from the next-level memory is determined to be a transfer instruction, obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information and outputting the second transfer instruction coding information to the instruction memory;

(2) and obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory.

Further, a pre-decoding method for an instruction pipeline as described above, wherein the first branch instruction encoding information includes an instruction type and a branch offset, the second branch instruction encoding information includes a branch instruction identifier, a simplified instruction type and branch target information, and the simplified instruction type includes pre-decoded recognized information and a branch instruction subtype;

the branch instruction identification is used for identifying whether the current instruction is a branch instruction;

the pre-decode identified information is used for identifying whether the branch instruction has already acquired corresponding second branch instruction encoding information through the pre-decode logic;

the branch target information is used for recording the address of the branch target instruction of the branch instruction;

the branch instruction subtype is used to identify the particular type of the branch instruction.

The invention has the beneficial effects that: the system and the method provided by the invention analyze the transfer instruction in advance through the pre-decoding logic to obtain second transfer instruction coding information and store the second transfer instruction coding information in the instruction memory, and when the control logic of the production line fetches the instruction from the instruction memory, the address of the transfer target instruction of the current instruction can be obtained by directly splicing the transfer target information in the second transfer instruction coding information of the current instruction stored in the instruction memory and the address of the current instruction in a high-section manner, thereby avoiding repeated pre-decoding action and effectively reducing the dynamic power consumption of the front section of the production line of the processor.

Drawings

FIG. 1 is a diagram illustrating a conventional pipeline and predecode logic provided in an embodiment of the present invention;

FIG. 2 is a block diagram of an exemplary embodiment of a predecoding system for an instruction pipeline;

FIG. 3 is a diagram illustrating an encoding format of a branch instruction stored in a next-level memory according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating an encoding format of a branch instruction stored in an instruction memory according to an embodiment of the present invention;

FIG. 5 is a simplified schematic illustration of the simplified instruction type of FIG. 4;

FIG. 6 is a diagram illustrating the operation of the predecode logic according to one embodiment of the present invention;

FIG. 7 is a flowchart illustrating a pre-decoding method of an instruction pipeline according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the detailed description.

The relationship between the conventional pipeline and the predecoding logic is shown in fig. 1, and the caches of the processor are generally organized into a multi-level structure, wherein the instruction pipeline obtains instructions from the first-level instruction cache, and the first-level instruction cache obtains instructions from the lower-level cache. After the instruction pipeline obtains the instruction, the instruction is sent to a predecoding component, wherein the predecoding component mainly comprises the analysis of the instruction type and the calculation of the branch direction executed by a branch type. Since the instructions stored in the first-level instruction cache are fetched and executed multiple times, for the branch-type instructions, the predecoding (determining the type of the branch instruction, calculating the branch direction of the program) is performed multiple times. Since most branch class instructions are identical in result of each predecoding, repeated predecoding actions can be considered redundant, and thus, the repetition of these predecoding actions causes a waste of dynamic power consumption during the operation of the processor.

In view of the above-mentioned drawbacks, the pre-decoding system and method for an instruction pipeline according to the present invention, as shown in fig. 2, mainly includes three aspects: 1) placing predecode logic between a first level instruction cache and a next level cache; 2) designing an instruction storage structure in the first-level instruction cache; 3) and splicing the transfer target addresses in the instruction pipeline. The design of the invention advances the pre-decoding component to the write-in path of the first-level instruction cache, analyzes the transfer instruction in advance, and calculates the transfer direction in advance, thereby avoiding repeated pre-decoding action and effectively reducing the dynamic power consumption of the front section of the processor assembly line.

As shown in FIG. 2, the present invention provides a predecoding system for an instruction pipeline, the predecoding system comprising: the instruction pipeline, the instruction memory, the pre-decoding logic and the next-stage memory are connected in sequence, and the instruction memory is connected with the next-stage memory;

the pre-decoding logic is used for obtaining second transfer instruction coding information of the current instruction according to the address of the current instruction and the first transfer instruction coding information when the current instruction taken out from the next-level memory is determined to be the transfer instruction, and outputting the second transfer instruction coding information to the instruction memory;

the instruction pipeline is used for obtaining the address of the branch target instruction of the current instruction according to the second branch instruction coding information of the current instruction and the address of the current instruction, which are obtained from the instruction memory.

The first transfer instruction encoding information comprises an instruction type and a transfer offset, the second transfer instruction encoding information comprises a transfer instruction identifier, a simplified instruction type and transfer target information, and the simplified instruction type comprises pre-decoded recognized information and a transfer instruction subtype;

the branch instruction identification is used for identifying whether the current instruction is a branch instruction or not;

the pre-decoding recognized information is used for identifying whether the branch instruction obtains corresponding second branch instruction coding information through pre-decoding logic;

the branch target information is used for recording the address of the branch target instruction of the branch instruction;

the branch instruction subtype is used to identify the specific type of the branch instruction.

The predecode logic is to:

when the current instruction is determined to be a branch instruction, calculating the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, and obtaining second branch instruction coding information of the current instruction according to the calculated address of the branch target instruction of the current instruction and the first branch instruction coding information of the current instruction.

The predecode logic is to:

when the current instruction is determined to be a branch instruction, calculating to obtain the address of a branch target instruction of the current instruction according to the branch offset in the first branch instruction coding information of the current instruction and the address of the current instruction, dividing the calculated address of the branch target instruction of the current instruction into a high section and a low section, and taking the low section as the branch target information in the second branch instruction coding information of the current instruction;

and identifying the pre-decoded identified information in the second branch instruction encoding information of the current instruction according to the value of the high-section part and the value of the address high section of the current instruction.

The predecode logic is to:

when it is determined that the value of the address high segment portion of the branch target instruction of the current instruction is equal to the value of the address high segment of the current instruction, the predecoded recognized information in the second branch instruction encoding information of the current instruction is identified as recognized.

The predecode logic is to:

judging whether the current instruction is a branch instruction according to the instruction type in the first branch instruction coding information of the current instruction, and identifying the branch instruction identification and the branch instruction subtype in the second branch instruction coding information of the current instruction according to the judgment result.

The instruction pipeline is to:

and determining whether to obtain the address of the branch target instruction of the current instruction according to the second branch instruction encoding information of the current instruction and the address of the current instruction according to the pre-decoded identified information in the second branch instruction encoding information of the current instruction obtained from the instruction memory.

The instruction pipeline is to:

and when the pre-decoded identification information in the second branch instruction coding information of the current instruction obtained from the instruction memory is identified, splicing the branch target information in the second branch instruction coding information of the current instruction with the address of the current instruction to obtain the address of the branch target instruction of the current instruction.

The invention analyzes the first transfer instruction coding information of the transfer instruction in advance through the pre-decoding logic to obtain the second transfer instruction coding information to be stored in the instruction memory, when the control logic of the production line fetches the instruction from the instruction memory, the transfer target information in the second transfer instruction coding information of the current instruction stored in the instruction memory can be directly spliced with the address high section of the current instruction to obtain the address of the transfer target instruction of the current instruction, thereby avoiding repeated pre-decoding action and effectively reducing the dynamic power consumption of the front section of the production line of the processor.

The working principle is as follows:

the invention arranges the pre-decoding logic between the first level instruction cache and the next level cache, all instructions obtained from the next level cache need to be analyzed by the pre-decoding logic, the transfer instruction is identified, and the transfer direction is calculated. For most branch-type instructions, the calculation of branch targets is unchanged in each execution, and the branch target calculation method for the branch-type instructions comprises the following steps:

branch target is local instruction address + local instruction encoding partial field one

After the predecode logic identifies the branch type of the instruction and calculates the branch direction, the information (including the branch type and the branch direction) is written into the first level instruction cache. In the conventional processor design, the instruction encoding information written in the instruction cache of the first level (instruction memory in fig. 1) is completely consistent with the encoding information of the instruction in the instruction cache of the next level (instruction memory of the next level in fig. 1), and the branch instruction encoding information in the conventional processor is shown in fig. 3. In the invention, a new instruction coding information format is provided, which mainly aims to distinguish branch instructions and non-branch instructions with minimum overhead, and simultaneously records the branch instruction information identified by predecoding logic in the instruction coding.

As shown in fig. 2, the information transmitted to the predecoding logic by the next-stage memory includes a plurality of instructions, the information of each instruction is as shown in fig. 3, that is, the first branch instruction encoding information, the information transmitted to the instruction memory by the predecoding logic corresponds to the plurality of instructions, and the information of each instruction is as shown in fig. 4, that is, the second branch instruction encoding information.

The branch instruction encoding information of the present invention is shown in fig. 4, and the main difference from the standard instruction encoding structure of fig. 3 is that:

(1) the instruction encoding width of FIG. 3 is increased by 1 bit to identify whether the current instruction is a branch type instruction, i.e., C bit in FIG. 4.

(2) The "instruction type" field in fig. 3 is shortened, all instruction types that can be identified by the encoding processor are required for the "instruction type" field in fig. 3, and only different branch instructions need to be distinguished for the "simplified instruction type" in fig. 4, that is, the "branch instruction subtype" in fig. 5 has pertinence, wherein the "recognized predecode" is marked as 1 bit, and whether the encoding of the branch instruction has been completely converted by predecode logic is marked. Instructions that cannot be fully converted by the predecode logic include two classes:

a) the branch target calculation method does not belong to the branch target calculation methods listed above;

for example: the branch target address is the value of a certain register plus the instruction address, wherein the value of the certain register needs to be obtained through one register reading operation.

The branch instruction that the processor needs to process has many types, one of which is the case of a), and the calculation of its branch target address needs to be dynamically changed each time it is executed (the root is that the calculation of its target address needs to obtain a dynamic register value), so it cannot be calculated in advance. The invention is applicable to another type of branch instruction whose branch target calculation depends only on static information, so that advance calculation can be implemented.

b) Branch instructions for which the branch target calculated by the predecode logic cannot be validly stored in the "branch target" field in fig. 4. In both cases a) and b), the predecode logic of the present invention will retain the "branch offset" field in the encoded information of the original branch instruction of the instruction, and will not convert it to the "branch target" field described below.

(3) The "branch offset" field in FIG. 3 is converted to the "branch target" field in FIG. 4 for recording the address of the branch target instruction for the branch instruction. Since the instruction address width of a processor typically exceeds the instruction encoding width, the "branch target" field in FIG. 4 cannot fully store the full branch target address. In the present invention, the address (branch target address) of the branch target instruction of the current instruction calculated by the predecoding logic is divided into two sections, namely, a high section and a low section, wherein the low section is stored in the 'branch target' field shown in fig. 4, and when the pipeline executes the branch instruction, two addresses exist: the address of the branch instruction itself and the address of the branch target instruction. The pipeline has a special structure for storing and maintaining the address of the branch instruction, and in the invention, the high section of the address of the branch target instruction directly uses the high section of the address of the branch instruction.

If the value of the high segment of the current instruction address is equal to the high segment of the branch target address, setting a mark of 'pre-decoding recognized', indicating that when the instruction is output from the instruction memory shown in fig. 2, the branch target address can be obtained by directly splicing a 'branch target' field in the second branch instruction encoding information and the high segment of the 'address of the current instruction', and the judgment and the setting are both in charge of pre-decoding logic.

If the value of the high segment of the current instruction address is not equal to the high segment of the branch target address, corresponding to the situation of b) above, the branch target calculated by the predecoding logic cannot be effectively stored in the field of the branch target in fig. 4. When the instruction is output from the instruction memory shown in FIG. 2, the branch target address is obtained by reusing the above equation one.