阅读说明：本技术 芯片沟槽的制备方法与芯片的制备方法 (Preparation method of chip groove and preparation method of chip ) 是由 王文兵 史波 肖婷 于 2019-09-23 设计创作，主要内容包括：本发明涉及一种芯片沟槽的制备方法与芯片的制备方法,该芯片沟槽的制备方法包括：提供衬底,在所述衬底的表面预设沟槽区和包围所述沟槽区的非沟槽区；其中,所述非沟槽区包括预设的阻挡区和过渡区,所述过渡区包围所述沟槽区,所述阻挡区包围所述过渡区；在所述阻挡区对应的所述衬底的表面形成掩膜；在所述过渡区对应的所述衬底的表面且在所述掩膜的侧壁形成侧墙,所述侧墙形成围设所述沟槽区的刻蚀孔；对所述刻蚀孔处的衬底进行刻蚀形成沟槽。利用本发明的制备方法能够解决现有技术中利用光刻技术制备沟槽时由于曝光显影精度限制造成的无法减少沟槽尺寸的问题,达到减小沟槽尺寸的目的。(The invention relates to a preparation method of a chip groove and a preparation method of a chip, wherein the preparation method of the chip groove comprises the following steps: providing a substrate, and presetting a groove region and a non-groove region surrounding the groove region on the surface of the substrate; the non-groove area comprises a preset blocking area and a transition area, the transition area surrounds the groove area, and the blocking area surrounds the transition area; forming a mask on the surface of the substrate corresponding to the blocking area; forming a side wall on the surface of the substrate corresponding to the transition region and on the side wall of the mask, wherein the side wall forms an etching hole surrounding the groove region; and etching the substrate at the etching hole to form a groove. The preparation method can solve the problem that the size of the groove cannot be reduced due to the limitation of exposure and development precision when the groove is prepared by utilizing the photoetching technology in the prior art, and achieves the purpose of reducing the size of the groove.)

1. A preparation method of a chip groove is characterized by comprising the following steps:

providing a substrate, and presetting a groove region and a non-groove region surrounding the groove region on the surface of the substrate; the non-groove area comprises a preset blocking area and a transition area, the transition area surrounds the groove area, and the blocking area surrounds the transition area;

forming a mask on the surface of the substrate corresponding to the blocking area;

forming a side wall on the surface of the substrate corresponding to the transition region and on the side wall of the mask, and forming an etching hole surrounding the groove region;

and etching the substrate at the etching hole to form a groove.

2. The method according to claim 1, wherein the forming a mask on the surface of the substrate corresponding to the blocking region comprises:

forming a masking film on the surface of the substrate;

and etching to remove the masking films of the groove area and the transition area, forming the mask in the blocking area, and forming a through hole which simultaneously surrounds the transition area and the groove area.

3. The method of claim 2, wherein the sidewalls of the mask are perpendicular to the surface of the substrate.

4. The method according to claim 2, wherein forming a sidewall on the surface of the substrate corresponding to the transition region and on the sidewall of the mask, the sidewall forming an etching hole surrounding the trench region, comprises:

forming a side wall film on the surface of the mask and in the through hole;

and etching to remove the mask surface and the side wall film of the groove area, and forming the side wall in the transition area.

5. The method according to claim 4, wherein an extension distance of the sidewall spacer formed in a radial direction of the through hole is gradually increased from the mask to the substrate.

6. The method according to claim 4, wherein the sidewall film is formed as an LPTEOS film.

7. The method according to claim 4, wherein the etching is performed to remove the mask surface and the sidewall film in the trench region, and the forming of the sidewall in the transition region comprises:

and etching and removing the mask surface and the side wall film of the groove region by using a selective etching technology, and forming the side wall in the transition region.

8. A method for manufacturing a chip, comprising:

a trench is formed by the method of any one of claims 1 to 6.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a chip groove and a preparation method of a chip.

Background

Reducing the chip area is a common goal in the current chip development field, and in order to improve various performance indexes of the chip, a trench is often required to be prepared on a substrate. But as chip areas continue to decrease, the size of the trenches prepared accordingly also decreases. If the trench size is too small due to the limitation of the photolithography technique, the accuracy is insufficient at the time of exposure and development, and a large error exists. Therefore, it is not feasible to reduce the trench size by using the current method of directly using the mask.

Disclosure of Invention

The first objective of the present invention is to provide a method for manufacturing a chip trench, so as to solve the problem that the size of the trench cannot be reduced due to the limitation of exposure and development precision when the trench is manufactured by using the photolithography technique in the prior art.

The second objective of the present invention is to provide a method for manufacturing a chip, so as to reduce the area of the chip.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, the present invention provides a method for preparing a chip trench, including:

providing a substrate, and presetting a groove region and a non-groove region surrounding the groove region on the surface of the substrate; the non-groove area comprises a preset blocking area and a transition area, the transition area surrounds the groove area, and the blocking area surrounds the transition area;

forming a mask on the surface of the substrate corresponding to the blocking area;

forming a side wall on the surface of the substrate corresponding to the transition region and on the side wall of the mask, wherein the side wall forms an etching hole surrounding the groove region;

and etching the substrate at the etching hole to form a groove.

Further, forming a mask on the surface of the substrate corresponding to the blocking region, including:

forming a masking film on the surface of the substrate;

and etching to remove the masking films of the groove area and the transition area, forming the mask in the blocking area, and forming a through hole which simultaneously surrounds the transition area and the groove area.

Further, the sidewalls of the mask are perpendicular to the surface of the substrate.

Further, forming a sidewall on the surface of the substrate corresponding to the transition region and on the sidewall of the mask, where the sidewall forms an etching hole surrounding the trench region, including:

forming a side wall film on the surface of the mask and in the through hole;

and etching to remove the mask surface and the side wall film of the groove area, and forming the side wall in the transition area.

Further, in the direction from the mask to the substrate, the extending distance of the side wall of the formed side wall in the radial direction of the through hole is gradually increased.

Further, the formed side wall film is an LPTEOS film.

Further, etching to remove the mask surface and the sidewall film in the trench region, and forming the sidewall in the transition region, including:

and etching and removing the mask surface and the side wall film of the groove region by using a selective etching technology, and forming the side wall in the transition region.

In a second aspect, the present invention provides a method for manufacturing a chip, comprising:

the trench is prepared by the preparation method of the first aspect of the invention.

Compared with the prior art, the technical scheme provided by the invention has the following advantages:

according to the preparation method of the chip groove, the mask is prepared in the blocking area of the substrate, then the side wall is formed on the side wall of the mask, the formed side wall occupies a certain place on the substrate, and when the groove is prepared through etching, the side wall can serve as the mask, so that the purpose of reducing the size of the groove is achieved.

In the process, the substrate near the mask is covered by the side wall, so that the size of groove etching is reduced, the effective area of the chip is increased, and the actual area of the chip is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1-6 are schematic flow charts illustrating a method for fabricating a chip trench according to the present invention.

Icon: 1. a substrate; 11. a non-trench region; 111. a blocking region; 112. a transition zone; 12. a trench region; 2. a masking film; 21. masking; 3. a side wall film; 31. a side wall; 4. etching the hole; 5. and (4) a groove.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In a first aspect, the present invention provides a method for manufacturing a chip trench 5, referring to fig. 1 to 6, including:

providing a substrate 1, presetting a groove region 12 and a non-groove region 11 surrounding the groove region 12 on the surface of the substrate 1; the non-trench region 11 includes a blocking region 111 and a transition region 112, the transition region 112 surrounds the trench region 12, and the blocking region 111 surrounds the transition region 112;

forming a mask 21 on the surface of the substrate 1 corresponding to the blocking region 111;

forming a side wall 31 on the surface of the substrate 1 corresponding to the transition region 112 and on the side wall of the mask 21, wherein the side wall 31 forms an etching hole 4 surrounding the trench region 12;

and etching the substrate 1 at the etching hole 4 to form a groove 5.

The invention mainly aims at the problem of photoetching precision, and if the size of a relevant part is too small in the photoetching process, the exposure cannot be carried out. The preparation method of the chip trench 5 provided by the invention comprises the steps of firstly preparing the mask 21 in the blocking region 111 of the substrate 1, then forming the side wall 31 on the side wall of the mask 21, wherein the formed side wall 31 occupies a certain place on the substrate 1, and when the trench 5 is prepared by etching, the side wall 31 can be used as the mask 21 so as to achieve the purpose of reducing the size of the trench 5.

In the process, the substrate 1 near the mask 21 is covered by the side wall 31, so that the etching size of the groove 5 is reduced, the effective area of the chip is increased, and the actual area of the chip is reduced.

The substrate 1 in the present invention may be a silicon substrate 1, an epitaxial layer, such as an N-type epitaxial layer, may be formed on the surface of the substrate, and an initial oxide layer may also be formed on the surface of the epitaxial layer. That is, the manufacturing method provided by the present invention can be implemented in any step in the manufacturing process of the chip, and there is no limitation on the specific structure of the substrate 1. It can be understood that the blocking region 111, the transition region 112 and the trench region 12 in the present invention are in a layer-by-layer surrounding structure, the blocking region 111 surrounds the transition region 112 and the trench region 12, the transition region 112 surrounds the trench region 12, that is, the trench region 12 is located in the middle, and the transition region 112 and the blocking region 111 are sequentially disposed toward the periphery.

In addition, the sidewall 31 of the present invention is formed on the sidewall of the mask 21 corresponding to the transition region 112, the bottom of the sidewall 31 covers the surface of the substrate 1 corresponding to the transition region 112, a longitudinal side surface covers the sidewall of the mask 21, and the sidewall 31 surrounds the trench region 12 to form the etching hole 4. The sidewall 31 only needs to cover the substrate 1 in the transition region 112 and form the etching hole 4 surrounding the trench region 12, and the specific shape thereof is not particularly limited, and may be, for example, L-shaped, or ramp-shaped.

In some embodiments of the present invention, the forming a mask 21 on the surface of the substrate 1 corresponding to the blocking region 111 includes:

forming a masking film 2 on the surface of the substrate 1;

and etching to remove the masking film 2 in the groove region 12 and the transition region 112, forming the mask 21 in the blocking region 111, and forming a through hole enclosing the transition region 112 and the groove region 12 at the same time.

The mask film 2 may be formed on the surface of the substrate 1 by a chemical vapor deposition method, for example, and the formed mask film 2 may be a silicon oxide film, a silicon nitride film, or the like.

In the etching process of this embodiment, the masking film 2 on the surface of the substrate 1 corresponding to the trench region 12 and the transition region 112 is removed by etching, and the masking film 2 on the surface of the substrate 1 corresponding to the barrier region 111 is left, thereby forming the mask 21 on the surface of the substrate 1. Meanwhile, through holes are formed at portions corresponding to the transition region 112 and the trench region 12. The through hole penetrates the mask 21 in the thickness direction of the mask 21 with respect to the thickness of the mask 21. One side of the via contacts the substrate 1.

In some embodiments of the invention, the sidewalls of the mask 21 are perpendicular to the surface of the substrate 1. Where vertical is substantially vertical, it does not mean absolute vertical, e.g., the angle of inclination does not exceed ± 5 °.

In some embodiments of the present invention, forming a sidewall 31 on the surface of the substrate 1 corresponding to the transition region 112 and on the sidewall of the mask 21, where the sidewall 31 forms an etching hole 4 surrounding the trench region 12, includes:

forming a side wall film 3 on the surface of the mask 21 and in the through hole;

and etching to remove the surface of the mask 21 and the sidewall film 3 of the trench region 12, and forming the sidewall 31 in the transition region 112.

Similarly, in this embodiment, the sidewall film 3 may also be formed by chemical vapor deposition.

The formed sidewall film 3 is, for example, an LPTEOS film.

In some embodiments of the present invention, the etching to remove the surface of the mask 21 and the sidewall film 3 of the trench region 12 and form the sidewall 31 in the transition region 112 includes:

and etching and removing the surface of the mask 21 and the side wall film 3 of the trench region 12 by using a selective etching technology, and forming the side wall 31 in the transition region 112.

In some embodiments of the present invention, an extending distance of the sidewall 31 formed in the direction from the mask 21 to the substrate 1 in the radial direction of the through hole is gradually increased.

In this embodiment, the sidewall of the sidewall 31 surrounding the etching hole 4 is gradually extended into the etching hole 4 from the mask 21 to the substrate 1, and accordingly, the opening of the etching hole 4 is gradually reduced.

In one embodiment of the present invention, the method for preparing the chip trench 5 comprises the following steps:

step S101, providing a substrate 1, and presetting a groove region 12 and a non-groove region 11 surrounding the groove region 12 on the surface of the substrate 1; the non-trench region 11 includes a blocking region 111 and a transition region 112, the transition region 112 surrounds the trench region 12, and the blocking region 111 surrounds the transition region 112; as shown in fig. 1;

step S102, as shown in fig. 2, forming a masking film 2 on the surface of the substrate 1;

step S103, as shown in fig. 3, etching to remove the masking film 2 in the trench region 12 and the transition region 112, forming the mask 21 in the blocking region 111, and forming a through hole enclosing the transition region 112 and the trench region 12 at the same time; wherein the side wall of the mask 21 is formed perpendicular to the surface of the substrate 1;

step S104, as shown in FIG. 4, depositing LPTEOS film on the surface of the mask 21 and in the through hole;

step S105, as shown in fig. 5, removing the LPTEOS film on the surface of the mask 21 and the trench region 12 by etching using a selective etching technique, and forming the sidewall 31 in the transition region 112; the extending distance of the side wall of the formed side wall 31 in the radial direction of the through hole gradually increases from the mask 21 to the substrate 1;

step S106, as shown in fig. 6, etching the substrate 1 at the etching hole 4 to form a trench 5.

Before the trench 5 is etched, a layer of LPTEOS is grown on a mask 21 layer, namely a Hardmask layer, and then the LPTEOS is etched back, so that LPTEOS side walls 31 can be formed on the side surfaces of the Hardmask layer, and then when the trench 5 is etched on the substrate 1, the size of the trench 5 is reduced because the side walls 31 can cover a certain amount of the substrate 1, so that the effective area of a chip is increased, and the effect of reducing the area of the chip is further achieved.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.