阅读说明：本技术 一种大电流绝缘体上硅横向绝缘栅双极型晶体管 (Large-current silicon-on-insulator lateral insulated gate bipolar transistor ) 是由 田涛 张营 于 2019-12-03 设计创作，主要内容包括：本发明公开一种大电流绝缘体上硅横向绝缘栅双极型晶体管,属于半导体集成电路技术领域,包括NMOS管A、自偏置PMOS管B、NMOS管C,NMOS管A的N+漏区与NMOS管C的N+源区通过金属互连,NMOS管A的N+源区与PMOS管B的P+漏区相连,二者通过金属短接作为本发明器件的阴极,与上述阴极金属相连的多晶硅作为PMOS管B的栅极,传统硅横向绝缘栅双极型晶体管的阳极作为本发明器件的阳极,本发明与现有技术的绝缘体上硅横向绝缘栅双极型晶体管相比,在相等的导通压降情况下,具有更大的电流密度,更小的导通损耗和芯片面积,解决了现有技术中出现的问题。(The invention discloses a high-current silicon-on-insulator lateral insulated gate bipolar transistor, which belongs to the technical field of semiconductor integrated circuits and comprises an NMOS (N-channel metal oxide semiconductor) tube A and a self-biased PMOS tube B, NMOS tube C, wherein an N + drain region of the NMOS tube A and an N + source region of the NMOS tube C are interconnected through metal, the N + source region of the NMOS tube A is connected with a P + drain region of the PMOS tube B, the N + source region and the P + drain region of the PMOS tube B are used as cathodes of the device of the invention through metal short circuits, polycrystalline silicon connected with the cathode metal is used as a grid electrode of the PMOS tube B, and an anode of a traditional silicon lateral insulated gate bipolar transistor is used as an anode of the device of the invention.)

1. The utility model provides a horizontal insulated gate bipolar transistor of silicon on heavy current insulator, includes P type substrate (1), and the top of P type substrate (1) is equipped with in proper order and buries oxygen (2), N type epitaxial layer (3) and N type buffer layer (4), and the top of N type epitaxial layer (3) is equipped with positive pole, negative pole and the grid of transistor, its characterized in that: an NMOS tube A (25), a self-biased PMOS tube B (26) and an NMOS tube C (27) are arranged above the N-type epitaxial layer (3), a first P-type well region (7) and a second P-type well region (19) are arranged on one side above the N-type epitaxial layer (3), the first P-type well region (7) and the second P-type well region (19) are respectively close to an anode and a cathode of a transistor, the NMOS tube A (25) is arranged in the second P-type well region (19), the self-biased PMOS tube B (26) is bridged between the first P-type well region (7) and the second P-type well region (19), the NMOS tube C (27) is bridged between the first P-type well region (7) and the N-type epitaxial layer (3), the NMOS tube A (25) is connected with the self-biased PMOS tube B (26), the NMOS tube A (25) comprises an A tube N + drain region (20) and an A tube N + source region (18), and the self-biased PMOS tube B (26) comprises a B tube P + drain region (17), the NMOS tube C (27) comprises a C tube N + source region (9), an A tube N + drain region (20) is connected with the C tube N + source region (9), the A tube N + source region (18) is connected with a B tube P + drain region (17) and then is short-circuited and led out to serve as a cathode of a transistor through cathode metal (16), an N-type buffer layer (4) is arranged on one side of an N-type epitaxial layer (3), a P + anode region (5) is arranged on one side, away from the cathode direction of the transistor, of the upper layer of the N-type buffer layer (4), the C tube N + source region (9), a first P-type well region (7) and the N-type epitaxial layer (3) jointly form an NPN-type parasitic triode, and the first P-type well region (7), the N-type epitaxial layer (3) and the P + anode region (5) jointly.

2. A high current soi bipolar transistor as claimed in claim 1 wherein: an anode metal (6) is arranged above the P + anode region (5), and the anode metal (6) is led out to be used as the anode of the transistor.

3. A high current soi bipolar transistor as claimed in claim 1 wherein: the NMOS tube A (25) further comprises a tube A polysilicon gate (22), the NMOS tube C (27) further comprises a tube C polysilicon gate (11), and the tube A polysilicon gate (22) is connected with the tube C polysilicon gate (11) and then serves as a gate of the transistor.

4. A high current soi bipolar transistor as claimed in claim 3 wherein: the NMOS tube A (25) further comprises an A tube gate oxide layer (23), the lower surface of the A tube gate oxide layer (23) is in contact with the upper surfaces of an A tube N + drain region (20) and an A tube N + source region (18) respectively, an A tube polycrystalline silicon gate (22) is located above the A tube gate oxide layer (23), an A tube metal (21) is arranged above the A tube N + drain region (20), and the A tube metal (21), the A tube polycrystalline silicon gate (22) and the cathode metal (16) are not connected with each other.

5. A high current SOI lateral insulated gate bipolar transistor according to claim 4, wherein: the self-bias PMOS tube B (26) further comprises a tube B polysilicon gate (14), and the tube B polysilicon gate (14) is connected with the cathode metal (16).

6. A high current SOI lateral insulated gate bipolar transistor according to claim 5, wherein: the self-bias PMOS tube B (26) further comprises a tube B P + source region (13) and a tube B gate oxide layer (15), the lower surface of the tube B gate oxide layer (15) is in contact with the upper surfaces of a tube B P + drain region (17) and the tube B P + source region (13) respectively, a tube B polysilicon gate (14) is located above the tube B gate oxide layer (15), cathode metal (16) is located above the tube B P + drain region (17), and a tube A N + source region (18) and the tube B P + drain region (17) are located on two sides below the cathode metal (16) respectively.

7. A high current SOI lateral insulated gate bipolar transistor according to claim 6, wherein: the NMOS tube C (27) further comprises a tube C gate oxide layer (10), and a tube C polysilicon gate (11) is located above the tube C gate oxide layer (10).

8. A high current soi bipolar transistor as claimed in claim 7 wherein: the transistor C is characterized in that a transistor C N + source region (9) is adjacent to a transistor B P + source region (13), a transistor C metal (12) is arranged above the transistor C N + source region (9), a transistor C polysilicon gate (11), the transistor C metal (12) and a transistor B polysilicon gate (14) are not connected with each other, and the transistor A metal (21) is connected with the transistor C metal (12).

9. A high current SOI lateral insulated gate bipolar transistor according to claim 6, wherein: a first P-type buried layer (8) is arranged in the first P-type well region (7), and a B tube P + source region (13) and a C tube N + source region (9) are arranged above the first P-type buried layer (8).

10. A high current soi bipolar transistor as claimed in claim 1 wherein: and a second P-type buried layer (24) is arranged in the second P-type well region (19), and the B tube P + drain region (17), the A tube N + source region (18) and the A tube N + drain region (20) are arranged above the second P-type buried layer (24).

Technical Field

The invention relates to a high-current silicon-on-insulator lateral insulated gate bipolar transistor, belonging to the technical field of semiconductor integrated circuits.

Background

An Insulated Gate Bipolar Transistor (IGBT) is a composite power device formed by combining and evolving an MOS (metal oxide semiconductor) gate device structure and a bipolar transistor structure, has the characteristics of an MOS (metal oxide semiconductor) transistor and a bipolar transistor, has good compromise relationship between on-state current and switching loss, and has a transverse structure which is widely applied to a power integrated circuit; for example, the Chinese patent application number is: 201510998522.X, discloses a lateral insulated gate bipolar transistor, which is additionally provided with an electric field strengthening unit on the basis of a LIGBT device in the prior art, wherein the unit strengthening unit consists of an accelerating grid, an accelerating grid heavily doped region, a high-resistance conductive region, a grounding doped region and a grounding electrode, the electric field strengthening unit is used for generating an electric field pointing to the lower surface of the electric field strengthening unit from an anode, the electric field strengthening unit is isolated from a drift region through an insulating medium, and the structure can improve the current density, but has the problems of larger leakage current and additional driving circuit. For another example, in the document "amplified structured semiconductor-assisted regulated SOI-LIGBT with Low On-state Voltage", a LIGBT device with self-modulated conductance and Low On-state Voltage is proposed, but the device needs to be made with an isolation dielectric region and a complicated trench etching process is required.

In summary, how to obtain an igbt with a larger current density, smaller conduction loss and smaller chip area under the condition of equal conduction voltage drop becomes a technical problem to be solved urgently.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a high-current silicon-on-insulator lateral insulated gate bipolar transistor, which solves the problems in the prior art.

The invention relates to a silicon transverse insulated gate bipolar transistor on a high-current insulator, which comprises a P-type substrate, wherein buried oxide, an N-type epitaxial layer and an N-type buffer layer are sequentially arranged above the P-type substrate, an anode, a cathode and a grid electrode of the transistor are arranged above the N-type epitaxial layer, an NMOS (N-channel metal oxide semiconductor) tube A, a self-biased PMOS tube B and an NMOS tube C are arranged above the N-type epitaxial layer, a first P-type well region and a second P-type well region are arranged on one side above the N-type epitaxial layer and respectively close to the anode and the cathode of the transistor, the NMOS tube A is arranged in the second P-type well region, the self-biased PMOS tube B is bridged between the first P-type well region and the second P-type well region, the NMOS tube C is bridged between the first P-type epitaxial layer and the N-type epitaxial layer, the NMOS tube A is connected with the self-biased PMOS tube B, and comprises an A tube N + drain region and an A tube N, the self-bias PMOS tube B comprises a tube B P + drain region, the NMOS tube C comprises a tube C N + source region, the tube A N + drain region is interconnected with the tube C N + source region, the tube A N + source region is connected with the tube B P + drain region and then is led out as a cathode of a transistor through a cathode metal short circuit, the N-type buffer layer is arranged on one side of the N-type epitaxial layer, a P + anode region is arranged on one side, away from the cathode direction of the transistor, of the upper layer of the N-type buffer layer, the tube C N + source region, the first P-type well region and the N-type epitaxial layer jointly form an NPN-type parasitic triode, and the first P-type well region, the N-type epitaxial layer and the P + anode.

The cathode region of the transistor is different from the cathode region of the silicon transverse insulated gate bipolar transistor in the prior art and is divided into an NMOS tube A and a self-biased PMOS tube B, NMOS C, and the tube A, the tube B and the tube C are compactly distributed. The grid of the NMOS tube A and the grid of the NMOS tube C are interconnected to be used as the grid (Gate) of the device, the N + drain region of the NMOS tube A is interconnected with the N + source region of the NMOS tube C, the N + source region of the NMOS tube A is connected with the P + drain region of the self-bias PMOS tube B, the N + drain region of the NMOS tube A and the P + drain region of the self-bias PMOS tube B are in short circuit connection through Cathode metal to be used as the Cathode (Cathode) of the device, polycrystalline silicon connected with the Cathode metal is used as the grid of the self-bias PMOS tube B, and the Anode of the silicon transverse insulated Gate bipolar transistor in the prior.

Furthermore, anode metal is arranged above the P + anode region, and the anode metal is led out to be used as an anode of the transistor.

Furthermore, the NMOS tube A also comprises a tube A polysilicon gate, the NMOS tube C also comprises a tube C polysilicon gate, and the tube A polysilicon gate is connected with the tube C polysilicon gate and then led out to serve as a gate of the transistor.

Furthermore, the NMOS tube A also comprises a tube A gate oxide layer, the lower surface of the tube A gate oxide layer is respectively contacted with the N + drain region of the tube A and the upper surface of the N + source region of the tube A, the polysilicon gate of the tube A is positioned above the tube A gate oxide layer, tube A metal is arranged above the N + drain region of the tube A, and the tube A metal, the polysilicon gate of the tube A and the cathode metal are not connected with each other.

Further, the self-bias PMOS tube B also comprises a tube B polysilicon gate, and the tube B polysilicon gate is connected with cathode metal.

Furthermore, the self-bias PMOS tube B also comprises a tube B P + source region and a tube B gate oxide layer, the lower surface of the tube B gate oxide layer is respectively contacted with the upper surfaces of the tube B P + drain region and the tube B P + source region, the tube B polysilicon gate is positioned above the tube B gate oxide layer, the cathode metal is positioned above the tube B P + drain region, and the tube A N + source region and the tube B P + drain region are respectively positioned on two sides below the cathode metal.

Furthermore, the NMOS transistor C also comprises a transistor C gate oxide layer, and a transistor C polysilicon gate is positioned above the transistor C gate oxide layer.

Furthermore, a C tube N + source region is adjacent to a B tube P + source region, C tube metal is arranged above the C tube N + source region, a C tube polycrystalline silicon grid, the C tube metal and a B tube polycrystalline silicon grid are not connected with each other, and the A tube metal and the C tube metal are connected with each other.

Furthermore, a first P-type buried layer is arranged in the first P-type well region, and a P + source region of the B tube and an N + source region of the C tube are arranged above the first P-type buried layer.

Furthermore, a second P-type buried layer is arranged in the second P-type well region, and the P + drain region of the B tube, the N + source region of the A tube and the N + drain region of the A tube are arranged above the second P-type buried layer.

Compared with the prior art, the invention has the following beneficial effects:

compared with the silicon-on-insulator lateral insulated gate bipolar transistor in the prior art, the high-current silicon-on-insulator lateral insulated gate bipolar transistor has larger current density, smaller conduction loss and smaller chip area under the condition of equal conduction voltage drop, when the anode voltage is 2.59V, the current density of the device is increased by 47% compared with the device in the prior art, and when the anode voltage is 20V, the current density of the device is increased by 103% compared with the device in the prior art. It is apparent that the device of the present invention utilizes latch-up to increase current density at lower voltages while maintaining a greater current density in the saturation region. Meanwhile, a complex grooving process is not needed, and the problems in the prior art are solved.

Drawings

FIG. 1 is a block diagram of a prior art SOI lateral insulated gate bipolar transistor;

FIG. 2 is a block diagram of a high current SOI lateral insulated gate bipolar transistor in accordance with an embodiment of the present invention, shown in FIG. 1;

FIG. 3 is a block diagram of a high current SOI lateral IGBT of the present invention, shown in FIG. 2;

FIG. 4 is a simplified equivalent circuit diagram of a prior art silicon lateral insulated gate bipolar transistor and a current flow diagram in a forward conducting state thereof according to an embodiment of the present invention;

FIG. 5 is an equivalent simplified circuit diagram of a high-current SOI lateral insulated gate bipolar transistor operating in a linear region and a current flow diagram thereof according to an embodiment of the present invention;

FIG. 6 is a current flow diagram of a cathode region of a high-current SOI lateral insulated gate bipolar transistor in a saturation region according to an embodiment of the present invention;

FIG. 7 is a current flow diagram of the cathode region when the high current SOI lateral insulated gate bipolar transistor enters the latch-up state at a lower voltage according to the embodiment of the present invention;

FIG. 8 is a current flow diagram of the cathode region when the high-current SOI lateral insulated gate bipolar transistor enters a saturation state after the anode voltage continues to increase in the embodiment of the present invention;

FIG. 9 is a graph comparing the breakdown voltage of a high current SOI lateral insulated gate bipolar transistor with a LIGBT device of the prior art in an embodiment of the present invention;

FIG. 10 is a graph comparing the forward conduction characteristics of a high current SOI lateral insulated gate bipolar transistor with a LIGBT device of the prior art when the anode voltage is 2.59V in an embodiment of the present invention;

FIG. 11 is a comparison graph of the forward conduction characteristics of a high current SOI lateral IGBT and a LIGBT device in the prior art when the anode voltage is 20V in the embodiment of the present invention;

in the figure: 1. a P-type substrate; 2. burying oxygen; 3. an N-type epitaxial layer; 4. an N-type buffer layer; 5. a P + anode region; 6. an anode metal; 7. a first P-type well region; 8. a first P-type buried layer; 9. a C tube N + source region; 10. c, a tube gate oxide layer; 11. c, a polysilicon grid; 12. c, tube metal; 13. b pipe P + source area; 14. b, a polysilicon gate; 15. b, a tube gate oxide layer; 16. a cathode metal; 17. a pipe B is a P + drain region; 18. a tube A N + source region; 19. a second P-type well region; 20. an N + drain region of the A tube; 21. a, tube metal; 22. a, a polysilicon gate; 23. a, a tube gate oxide layer; 24. a second P-type buried layer; 25. an NMOS tube A; 26. a self-biased PMOS tube B; 27. and an NMOS tube C.

Detailed Description

The invention is further illustrated by the following figures and examples: