阅读说明：本技术 基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管及制备方法 (Tin oxide-based thin film transistor based on plasma enhanced atomic layer deposition grid insulation layer and preparation method ) 是由 宁洪龙 刘贤哲 姚日晖 袁炜健 张旭 张观广 梁志豪 梁宏富 邱斌 彭俊彪 于 2019-10-21 设计创作，主要内容包括：本发明属于薄膜晶体管技术领域,涉及一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管,包括依次设置的：衬底、栅极、栅极绝缘层、有源层和源漏电极,其中：栅极绝缘层是由等离子体增强原子层沉积制备的氧化铝薄膜,有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜。本发明的氧化锡基薄膜晶体管采用等离子体增强原子层沉积法制备高介电常数的氧化铝作为栅极绝缘层,并且使用非晶硅掺杂氧化锡半导体材料作为有源层材料,降低了有源层/栅极绝缘层界面缺陷态和器件的开启电压,显著地提高了器件迁移率和稳定性。本发明还提供一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法。(The invention belongs to the technical field of thin film transistors, and relates to a tin oxide-based thin film transistor based on a plasma enhanced atomic layer deposition grid insulation layer, which comprises the following components in sequence: substrate, grid, gate insulation layer, active layer and source-drain electrode, wherein: the gate insulating layer is an alumina film prepared by plasma enhanced atomic layer deposition, and the active layer is a silicon-doped tin oxide film prepared by magnetron sputtering deposition. The tin oxide-based thin film transistor adopts a plasma enhanced atomic layer deposition method to prepare aluminum oxide with high dielectric constant as a gate insulating layer, and uses an amorphous silicon doped tin oxide semiconductor material as an active layer material, so that the interface defect state of the active layer/gate insulating layer and the starting voltage of a device are reduced, and the mobility and the stability of the device are remarkably improved. The invention also provides a preparation method of the tin oxide-based thin film transistor based on the plasma enhanced atomic layer deposition grid insulation layer.)

1. Tin oxide base thin film transistor based on plasma enhanced atomic layer deposition grid insulation layer, its characterized in that, including setting gradually: substrate, grid, gate insulation layer, active layer and source-drain electrode, wherein: the gate insulating layer is an alumina film prepared by plasma enhanced atomic layer deposition, and the active layer is a silicon-doped tin oxide film prepared by magnetron sputtering deposition.

2. The tin oxide-based thin film transistor of claim 1, wherein the gate insulating layer is made of an aluminum oxide material, the aluminum material is trimethylaluminum, the reaction gas is oxygen, and the reaction temperature is 80-100 ℃.

3. The tin oxide-based thin film transistor of claim 1, wherein the semiconductor material of the active layer is silicon-doped tin oxide (SiSnO, SiO) ₂The doping weight is 3-5 wt%; the thickness of the active layer is 5-10 nm.

4. The tin oxide-based thin film transistor according to claim 1, wherein the active layer is formed by a sputtering process with a sputtering power of 50 to 110W, an operating pressure of 2 to 5mtorr, and a sputtering gas of a mixture of argon and oxygen.

5. The tin oxide-based thin film transistor of claim 1, wherein the substrate comprises: a glass substrate or a flexible substrate; the flexible substrate comprises PI, PEN or PET.

6. The tin oxide-based thin film transistor according to claim 1, wherein the source-drain electrode material comprises: al, Mo, Cu or ITO.

7. The preparation method of the tin oxide-based thin film transistor based on the gate insulation layer of the plasma enhanced atomic layer deposition is characterized by comprising the following steps of:

s1, preparing a conductive film on the substrate by direct current magnetron sputtering at room temperature and patterning the conductive film to form a grid;

s2, growing an insulating film on the grid electrode by using a plasma enhanced atomic layer deposition technology to serve as a grid electrode insulating layer;

s3, carrying out heat treatment on the substrate on a hot table;

s4, preparing an amorphous SiSnO film on the gate insulating layer through radio frequency magnetron sputtering and patterning the amorphous SiSnO film to serve as an active layer;

and S5, preparing a conductive film on the active layer through direct current magnetron sputtering deposition and patterning the conductive film to be used as a source/drain electrode, and obtaining the tin oxide-based thin film transistor based on the plasma enhanced atomic layer deposition gate insulating layer.

8. The method according to claim 7, wherein the gate insulating layer in step S2 is made of an aluminum oxide material, the aluminum material is trimethylaluminum, the reaction gas is oxygen, and the reaction temperature is 80-100 ℃.

9. The method according to claim 7, wherein the heat treatment in step S3 is carried out in air at a heating temperature of 150-250 ℃ for an annealing time of 30-60 min.

10. The method according to claim 7, wherein the active layer is prepared by sputtering with a sputtering power of 50-110W and a working pressure of 2-5 mtorr in step S4, and the sputtering gas is argon and oxygen mixture; and after the active layer is prepared, carrying out heat treatment, wherein the annealing temperature is 250-350 ℃, and the annealing time is 30-60 min.

Technical Field

The invention belongs to the technical field of thin film transistors, and relates to a tin oxide-based thin film transistor based on a plasma enhanced atomic layer deposition grid insulation layer and a preparation method thereof.

Background

At present, the flat panel display technology is rapidly developed, and a large-size, high-resolution, high-refresh-rate display becomes the mainstream. The core technology of the flat panel display industry is a Thin Film Transistor (TFT) backboard technology, and the improvement of the performance of the TFT and the reduction of the production cost are very important. In a conventional TFT, silicon oxide or silicon nitride is used as a gate insulating layer. Due to their low dielectric constant (about 3.9), small capacitance, generally results in small device mobility and low "on" current. The insulating layer material with high dielectric constant has the advantages of high dielectric constant, relatively low leakage current, wide band gap and the like, can reduce the working voltage of the device, and obviously improves the performance of the device.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a tin oxide-based thin film transistor based on a plasma enhanced atomic layer deposition grid insulating layer.

The invention also provides a preparation method of the tin oxide-based thin film transistor based on the plasma enhanced atomic layer deposition grid insulation layer.

The invention is realized by adopting the following technical scheme:

tin oxide base thin film transistor based on plasma enhanced atomic layer deposition grid insulation layer, including setting gradually: substrate, grid, gate insulation layer, active layer and source-drain electrode, wherein: the gate insulating layer is an alumina film prepared by plasma enhanced atomic layer deposition, and the active layer is a silicon-doped tin oxide film prepared by magnetron sputtering deposition.

Furthermore, the gate insulating layer is made of an aluminum oxide material, the aluminum material is trimethylaluminum, the reaction gas is oxygen, and the reaction temperature is 80-100 ℃.

Furthermore, the semiconductor material of the active layer is silicon-doped tin oxide SiSnO, SiO ₂The doping weight is 3-5 wt%; the thickness of the active layer is 5-10 nm.

Preferably, the preparation process of the active layer comprises the steps of sputtering with the power of 50-110W, working pressure of 2-5 mtorr and the sputtering gas of argon and oxygen mixed.

Preferably, the substrate comprises: a glass substrate or a flexible substrate; the flexible substrate comprises PI, PEN or PET.

Preferably, the source-drain electrode material includes: al, Mo, Cu or ITO.

The preparation method of the tin oxide-based thin film transistor based on the gate insulation layer of the plasma enhanced atomic layer deposition comprises the following steps:

s1, preparing a conductive film on the substrate by direct current magnetron sputtering at room temperature and patterning the conductive film to form a grid;

s2, growing an insulating film on the grid electrode by using a plasma enhanced atomic layer deposition technology to serve as a grid electrode insulating layer;

s3, carrying out heat treatment on the substrate on a hot table;

s4, preparing an amorphous SiSnO film on the gate insulating layer through radio frequency magnetron sputtering and patterning the amorphous SiSnO film to serve as an active layer;

and S5, preparing a conductive film on the active layer through direct current magnetron sputtering deposition and patterning the conductive film to be used as a source/drain electrode, and obtaining the tin oxide-based thin film transistor based on the plasma enhanced atomic layer deposition gate insulating layer.

Further, in the step S2, the gate insulating layer is made of an aluminum oxide material, the aluminum material is trimethylaluminum, the reaction gas is oxygen, and the reaction temperature is 80 to 100 ℃.

Preferably, the heat treatment condition in step S3 is in air, the heating temperature is 150 to 250 ℃, and the annealing time is 30 to 60 min.

Further, in the step S4, the preparation process of the active layer includes that the sputtering power is 50-110W, the working pressure is 2-5 mtorr, and the sputtering gas is argon and oxygen mixed; and after the active layer is prepared, carrying out heat treatment, wherein the annealing temperature is 250-350 ℃, and the annealing time is 30-60 min.

The preparation method and the obtained thin film transistor have the following advantages and beneficial effects:

(1) the high-dielectric-constant aluminum oxide is prepared by adopting a plasma enhanced atomic layer deposition method to serve as a gate insulating layer, and the amorphous silicon doped tin oxide semiconductor material is used as an active layer material, so that the interface defect state of the active layer/gate insulating layer and the starting voltage of a device are reduced, and the mobility and the stability of the device are remarkably improved.

(2) The low-cost environment-friendly silicon-doped tin oxide semiconductor material is used as an active layer material, the high-dielectric constant aluminum oxide is used as a gate insulation layer, the preparation process is simple, the cost is low, the high-performance thin film transistor is obtained, and the flexible preparation of the thin film transistor is facilitated.

Drawings

Fig. 1 is a schematic diagram of a metal-insulator-metal structure according to an embodiment of the invention. Wherein 11 is Al, 12 is AlOx, and 13 is Al.

FIG. 2 is a graph of capacitance versus frequency for different thicknesses of alumina in one embodiment of the present invention. Wherein, the sample is annealed at 350 ℃ for 30 min; curves 21, 22 and 23 correspond to alumina thicknesses of 50, 100 and 200nm, respectively; the frequency varies from 1k to 1 MHz.

FIG. 3 is a current-voltage curve for different thicknesses of alumina in one embodiment of the present invention. Wherein, the sample is annealed at 350 ℃ for 30 min; curves 31, 32 and 33 correspond to alumina thicknesses of 50, 100 and 200nm, respectively; the voltage variation is from 0 to-50V.

FIG. 4 is a graph of the transfer characteristics of a SiSnO-TFT in one embodiment of the present invention. Wherein SiO is ₂The doping weight is 5 wt%; curves 41 and 42 are atomic layer deposited alumina at 100 and 200nm, respectively; the active layer is made of SiSnO and is 5nm thick; the test condition is a source/drain voltage V _DS30.1V, gate scan voltage V _GS＝-30～30V。

FIG. 5 is a graph illustrating the bias stability of a SiSnO-TFT in one embodiment of the present invention. Wherein the thickness of the aluminum oxide is 100 nm; the active layer is made of SiSnO, and the thickness of the active layer is 5 nm; curves 51, 52, 53, 54 and 55 correspond to bias times of 0, 900, 1800, 2700 and 3600s, respectively; applying a bias condition of V _GS＝10V，V _DS0V; the test condition is a source/drain voltage V _DS30.1V, gate scan voltage V _GS＝-30～30V。

Detailed Description

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.

A tin oxide-based thin film transistor based on a gate insulating layer of plasma enhanced atomic layer deposition (PECVD) comprises the following components in sequence: substrate, grid, gate insulation layer, active layer and source-drain electrode, wherein: the gate insulating layer is an alumina film prepared by plasma enhanced atomic layer deposition, and the active layer is a silicon-doped tin oxide film prepared by magnetron sputtering deposition.

The invention introduces high-quality alumina as the gate insulation layer, improves the quality of the gate insulation layer/active layer interface, and effectively improves the mobility and stability of the device. The aluminum oxide film is prepared through atomic layer deposition, the material of the gate insulating layer is an aluminum oxide material, the aluminum material is trimethylaluminum, the reaction gas is oxygen, the reaction temperature is 80-100 ℃, and the thickness of the film (the gate insulating layer) is 50-200 nm.

The existing atomic layer deposition process usually needs high temperature heating to provide reaction energy, and meanwhile, the high reaction temperature can cause decomposition or desorption of reactants (metal organic compounds), so that the reaction is insufficient, and the impurity content in the deposited film is high. The process for manufacturing the gate insulating layer utilizes plasma to provide reaction energy, high-temperature heating is not needed, decomposition and desorption of reactants are effectively avoided, and smooth film deposition is ensured. The process has the advantages of low deposition temperature, capability of fully removing redundant reactants and products, good film uniformity and low impurity content.

The active layer is a silicon-doped tin oxide film prepared by magnetron sputtering deposition, and the semiconductor material of the active layer is silicon-doped tin oxide (SiSnO), wherein SiO ₂The doping weight is 3-5 wt%; the thickness of the active layer is 5-10 nm.

The active layer material of the invention does not contain indium (In), so the material has the advantages of low cost, no toxicity, no pollution, environmental protection and the like. Meanwhile, the material has strong acid resistance, does not need the protection of an etching barrier layer, and can effectively reduce the production cost.

The substrate includes: a glass substrate or a flexible substrate; the flexible substrate comprises PI, PEN or PET.

The source-drain electrode material includes: al, Mo, Cu or ITO.

A tin oxide-based thin film transistor preparation method based on a plasma enhanced atomic layer deposition grid insulation layer comprises the following steps:

s1, preparing a conductive film on the substrate by direct current magnetron sputtering at room temperature and patterning the conductive film to form a grid;

s2, growing an insulating film on the grid electrode by using a plasma enhanced atomic layer deposition technology to serve as a grid electrode insulating layer;

the gate insulating layer is made of an aluminum oxide material, wherein the aluminum material is trimethylaluminum, the reaction gas is oxygen, the reaction temperature is 80-100 ℃, and the film thickness is 50-200 nm.

S3, carrying out heat treatment on the substrate on a hot table;

the heat treatment condition is that the heating temperature is 150-250 ℃ in air, and the annealing time is 30-60 min.

S4, preparing an amorphous SiSnO film on the gate insulating layer through radio frequency magnetron sputtering and patterning the amorphous SiSnO film to serve as an active layer;

the preparation process of the active layer comprises the steps of sputtering with the power of 50-110W, working pressure of 2-5 mtorr and the sputtering gas of argon and oxygen mixed.

And after the active layer is prepared, carrying out heat treatment, wherein the annealing temperature is 250-350 ℃, and the annealing time is 30-60 min.

And S5, preparing a conductive film on the active layer through direct current magnetron sputtering deposition and patterning the conductive film to be used as a source/drain electrode, and obtaining the tin oxide-based thin film transistor based on the plasma enhanced atomic layer deposition gate insulating layer.

The present invention will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of metal-insulator-metal for characterizing the insulating layer and testing the capacitance, dielectric constant, breakdown voltage and leakage current of the insulating layer. Fig. 2 and 3 are capacitance-frequency and current-voltage curves, respectively. Wherein the insulating layers have a thickness of 50, 100 and 200nm, respectively.

From the above results, it can be seen that the aluminum oxides with different thicknesses have higher capacitance frequency response, and can well avoid the delay or distortion of the electrical signal. 50. The capacitances of 100 and 200nm alumina were 206.37, 94.11 and 48.41nF/cm, respectively ². 50. The dielectric constants of 100 and 200nm alumina are 11.66, 10.63 and 10.94, respectively. The breakdown voltage resistance of the atomic layer deposited alumina is more than 50V and the leakage current is less than 10 ^-9A。

Fig. 4 is a graph of the transfer characteristics of a silicon doped tin oxide thin film transistor. Wherein the capacitance sizes of the 100nm alumina and the 200nm alumina are respectively 94.11 nF/cm and 56.48nF/cm ². The turn-on voltage of a 100nm alumina gate insulator device was-5V and the "on" current was 1.8X 10 ^-4A, the mobility of the device is 9.75cm ²Vs, subthreshold swing of 0.71V/decade; the turn-on voltage of a 200nm alumina gate insulator device was-10V and the "on" current was 5.05X 10 ^-5A, the mobility of the device is 2.81cm ²Vs, subthreshold swing 1.27V/decade.

From the above results, it can be seen that the device with the gate insulating layer thickness of 100nm has higher device performance: the gate-on-state current is high, the mobility is high, and the sub-threshold swing is small, so that under the condition of low gate voltage, more carriers can be accumulated at the interface of the semiconductor and the insulating layer to form a conductive channel, and the energy consumption can be effectively reduced; meanwhile, a better contact interface is formed between the grid insulation layer and the active layer, so that the scattering of current carriers at the interface is reduced, and larger on-state current and device mobility are obtained.

Fig. 5 is a graph of the transfer characteristics of a silicon doped tin oxide thin film transistor under bias stability. Wherein the bias condition is applied as V _GS＝10V，V _DS0V; the transfer curve has little movement and the turn-on voltage has only moved 0.05V in the forward direction.

From the above results, it can be seen that the stability of the thin film transistor can be improved by using the plasma enhanced atomic layer deposited alumina as the gate insulating layer.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.