Inverse doherty power amplifier with large RF fraction and instantaneous bandwidth
阅读说明:本技术 具有大rf分数和瞬时带宽的反向多尔蒂功率放大器 (Inverse doherty power amplifier with large RF fraction and instantaneous bandwidth ) 是由 杰拉德·布伊斯 克里斯蒂安·卡苏 于 2017-04-24 设计创作,主要内容包括:描述了用于操作在千兆赫兹频率下的反向多尔蒂放大器的装置和方法。当基于主放大器和峰值放大器的特征以及放大器的非对称因子来设计反向多尔蒂放大器的输出网络中的阻抗匹配部件和阻抗逆变器时,可以在常规多尔蒂放大器配置上增加RF分数带宽和信号带宽。(Apparatus and methods for operating an inverse doherty amplifier at gigahertz frequencies are described. When the impedance matching components and impedance inverters in the output network of the inverted doherty amplifier are designed based on the characteristics of the main and peak amplifiers and the asymmetry factor of the amplifiers, the RF fractional bandwidth and signal bandwidth can be increased over conventional doherty amplifier configurations.)
1. An inverted doherty amplifier comprising:
a main amplifier in the first circuit branch;
a peak amplifier in the second circuit branch and arranged to operate as a class C amplifier;
a combining node located at a position where a first portion after the main amplifier in the first circuit branch is connected with a second portion after the peak amplifier in the second circuit branch;
a first impedance matching element connected between the main amplifier and the combining node in a first portion of the first circuit branch, wherein the first impedance matching component matches the input impedance Z optConversion to output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load of the main amplifier that provides maximum power transfer from the main amplifier when connected to the output of the main amplifier, R LIs the resistance of a load driven by the inverse doherty amplifier, and α is the asymmetry factor of the inverse doherty amplifier, where the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier, and
an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
2. The inverse doherty amplifier of claim 1 wherein Z optmFrom a real resistance R optmComposition and resistance value R combWithin 20% of the expression in claim 1.
3. The inverse doherty amplifier according to claim 1 or 2, further comprising: an impedance inverter connected in the second circuit branch between the peak amplifier and a combining node, wherein the impedance inverter comprises a microstrip transmission line.
4. The inverse doherty amplifier of claim 3 wherein the characteristic impedance of the microstrip transmission line is approximately equal to the impedance at the combining node multiplied by (1+ α)/α.
5. The inverse doherty amplifier of claim 3 or 4, wherein the impedance inverter adds a phase delay of about 270 degrees.
6. The inverse doherty amplifier of any one of claims 1 to 4, wherein the RF fractional bandwidth of the inverse doherty amplifier, defined by the S11 scattering parameter at the output of the main amplifier, is 7% to 25% when the asymmetry factor of the inverse doherty amplifier is 1, looking towards the combining node and the peak amplifier is in the non-amplifying state.
7. An inverse doherty amplifier according to any of claims 1 to 6 and wherein said combining node is arranged to be directly connected to a load having an impedance equal to approximately 50 ohms.
8. The inverse doherty amplifier of any one of claims 3 to 7, further comprising:
a coupler arranged to split an input signal into a first signal provided to a first circuit branch and a second signal provided to a second circuit branch, and to add to the first signal a first phase delay having more than 80 degrees relative to the second signal; and
a second impedance matching block connected between the peak amplifier and the impedance inverter in the second portion of the second circuit branch.
9. The inverse doherty amplifier of claim 8, further comprising:
a first shunt inductor and a first capacitor in the first impedance matching section, which are connected in series between an output of the main amplifier and a first reference potential; and
a second shunt inductor and a second capacitor in the second impedance matching block, which are connected in series between the output of the peak amplifier and a second reference potential.
10. The inverse doherty amplifier of claim 9, further comprising:
a first bias terminal connected to the first shunt inductor and arranged to provide a first bias path for applying a first bias voltage to the main amplifier via the first shunt inductor; and
a second bias terminal connected to the second shunt inductor and arranged to provide a second bias path for applying a second bias voltage to the peaking amplifier via the second shunt inductor.
11. An inverse doherty amplifier according to claim 9 or 10 and wherein the value of said first capacitor is from 100 picofarads to 10 microfarads.
12. The inverse doherty amplifier of any one of claims 8 to 11, wherein the impedance inverter increases the second phase delay by approximately equal to the first phase delay.
13. The inverse doherty amplifier of any one of claims 8-12, wherein the impedance inverter increases the second phase delay by an odd multiple equal to approximately 90 degrees.
14. The inverse doherty amplifier of any one of claims 8 to 13, wherein the first and second impedance matching components each provide a phase delay of approximately 90 degrees.
15. The inverse doherty amplifier of any one of claims 1 to 14 wherein the main and peak amplifiers comprise gallium nitride transistors.
16. A method of operating an inverse doherty amplifier, the method comprising:
receiving an input signal;
dividing an input signal;
providing a first portion of an input signal to a first circuit branch comprising a main amplifier;
providing a second portion of the input signal to a second circuit branch comprising a peak amplifier operating as a class C amplifier;
the input impedance Z is coupled to the main amplifier and the combining node by means of a first impedance matching block connected between the main amplifier and the combining node in a first part of the first circuit branch optConversion to an output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load of the main amplifier that provides maximum power transfer from the main amplifier when connected to the output of the main amplifier, R LIs the resistance of a load driven by the inverse doherty amplifier, and α is the asymmetry factor of the inverse doherty amplifier, wherein the asymmetry factorThe sub is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier;
combining at a combining node a signal from after the main amplifier in the first circuit branch and a signal after the peak amplifier in the second circuit branch; and
providing an output signal from the combining node to an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
17. The method of claim 16, further comprising:
supplying the amplified signal from the peak amplifier to a second impedance matching block; and is
The signal from the second impedance matching block is provided to an impedance inverter that delays the signal from the second impedance matching block by a value approximately equal to an odd multiple of 90 degrees.
18. The method of claim 17, wherein the impedance inverter is an integrated transmission line and the delay is about 270 degrees.
19. The method of claim 17 or 18, wherein the impedance inverter is an integrated microstrip transmission line having a characteristic impedance determined approximately by the expression:
20. the method of any of claims 17 to 19, further comprising: a drain-source voltage is applied to a transistor of the main amplifier via a shunt inductor located in the first impedance matching block and connected in series with the decoupling capacitor between the RF signal path from the main amplifier and a reference potential.
21. The method of any of claims 16 to 20, further comprising: the combined signal from the combining node is provided via an output port to an external load having an impedance of approximately 50 ohms.
22. An inverted doherty amplifier comprising:
a main amplifier in the first circuit branch;
a peak amplifier in the second circuit branch and arranged to operate as a class C amplifier;
a combining node located at a position where a first portion after the main amplifier in the first circuit branch is connected with a second portion after the peak amplifier in the second circuit branch;
an impedance inverter located in the second circuit branch between the peak amplifier and the combining node, wherein the impedance inverter comprises an integrated transmission line having a characteristic impedance that is within 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load which, when connected to the output of the main amplifier, provides maximum power transfer from the main amplifier, R LIs the resistance of a load driven by the inverse doherty amplifier, and α is the asymmetry factor of the inverse doherty amplifier, where the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier, and
an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
23. The inverse doherty amplifier of claim 22 wherein Z optmFrom a real resistance R optmAnd (4) forming.
24. The inverse doherty amplifier of claim 22 or 23 wherein the impedance inverter comprises a microstrip transmission line.
25. The inverse doherty amplifier of claim 23 wherein the characteristic impedance of the microstrip transmission line is approximately equal to the impedance at the combining node multiplied by (1+ α)/α.
26. The inverse doherty amplifier of any one of claims 22-25 wherein the impedance inverter adds approximately 270 degrees of phase delay.
27. A backward doherty amplifier according to any of claims 22-26 and wherein the RF fractional bandwidth of the backward doherty amplifier, defined by the S11 scattering parameter at the output of the main amplifier, is 7% to 25% when the asymmetry factor of the backward doherty amplifier is 1, looking towards the combining node and the peak amplifier is in the non-amplifying state.
28. An inverse doherty amplifier according to any of claims 22-27 and wherein said combining node is arranged to be directly connected to a load having an impedance approximately equal to 50 ohms.
29. The inverse doherty amplifier of any one of claims 22-28, further comprising:
a coupler arranged to split an input signal into a first signal provided to a first circuit branch and a second signal provided to a second circuit branch, and to add to the first signal a first phase delay having more than 80 degrees relative to the second signal;
a first impedance matching block connected between the main amplifier and the combining node in a first portion of the first circuit branch; and
a second impedance matching block connected between the peak amplifier and the impedance inverter in the second portion of the second circuit branch.
30. The inverse doherty amplifier of claim 29, further comprising:
a first shunt inductor and a first capacitor in the first impedance matching section, which are connected in series between an output of the main amplifier and a first reference potential; and
a second shunt inductor and a second capacitor in the second impedance matching block, which are connected in series between the output of the peak amplifier and a second reference potential.
31. The inverse doherty amplifier of claim 30, further comprising:
a first bias terminal connected to the first shunt inductor and arranged to provide a first bias path for applying a first bias voltage to the main amplifier via the first shunt inductor; and
a second bias terminal connected to the second shunt inductor and arranged to provide a second bias path for applying a second bias voltage to the peaking amplifier via the second shunt inductor.
32. An inverse doherty amplifier according to claim 30 or 31 and wherein the value of said first capacitor is between 100 picofarads and 10 microfarads.
33. The inverse doherty amplifier of any one of claims 29-32 wherein the first impedance matching component is configured to match an input impedance Z optConversion to an output impedance R combSaid output impedance R combWithin 30% of the value determined by the expression:
34. the inverse doherty amplifier of any one of claims 29 to 33 wherein the impedance inverter increases the second phase delay by about equal to the first phase delay.
35. The inverse doherty amplifier of any one of claims 29-34 wherein the impedance inverter increases the second phase delay by an odd multiple equal to approximately 90 degrees.
36. The inverse doherty amplifier of any one of claims 29-35 wherein the first and second impedance matching components each provide a phase delay of approximately 90 degrees.
37. The inverse doherty amplifier of any one of claims 22-36 wherein the main and peak amplifiers comprise gallium nitride transistors.
38. A method of operating an inverse doherty amplifier, the method comprising:
receiving an input signal;
dividing an input signal;
providing a first portion of an input signal to a first circuit branch comprising a main amplifier;
providing a second portion of the input signal to a second circuit branch comprising a peak amplifier operating as a class C amplifier;
providing a signal after the peak amplifier in the second circuit branch to an impedance inverter, wherein the impedance inverter comprises an integrated transmission line having a characteristic impedance that is within 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load which, when connected to the output of the main amplifier, provides maximum power transfer from the main amplifier, R LIs the resistance of the load driven by the inverse doherty amplifier, and α is the asymmetry factor of the inverse doherty amplifier, where the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier;
combining at a combining node a signal from after the main amplifier in the first circuit branch and a signal after the peak amplifier in the second circuit branch; and
providing an output signal from the combining node to an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
39. The method of claim 38, further comprising: the input impedance Z is coupled to the main amplifier and the combining node by means of a first impedance matching block connected between the main amplifier and the combining node in a first part of the first circuit branch optConversion to an output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
40. the method of claim 39, further comprising:
supplying the amplified signal from the peak amplifier to a second impedance matching block; and is
The signal from the second impedance matching block is provided to an impedance inverter that delays the signal from the second impedance matching block by a value approximately equal to an odd multiple of 90 degrees.
41. The method of claim 39 or 40, further comprising: a drain-source voltage is applied to a transistor of the main amplifier via a shunt inductor located in the first impedance matching block and connected in series with the decoupling capacitor between the RF signal path from the main amplifier and a reference potential.
42. The method of any of claims 38 to 41, further comprising: the signal in the second circuit branch is delayed by approximately 270 degrees by the impedance inverter.
43. The method of any of claims 38 to 42, further comprising: the output signal is provided to an external load having an impedance of about 50 ohms.
Technical Field
The present technology relates to high speed, high power, wide bandwidth Doherty (Doherty) amplifiers.
Background
High-speed power amplifiers formed from semiconductor materials have a variety of useful applications, such as Radio Frequency (RF) communications, radar, RF energy, and microwave applications. In recent years, gallium nitride semiconductor materials have received considerable attention due to their desirable electronic and electro-optical properties. GaN has a wide direct band gap of about 3.4eV corresponding to the blue wavelength region of the visible spectrum. Due to its wider bandgap, GaN is more resistant to avalanche breakdown and can maintain electrical performance at higher temperatures than other semiconductors such as silicon. GaN also has a higher carrier saturation velocity compared to silicon. In addition, GaN has a wurtzite crystal structure, is a very stable and hard material, has high thermal conductivity, and has a much higher melting point than other conventional semiconductors (such as silicon, germanium, and gallium arsenide). Thus, GaN is useful for high speed, high voltage and high power applications.
Applications supporting mobile communications and wireless internet access under current and proposed communication standards, such as WiMax, 4G and 5G, may place stringent performance requirements on high-speed amplifiers composed of semiconductor transistors. The amplifier may need to meet performance specifications related to output power, signal linearity, signal gain, bandwidth, and efficiency.
Disclosure of Invention
Apparatus and methods for improving the performance of high speed, high power, wideband amplifiers are described. The structure and method relate to a circuit for combining amplified signals in an inverse doherty amplifier. Impedance matching unit, impedance of impedance inverter (sometimes referred to as delay line)Or bias line), the phase delay of the impedance inverter, and the impedance at the combined node of the inverse doherty amplifiers can be configured to significantly improve the amplifier RF fractional bandwidth (Δ ω/ω) of the symmetric inverse doherty amplifier and the asymmetric inverse doherty amplifier o) And signal bandwidth (also referred to as "instantaneous bandwidth").
Some embodiments relate to an inverse doherty amplifier, comprising: a main amplifier in the first circuit branch; a peak amplifier in the second circuit branch and arranged to operate as a class C amplifier; a combining node located at a position where a first portion after the main amplifier in the first circuit branch is connected with a second portion after the peak amplifier in the second circuit branch; a first impedance matching element connected between the main amplifier and the combining node in a first portion of the first circuit branch, wherein the first impedance matching component matches the input impedance Z optConversion to output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load of the main amplifier that provides maximum power transfer from the main amplifier when connected to the output of the main amplifier, R LIs the resistance of a load driven by the inverted doherty amplifier, and α is the asymmetry factor of the inverted doherty amplifier, wherein the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier, and an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
In some aspects, Z optmFrom a real resistance R optmComposition and resistance value R combIs within 20% of the expression in the previous paragraph. In some cases, the inverse doherty amplifier can further include:in some embodiments, the characteristic impedance of the microstrip transmission line is approximately equal to the impedance at the combining node multiplied by (1+ α)/α.
According to some embodiments, when the asymmetry factor of the inverse doherty amplifier is 1, the RF fractional bandwidth of the inverse doherty amplifier, defined by the S11 scattering parameter at the output of the main amplifier, is 7% to 25% looking towards the combining node and the peak amplifier is in the non-amplified state.
In some cases, the combining node of the inverted doherty amplifier is arranged to be directly connected to a load having an impedance approximately equal to 50 ohms.
In some embodiments, the inverse doherty amplifier can further include: a coupler arranged to split an input signal into a first signal provided to a first circuit branch and a second signal provided to a second circuit branch, and to add to the first signal a first phase delay having more than 80 degrees relative to the second signal; and a second impedance matching block connected between the peak amplifier and the impedance inverter in the second portion of the second circuit branch.
In some aspects, the inverse doherty amplifier can further comprise: a first shunt inductor and a first capacitor in the first impedance matching section, which are connected in series between an output of the main amplifier and a first reference potential; and a second shunt inductor and a second capacitor in the second impedance matching section, which are connected in series between the output of the peak amplifier and a second reference potential.
The inverse doherty amplifier may further include: a first bias terminal connected to the first shunt inductor and arranged to provide a first bias path for applying a first bias voltage to the main amplifier via the first shunt inductor; and a second bias terminal connected to the second shunt inductor and arranged to provide a second bias path for applying a second bias voltage to the peaking amplifier via the second shunt inductor. In some aspects, the first capacitor has a value of 100 picofarads to 10 microfarads.
In some embodiments, the impedance inverter increases a second phase delay approximately equal to the first phase delay. In some cases, the impedance inverter increases a second phase delay equal to approximately an odd multiple of 90 degrees.
According to some embodiments, the first impedance matching block and the second impedance matching block each provide a phase delay of about 90 degrees.
In some cases, the main amplifier and the peak amplifier include gallium nitride transistors.
Some embodiments relate to a method of operating an inverse doherty amplifier. A method may include the operations of: receiving an input signal; dividing an input signal; providing a first portion of an input signal to a first circuit branch comprising a main amplifier; providing a second portion of the input signal to a second circuit branch comprising a peak amplifier operating as a class C amplifier; the input impedance Z is coupled to the main amplifier and the combining node by means of a first impedance matching block connected between the main amplifier and the combining node in a first part of the first circuit branch optConversion to an output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load of the main amplifier that provides maximum power transfer from the main amplifier when connected to the output of the main amplifier, R LIs the resistance of a load driven by the inverse doherty amplifier, and α is the asymmetry factor of the inverse doherty amplifier, wherein the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier, grouping a signal from after the main amplifier in the first circuit branch and a signal after the peak amplifier in the second circuit branch at a combining nodeCombining; and providing an output signal from the combining node to an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
In some cases, a method may further comprise: supplying the amplified signal from the peak amplifier to a second impedance matching block; and providing the signal from the second impedance matching block to an impedance inverter that delays the signal from the second impedance matching block by a value approximately equal to an odd multiple of 90 degrees.
In some aspects, the impedance inverter is an integrated transmission line and the delay is about 270 degrees. In some embodiments, the impedance inverter is an integrated microstrip transmission line having a characteristic impedance determined approximately by the expression:
a method of operating an inverse doherty amplifier can further comprise: a drain-source voltage is applied to a transistor of the main amplifier via a shunt inductor located in the first impedance matching block and connected in series with the decoupling capacitor between the RF signal path from the main amplifier and a reference potential.
In some aspects, a method further comprises: the combined signal from the combining node is provided via an output port to an external load having an impedance of approximately 50 ohms.
Some embodiments relate to an inverse doherty amplifier, comprising: a main amplifier in the first circuit branch; a peak amplifier in the second circuit branch and arranged to operate as a class C amplifier; a combining node located at a position where a first portion after the main amplifier in the first circuit branch is connected with a second portion after the peak amplifier in the second circuit branch; an impedance inverter located in the second circuit branch between the peak amplifier and the combining node, wherein the impedance inverter comprises an integrated transmission line having a characteristic impedance that is within 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load which, when connected to the output of the main amplifier, provides maximum power transfer from the main amplifier, R LIs the resistance of a load driven by the inverted doherty amplifier, and α is the asymmetry factor of the inverted doherty amplifier, wherein the asymmetry factor is the ratio of the maximum power output by the peak amplifier to the maximum power output by the main amplifier, and an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
In some aspects, Z optmFrom a real resistance R optmIn some embodiments, the microstrip transmission line has a characteristic impedance approximately equal to the impedance at the combining node multiplied by (1+ α)/α.
According to some aspects, when the asymmetry factor of the inverse doherty amplifier is 1, the RF fractional bandwidth of the inverse doherty amplifier, as defined by the S11 scattering parameter at the output of the main amplifier, is 7% to 25% looking towards the combining node and the peak amplifier is in the non-amplifying state.
In some cases, the combining node is arranged to be directly connected to a load having an impedance approximately equal to 50 ohms.
The inverted doherty amplifier can also include: a coupler arranged to split an input signal into a first signal provided to a first circuit branch and a second signal provided to a second circuit branch, and to add to the first signal a first phase delay having more than 80 degrees relative to the second signal; a first impedance matching block connected between the main amplifier and the combining node in a first portion of the first circuit branch; and a second impedance matching block connected between the peak amplifier and the impedance inverter in the second portion of the second circuit branch.
In some cases, the inverse doherty amplifier can further include: a first shunt inductor and a first capacitor in the first impedance matching section, which are connected in series between an output of the main amplifier and a first reference potential; and a second shunt inductor and a second capacitor in the second impedance matching section, which are connected in series between the output of the peak amplifier and a second reference potential.
In some embodiments, the inverse doherty amplifier further comprises: a first bias terminal connected to the first shunt inductor and arranged to provide a first bias path for applying a first bias voltage to the main amplifier via the first shunt inductor; and a second bias terminal connected to the second shunt inductor and arranged to provide a second bias path for applying a second bias voltage to the peaking amplifier via the second shunt inductor. The value of the first capacitor may be 100 picofarads to 10 microfarads.
In some aspects, the first impedance matching component is configured to match an input impedance Z optConversion to an output impedance R combSaid output impedance R combWithin 30% of the value determined by the expression:
in some cases, the impedance inverter increases a second phase delay that is approximately equal to the first phase delay. In some embodiments, the impedance inverter increases the second phase delay by an odd multiple of approximately equal to 90 degrees. According to some aspects, the first and second impedance matching blocks each provide a phase delay of about 90 degrees.
In some cases, the main amplifier and the peak amplifier include gallium nitride transistors.
Some embodiments relate to a method of operating an inverse doherty amplifier. A method may include the operations of: receiving an input signal; dividing an input signal; providing a first portion of an input signal to a first circuit branch comprising a main amplifier; providing a second portion of the input signal to a second circuit branch comprising a peak amplifier operating as a class C amplifier; providing a signal after the peak amplifier in the second circuit branch to an impedance inverter, wherein the impedance inverter comprises an integrated transmission line having a characteristic impedance that is within 30% of a value determined by the following expression:
wherein Z is optmIs an impedance load which, when connected to the output of the main amplifier, provides maximum power transfer from the main amplifier, R LIs a resistance of a load driven by the inverse doherty amplifier, and α is an asymmetry factor of the inverse doherty amplifier, wherein the asymmetry factor is a ratio of a maximum power output by the peak amplifier to a maximum power output by the main amplifier, combining a signal from after the main amplifier in the first circuit branch and a signal from after the peak amplifier in the second circuit branch at a combining node, and providing an output signal from the combining node to an output port connected to the combining node and configured to be connected to an external circuit, wherein there is no impedance matching component between the output port and the combining node.
In some aspects, a method may further comprise: the input impedance Z is coupled to the main amplifier and the combining node by means of a first impedance matching block connected between the main amplifier and the combining node in a first part of the first circuit branch optConversion to an output impedance R combSaid output impedance R combWithin 30% of a value determined by the following expression:
in some embodiments, a method may further comprise: supplying the amplified signal from the peak amplifier to a second impedance matching block; and providing the signal from the second impedance matching block to an impedance inverter that delays the signal from the second impedance matching block by a value approximately equal to an odd multiple of 90 degrees.
In some cases, a method may further comprise: a drain-source voltage is applied to a transistor of the main amplifier via a shunt inductor located in the first impedance matching block and connected in series with the decoupling capacitor between the RF signal path from the main amplifier and a reference potential.
In some aspects, a method further comprises: the signal in the second circuit branch is delayed by approximately 270 degrees by the impedance inverter.
In some embodiments, a method further comprises providing the output signal to an external load having an impedance of about 50 ohms.
The foregoing apparatus and method embodiments may be implemented with any suitable combination of the aspects, features, and operations described above or in further detail below. These and other aspects, embodiments, and features of the present invention will be more fully understood from the following description taken in conjunction with the accompanying drawings.
Drawings
The skilled artisan will appreciate that the drawings described herein are for illustration purposes only. It is understood that aspects of the embodiments may in some cases be shown exaggerated or enlarged to facilitate an understanding of the embodiments. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the teachings. In the drawings, like reference characters generally refer to like features, functionally similar, and/or structurally similar elements throughout the separate views. Wherein the figures relating to microfabricated circuitry show only one device and/or circuit to simplify the figures. In practice, a large number of devices or circuits can be fabricated in parallel over a large area of the substrate or the entire substrate. Further, the described devices or circuits may be integrated within a larger circuit.
Spatial references to "top," "bottom," "upper," "lower," "vertical," "horizontal," and the like may be used when referring to the figures in the following detailed description. Such references are for teaching purposes and are not intended as absolute references to the embodied devices. The embodied devices may be spatially oriented in any suitable manner different from the orientation shown in the figures. The drawings are not intended to limit the scope of the present teachings in any way.
FIG. 1 shows an arrangement of a conventional Doherty amplifier;
FIG. 2 shows an equivalent circuit of a Doherty amplifier operating at low output power;
FIG. 3 depicts a frequency response curve of a Doherty amplifier in accordance with some embodiments;
FIG. 4 illustrates an inverse Doherty amplifier in accordance with some embodiments wherein an impedance inverter at the output of the amplifier is located between the peaking amplifier and a combining node;
FIG. 5 illustrates components of an inverse Doherty amplifier in accordance with some embodiments;
FIG. 6 depicts frequency response curves for symmetric and asymmetric inverse Doherty amplifiers in accordance with some embodiments;
FIG. 7 depicts a frequency response curve of an asymmetric inverse Doherty amplifier in accordance with some embodiments in which the impedance varies at a combining node;
FIG. 8 illustrates an impedance matching network according to some embodiments;
FIG. 9 illustrates an impedance matching network for an inverse Doherty amplifier in accordance with some embodiments;
FIG. 10 depicts frequency response curves for two embodiments of an inverse Doherty amplifier in accordance with some embodiments; and
FIG. 11 illustrates components of an inverse Doherty amplifier in accordance with some embodiments.
The features and advantages of the embodiments shown in the detailed description given below will become more apparent when considered in conjunction with the accompanying drawings.
Detailed Description
Among the different types of amplifiers available, doherty amplifiers are well suited for RF communication applications. Certain RF communication protocols, such as wideband code division multiple access and orthogonal frequency division multiplexing, typically include signals with high peak-to-average power ratios. Amplifier linearity is important for such systems. However, maintaining amplifier linearity over a large signal power range with a single stage amplifier results in poor amplifier power efficiency. The doherty amplifier 100 shown in fig. 1 can improve power efficiency by using series amplifiers: a main amplifier 132 (operating in class AB or class B mode) and a peak amplifier 138 (operating in class C mode). Although the main and peak amplifiers may be of the same design,
In the doherty amplifier, the
After the
The impedance matching components 122, 124 may be placed before the
The inventors have recognized and appreciated that doherty amplifier 100 having the configuration shown in fig. 1 has bandwidth limitations associated with the circuit topology. This bandwidth limitation is due in part to the long electrical path length added by the impedance matching components 122, 124, 142, 144. Due to the increased electrical path length,
To investigate the cost of the bandwidth performance of the doherty amplifier 100 due to impedance matching components, a high frequency simulation was performed using a low
In the low
The simulation of the circuits and circuit elements described herein can be implemented using software tools such as the Advanced Design Systems (ADS) available from texas Technologies, located in Santa Rosa, California. Other suitable Software tools include, but are not limited to, the NI AWR Design Environment (NI AWR Design Environment) available from AWR located in Elssendo, California, and the Sonnet Software available from Sonnet Software located in North Syracuse, New York
A software tool.The doherty amplifier 100 and the simulation results as modeled in fig. 2 are shown in fig. 3. The
The inventors have recognized and appreciated that well-designed inverted doherty amplifier configurations can provide a much larger RF fractional bandwidth than conventional doherty amplifiers. Fig. 4 illustrates an inverse doherty amplifier topology according to some embodiments. In an inverse doherty amplifier, a 90 ° phase delay at
In overview and in accordance with some embodiments, the
The components of the
More specifically,
The
According to some embodiments, the
Each
In some embodiments, the
In some embodiments of the inverted
The
In symmetric and asymmetric inverse doherty amplifiers, the main and peak amplifiers may be biased differently at their gates. The
The inventors have recognized and appreciated that the configuration of the
Value R
optmIs a real impedance value that would go from the power transistor of the main amplifier to the load R if connected directly as a load to the transistor drain of the
Value R optm(or Z) optm) Typically depending on the characteristics of the amplifier. For example, and in some embodiments, R may be determined approximately using the following relationship optm。
R optm≈2(V ds-V k)/I max(equation 1)
Wherein, V dsIs a drain-source bias applied to the amplifier, V kIs the knee voltage of the amplifier, and I maxIs the maximum output current of the amplifier. V ds、V kAnd I maxThe value of (d) may be listed in the amplifier's operating specification or data table, or may be measured when a transistor has been switched into the main amplifier. Other methods may be used to determine R optmSuch as using load pull techniques or using a non-linear model of the amplifier transistors.
Additional details of the output components (sometimes referred to as the load network) of the inverse doherty amplifier are shown in fig. 5, according to some embodiments. In some cases, the
β ═ 1+ α (equation 2)
α=P p/P m(equation 3)
Wherein, P
pIs the maximum output power capability of the peaking
Value R
combIs selected as the output impedance of the
With the above selection of impedance values and modeling of the
According to some embodiments, R can be determined in the following manner
combThe value of (c). As described above, the limiting RF fractional bandwidth (low power bandwidth) of the doherty amplifier occurs when the
R optm/R comb=(R comb/β)R L(equation 4)
For R combProcessing equation 4, the following expression is given
Wherein R is
optmRepresents an impedance matching value (which may be approximately determined using equation 1 for the main amplifier), R, for maximum power transfer from the
Equation 6 may be used to obtain the impedance value at the combining
For illustrative purposes only and not to limit the invention, some example impedance values may be calculated from the above equations for a GaN-based inverse doherty amplifier. Different values can be obtained for an inverse doherty amplifier based on other semiconductors or different transistor designs. In some main amplifiers, the drain-source voltage may be about 50V, with a maximum current capability of 3A, and the knee voltage may be about 3V. According to equation 1, R
optmApproximately 31.3 ohms. If the inverse Doherty is symmetric and configured to driveA 50 ohm load, the impedance R at the combining
If the inverted doherty amplifier is not symmetric (α >1), the calculated value will change based on the values of α and β the impedance at the combining
Simulations similar to those performed for a conventional doherty amplifier and discussed above in connection with fig. 3 were performed on an inverted doherty amplifier configured as described in fig. 5. In a first set of simulations, the
Fig. 6 shows the simulation results for the low power case (peak amplifier idle). The graph plots the S11 scattering parameter at the output of the
For a symmetric inverse doherty amplifier (α ═ 1), the RF fractional bandwidth is wide, and the reflected signal from the impedance matching component of the main amplifier is not increased by about-20 dB to exceed the simulated frequency range in which case the RF fractional bandwidth can be determined by the frequency characteristics of the
The signal bandwidth (also referred to as the "instantaneous bandwidth" or "video bandwidth") can be defined as the maximum modulated signal that can be amplified by an inverse doherty amplifier without asymmetric distortion. The signal bandwidth is less than or equal to the RF fractional bandwidth. It may be important to avoid introducing asymmetric distortion because a digital predistortion system (which may be used in conjunction with a doherty amplifier to linearize the signal) may not be able to correct for asymmetric distortion.
One way to measure the signal bandwidth is to apply two unmodulated carrier tones to the inverse doherty amplifier. The spacing between two carrier tones (spacing in frequency) may be initially small (e.g., a few kilohertz or megahertz) and then increase while the amplitude of the third order intermodulation products is plotted as a function of frequency spacing. According to some embodiments, the frequency spacing at which there is a significant change in the divergence of the third order intermodulation products is approximately representative of the signal bandwidth.
Additional simulations were performed on the same reverse doherty configuration depicted in fig. 5 to evaluate the RF fractional bandwidth versus R optmThe results of these simulations are shown in FIG. 7. in these simulations, the asymmetry factor α is fixed at 1.5, and R is optmVarying from 5 ohms to 45 ohms in 5ohm steps. R ranging from 5 to 25 ohms is shown in the graph next to each curve optmThe value is obtained. Also to R optmA curve is plotted at 45 ohms. For R between about 10 and 20 ohms optmThe value, the reflected signal does not rise above-20 dB, indicating a potentially wide RF and signal bandwidth. For R less than about 10 ohms optmValue, RF fractional bandwidth with R optmThe decrease in value becomes well defined and narrows. For R greater than about 20 ohms optmValue, RF fractional bandwidth with R optmThe increase in value becomes well defined and narrows. Even at R of 5ohm and 45ohm optmAt this value, the fractional bandwidth of the RF for an asymmetric configuration is approximately 29%, which is much larger than the typical 4% bandwidth value of a conventional symmetric doherty amplifier. The signal bandwidth, which can be no greater than and typically less than the RF fractional bandwidth, will also be significantly greater than that of conventional doherty amplifiers. For a symmetric inverse doherty amplifier configured in accordance with the present embodiment, the RF and signal bandwidths will be even greater.
The results of FIG. 7 show that in the inverted Doherty amplifier of the present embodiment, R is
optmCan vary by as much as 50% (e.g., 20
Since it can be roughly based on R according to equation 6
optmTo determine the impedance R at the combining
The inventors have further recognized and appreciated that careful design of the
According to some embodiments, the impedance matching network 800 may further comprise a bias port V for applying a drain-source bias to a transistor of the amplifier bias. The bias port may be connected to a shunt inductor L shAnd a decoupling capacitor C decA node in between.
Another example of an
The values of the inductors and capacitors of the
The impedance matching networks shown in fig. 8 and 9 are both capable of providing the desired impedance transformation and phase delay despite the bandwidth associated with each impedance matching network. Using RF circuit simulations for both impedance matching networks, the inventors have found that the arrangement of elements in the impedance matching network 800 of fig. 8 is capable of providing a 90 ° phase delay at a center frequency of about 2.65GHz and exhibits an RF fractional bandwidth of about 19% (determined by frequency analysis of the S11 scattering parameter where the reflected signal rises 20dB below the incident signal). The phase delay varies by about ± 15 ° over the RF fractional bandwidth. For the simulation L sh=1.25nH;C dec=0.1μF;L ser=1.29nH;C ser=33.17pF;C sh2.73 pF. Other values may be used to obtain similarly wide bandwidths at other center frequencies.
For comparison, the
According to some embodiments, the
Additional simulations were performed in order to include the effects of the impedance matching network 800 described in fig. 8 and to evaluate the effects of the added phase delay in the
The results of the high power, symmetrical inverse doherty simulation for both cases are plotted in fig. 10. Both cases are low power cases when the peak amplifier is in an idle state, which represents the most restrictive case in terms of amplifier bandwidth. In both simulations, the component values of the impedance matching network 800 were: l is sh=1.06nH;C dec=0.1μF;L ser=1.20nH;C ser=99.02pF;C sh=2.32pF。
In a first simulation (labeled 90 °), the inversion is by impedanceThe phase delay provided by the
Somewhat surprisingly, reconfiguring
The results show that improvements in the RF and signal bandwidth of the amplifier can be obtained with an inverse doherty amplifier configuration, where the impedance matching components, impedance inverters, and the design of the impedances at the combining nodes are based on the characteristics (R) of the main and peak amplifiers
optm,R
optp) The asymmetry factor of the doherty, and the load impedance. In part, bandwidth improvement can be achieved by making the ratio of the impedance transformation from the output of the
Although the
In some embodiments, the asymmetric inverse doherty amplifier can be constructed in different ways. One approach is to set the gate width of the power transistors in the
According to some embodiments, a more compact amplifier package may be obtained by omitting the output
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