阅读说明：本技术 基于传输线行波量化的超高速时间编码器及编码方法 (Ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization ) 是由 朱樟明 梁鸿志 刘术彬 丁瑞雪 于 2021-06-08 设计创作，主要内容包括：本发明提供的一种基于传输线行波量化的超高速时间编码器及编码方法,通过设计差分时钟传输线作为延迟基准,将一对固定时钟信号的频率设置为采样保持频率的两倍,将TCD输出两个上升沿TCD-OUTP和TCD-OUTN之间的时间差ΔT通过放电通路控制在0～π/f-tline范围内,从而当时间差ΔT小于传输线上相邻输出口TAP之间的行波传输时间,则相位差检测输出则为全0数字码,而当时间差ΔT等于π/f-tline,则两次相位差检测电路输入相差180°,故输出为全1数字码,其中输出数字码1的数量和时间差ΔT的差值成线性正比,从而实现以传输线延时为基准的TDC量化编码方式。(The invention provides an ultra-high speed time encoder and an encoding method based on transmission line traveling wave quantization, by designing a differential clock transmission line as a delay reference, setting the frequency of a pair of fixed clock signals to be twice of the sampling and holding frequency, controlling the time difference delta T between two rising edges TCD _ OUTP and TCD _ OUTN output by the TCD within the range of 0-pi/f _ tline through a discharge path, so that when the time difference delta T is less than the traveling wave transmission time between adjacent output ports TAP on the transmission line, the phase difference detection output is an all-0 digital code, when the time difference delta T is equal to pi/f-tline, the phase difference between the inputs of the two phase difference detection circuits is 180 degrees, so that the output is all-1 digital code, the quantity of the output digital codes 1 is in linear proportion to the difference value of the time difference delta T, so that a TDC quantization coding mode taking transmission line delay as reference is realized.)

1. An ultra-high speed time encoder based on transmission line traveling wave quantization, said ultra-high speed time encoder connected to a time converter, comprising: the device comprises a clock driving circuit, a transmission line impedance matching unit, a differential clock transmission line, a plurality of delay quantization units, a clock tree transmission unit and a digital coding circuit;

the input end of the clock driving circuit is connected with a pair of fixed clock signals, the output end of the clock driving circuit is connected with one end of the differential clock transmission line, the other end of the differential clock transmission line is connected with the transmission line impedance matching unit, the clock driving circuit outputs a pair of delay clock signals, the clock tree transmission unit is connected with a first output signal (TCD _ OUTP) and a second output signal (TCD _ OUTN) output by the VTC output by the time converter, the output end of the clock tree transmission unit is connected with each delay quantization unit, and each output end of the delay quantization unit is connected to the digital coding circuit;

wherein, the pair of delayed clock signals is a first delayed clock signal (CLK _ P) and a second delayed clock signal (CLK _ M);

the clock tree transmission unit transmits rising edges of a first output signal (TCD _ OUTP) and a second output signal (TCD _ OUTN) output by the VTC to the plurality of delay quantization units;

each delay quantization unit performs a first sampling of the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) upon arrival of the first delayed clock signal (CLK _ P) transmitted by the first differential clock transmission line, and performs a second sampling of the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) upon arrival of the second delayed clock signal (CLK _ M) transmitted by the second differential clock transmission line, and outputs the first and second output signals (TCD _ OUTP) and (TCD _ OUTN) to the digital encoding circuit;

the differential clock transmission lines comprise a first differential clock transmission line and a second differential clock transmission line which have the same internal structure, a first distance between the first differential clock transmission line and the second differential clock transmission line, a second distance between an internal metal layer and a shielding layer of each differential clock transmission line, and a line width of each differential clock transmission line are in positive correlation with a time difference delta T, wherein the time difference delta T is a time difference between a first output signal (TCD _ OUTP) and a second output signal (TCD _ OUTN);

and the digital coding circuit correspondingly codes the output of each delay quantization unit, converts the output into binary codes and outputs the binary codes.

2. The ultra high speed time encoder of claim 1, wherein said transmission line clock driver circuit comprises two transistors, two resistors and a current source, wherein the drain of each transistor is connected to a respective resistor, the ends of the two resistors not connected to the transistors are connected together to a Voltage (VDD), the sources of the two transistors are connected together and then connected to the positive end of the current source, the negative end of the current source is connected to a power ground, the gate of each transistor is connected to a respective fixed clock signal, and the respective output of the drain of each transistor is connected to a differential clock transmission line.

3. The ultra high speed time encoder according to claim 1, wherein said transmission line impedance matching unit comprises two adjustable resistors, each of which has one end connected to a differential clock transmission line and the other end connected to a power ground.

4. The ultra high speed time encoder as claimed in claim 1, wherein each delay quantization unit comprises two D flip-flops and an exclusive or gate, wherein a clock terminal of one D flip-flop is connected to a clock signal of the first output signal (TCD _ OUTP) transmitted by the clock tree transmission unit, a clock terminal of the other D flip-flop is connected to a clock signal of the second output signal (TCD _ OUTP) transmitted by the clock tree transmission unit, data terminals of the two D flip-flops are simultaneously connected to the first clock differential transmission line and the second clock differential transmission line, output terminals of the two D flip-flops are connected to the exclusive or gate, and an output of the exclusive or gate is connected to the digital coding unit.

5. The ultra high speed time encoder according to claim 1, wherein the digital coding circuit performs exclusive or on the output of each delay quantization unit to obtain a binary code and outputs the binary code.

6. An ultra high speed time encoder as claimed in claim 1, wherein the frequency of the fixed clock signal is set to twice the frequency of the sample and hold clock.

7. An encoding method based on transmission line traveling wave quantization using the ultra-high speed time encoder according to any one of claims 1 to 4, the encoding method comprising:

determining a parameter of the differential clock transmission line based on a time difference Δ T between a first output signal (TCD _ OUTP) and a second output signal (TCD _ OUTN) output by the VTC output of the time converter;

wherein the parameters include: a first spacing between the first differential clock transmission line and the second differential clock transmission line, a second spacing between the inner metal layer and the shielding layer of each differential clock transmission line, and a line width of the differential clock transmission lines;

when the differential clock transmission line after the parameter determination transmits the delay clock signals, each delay quantization unit is obtained, when a first delay clock signal (CLK _ P) transmitted by the first differential clock transmission line arrives, the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) are sampled for the first time, when a second delay clock signal (CLK _ M) transmitted by the second differential clock transmission line arrives, the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) are sampled for the second time, and the digital coding circuit correspondingly codes the output of each delay quantization unit and converts the output into a binary coding output result.

8. The encoding method according to claim 7, wherein determining the parameter of the differential clock transmission line based on the time difference Δ T between the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) of the VTC output from the time converter comprises:

a time difference Δ T between the first output signal (TCD _ OUTP) and the second output signal (TCD _ OUTN) based on the VTC output from the time converter;

determining a maximum value in the time difference Δ T;

determining the transmission time delay of the port of each adjacent delay quantization unit connected on each differential clock transmission line based on the maximum value and the precision of the ultra-high speed time encoder;

and determining parameters of the differential clock transmission line based on the transmission time delay.

9. The encoding method according to claim 7, wherein the digital encoding circuit performs exclusive-or on an output of each delay quantization unit to obtain a binary code and outputs the binary code.

Technical Field

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to an ultra-high-speed time encoder and an encoding method based on transmission line traveling wave quantization.

Background

An ultra-high speed Time domain analog-to-Digital converter (adc) mainly comprises a Voltage Time Converter (VTC) and a Time Digital encoder (TDC). The VTC is composed of a sample-and-hold circuit, a voltage-pulse width conversion circuit, and a threshold detection circuit. The TDC is only composed of a transmission line quantizer and a digital transcoding circuit.

Referring to fig. 1, fig. 1 is a connection relationship diagram of a transmission line quantizer and a digital transcoding circuit in a conventional TDC, where the transmission line quantizer in fig. 1 is composed of a quantization unit composed of an inverter delay chain with a delay of t0, an inverter delay chain with a delay of t1, and N flip-flops, and performs quantization coding in a time domain using inverter delays or different inverter delay differences as a reference source. However, in such a structure, the reference source is susceptible to external environment, process and voltage, which causes delay deviation of the reference source. Delay skew can affect overall system performance, while the delay of the inverter chain limits the sampling rate of the overall TDC.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides an ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization. The technical problem to be solved by the invention is realized by the following technical scheme:

in a first aspect, the present invention provides an ultra-high speed time encoder based on transmission line traveling wave quantization, the ultra-high speed time encoder is connected to a time converter, and the ultra-high speed time encoder includes: the device comprises a clock driving circuit, a transmission line impedance matching unit, a differential clock transmission line, a plurality of delay quantization units, a clock tree transmission unit and a digital coding circuit;

the input end of the clock driving circuit is connected with a pair of fixed clock signals, the output end of the clock driving circuit is connected with one end of a differential clock transmission line, the other end of the differential clock transmission line is connected with a transmission line impedance matching unit, the clock driving circuit outputs a pair of delay clock signals, the clock tree transmission unit is connected with a first output signal TCD _ OUTP and a second output signal TCD _ OUTN output by a VTC output by a time converter, the output end of the clock tree transmission unit is connected with each delay quantization unit, and each output end of each delay quantization unit is connected to the digital coding circuit;

wherein, the pair of delayed clock signals are a first delayed clock signal CLK _ P and a second delayed clock signal CLK _ M;

the clock tree transmission unit transmits rising edges of a first output signal TCD _ OUTP and a second output signal TCD _ OUTN output by the VTC to the plurality of delay quantization units;

each delay quantization unit performs first sampling on the first output signal TCD _ OUTP and the second output signal TCD _ OUTN when a first delay clock signal CLK _ P transmitted by the first differential clock transmission line arrives, performs second sampling on the first output signal TCD _ OUTP and the second output signal TCD _ OUTN when a second delay clock signal CLK _ M transmitted by the second differential clock transmission line arrives, and outputs the first output signal TCD _ OUTP and the second output signal TCD _ OUTN to the digital coding circuit;

the differential clock transmission lines comprise a first differential clock transmission line and a second differential clock transmission line which have the same internal structure, a first distance between the first differential clock transmission line and the second differential clock transmission line, a second distance between an internal metal layer and a shielding layer of each differential clock transmission line, and a line width of each differential clock transmission line are in positive correlation with a time difference delta T, wherein the time difference delta T is a time difference between a first output signal TCD _ OUTP and a second output signal TCD _ OUTN;

and the digital coding circuit correspondingly codes the output of each delay quantization unit, converts the output into binary codes and outputs the binary codes.

Optionally, the transmission line clock driving circuit includes two transistors, two resistors, and a current source, a drain of each transistor is connected to a resistor, ends of the two resistors, which are not connected to the transistors, are connected together to access the voltage VDD, sources of the two transistors are connected together and then are connected to a positive end of the current source, a negative end of the current source is connected to a power ground, a gate of each transistor is connected to a fixed clock signal, and an output of a drain of each transistor is connected to a differential clock transmission line.

Optionally, the transmission line impedance matching unit includes two adjustable resistors, one end of each adjustable resistor is connected to one differential clock transmission line, and the other end of each adjustable resistor is connected to the power ground.

Optionally, each delay quantization unit includes two D flip-flops and an exclusive-or gate, a clock terminal of one D flip-flop is connected to a clock signal in the first output signal TCD _ OUTP transmitted by the clock tree transmission unit, a clock terminal of the other D flip-flop is connected to a clock signal in the second output signal TCD _ OUTP transmitted by the clock tree transmission unit, data terminals of the two D flip-flops are simultaneously connected to the first clock differential transmission line and the second clock differential transmission line, output terminals of the two D flip-flops are connected to the exclusive-or gate, and an output of the exclusive-or gate is connected to the digital coding unit.

Optionally, the digital coding circuit performs exclusive or on the output of each delay quantization unit to obtain a binary code and outputs the binary code.

Optionally, the frequency of the fixed clock signal is set to twice the frequency of the sample-and-hold clock.

In a second aspect, the present invention provides a coding method based on transmission line traveling wave quantization, using the ultra-high speed time coder of the first aspect, where the coding method includes:

determining a parameter of the differential clock transmission line based on a time difference Δ T between a first output signal TCD _ OUTP and a second output signal TCD _ OUTN outputted by the VTC outputted by the time converter;

wherein the parameters include: a first spacing between the first differential clock transmission line and the second differential clock transmission line, a second spacing between the inner metal layer and the shielding layer of each differential clock transmission line, and a line width of the differential clock transmission lines;

when the differential clock transmission lines after the parameter determination transmit the delay clock signals, each delay quantization unit is obtained, when the first delay clock signal CLK _ P transmitted by the first differential clock transmission line arrives, the first output signal TCD _ OUTP and the second output signal TCD _ OUTN are sampled for the first time, when the second delay clock signal CLK _ M transmitted by the second differential clock transmission line arrives, the first output signal TCD _ OUTP and the second output signal TCD _ OUTN are sampled for the second time, and the digital coding circuit correspondingly codes the output of each delay quantization unit and converts the output into a binary coding output result.

Optionally, determining the parameter of the differential clock transmission line based on the time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN output by the VTC output from the time converter includes:

a time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN output based on the VTC output from the time converter;

determining a maximum value in the time difference Δ T;

determining the transmission time delay of the port of each differential clock transmission line connected with the adjacent delay quantization unit based on the maximum value and the precision of the ultra-high speed time encoder;

based on the transmission delay, parameters of the differential clock transmission line are determined.

Optionally, the digital coding circuit performs exclusive or on the output of each delay quantization unit to obtain a binary code and outputs the binary code.

Compared with the prior art, the invention can realize at least one of the following beneficial effects:

1. the phase speed of the travelling wave of the differential clock transmission line designed by the invention is kept stable under a fixed frequency, and compared with the TDC taking the time delay of the traditional inverter as the reference, the differential clock transmission line is not easily influenced by the process, the temperature and the external environment.

2. The low-loss transmission line and the programmable impedance matching resistor network are formed, so that the waveform on the transmission line is transmitted by traveling waves without superposition of reflected waves. So that at the same time the first delayed quantisation element output is 180 deg. out of phase with the last delayed quantisation element.

3. The frequency of a fixed clock signal is set to be twice of a sampling holding frequency, the time difference delta T between two rising edges TCD _ OUTP and TCD _ OUTN output by a TCD is controlled within the range of 0-pi/f _ tline through a discharging path by the ultra-high speed time encoder, so that when the time difference delta T is smaller than the traveling wave transmission time between adjacent output ports TAP on a transmission line, the phase difference detection output is all-0 digital codes, and when the time difference delta T is equal to pi/f _ tline, the phase difference detection circuit inputs the phase difference for two times by 180 degrees, the phase difference detection output is all-1 digital codes, wherein the number of the output digital codes 1 is linearly proportional to the difference value of the time difference delta T, and the TDC quantization encoding mode taking transmission line delay as the reference is realized.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a diagram illustrating a connection relationship between a transmission line quantizer and a digital transcoding circuit in a conventional TDC according to an embodiment of the present invention;

FIG. 2 is a block diagram of an ultra-high speed time domain analog-to-digital converter according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an ultra-high speed time encoder based on transmission line traveling wave quantization according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the internal structure of an ultra-high speed time encoder based on transmission line traveling wave quantization according to an embodiment of the present invention;

FIG. 5 is a cross-sectional and top view of a differential clock transmission line provided by an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating a voltage variation of an upper plate of a capacitor CAP _ P and a voltage variation of an upper plate of a capacitor CAP _ N in the VTC according to an embodiment of the present invention;

fig. 7 is a schematic diagram of waveform transmission in the differential clock transmission line according to the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

With reference to fig. 2 and 3, the present invention provides an ultra high speed time encoder based on transmission line traveling wave quantization, the ultra high speed time encoder is connected to a time converter, and the ultra high speed clock encoder includes: the device comprises a clock driving circuit, a transmission line impedance matching unit, a differential clock transmission line, a plurality of delay quantization units, a clock tree transmission unit and a digital coding circuit;

the input end of the clock driving circuit is connected with a pair of fixed clock signals, the output end of the clock driving circuit is connected with one end of a differential clock transmission line, the clock driving circuit outputs a pair of delay clock signals, the other end of the differential clock transmission line is connected with a transmission line impedance matching unit, a clock tree transmission unit is connected with a first output signal TCD _ OUTP and a second output signal TCD _ OUTN output by a VTC output by a time converter, the output end of the clock tree transmission unit is connected with each delay quantization unit, and each output end of each delay quantization unit is connected to a digital coding circuit; the transmission line impedance matching unit comprises two adjustable resistors, one end of each adjustable resistor is connected with one differential clock transmission line, and the other end of each adjustable resistor is connected with a power ground for realizing impedance matching of the differential clock transmission lines. The pair of fixed clock signals are a first clock signal CLK _ TLINEP and a second clock signal CLK _ TLINEM, and the pair of fixed clock signals form a difference. The frequency f _ TLINE of the fixed clock signal CLK _ TLINE is set to be twice the frequency f _ SH of the sample-and-hold clock CLK _ SH. A fixed clock signal is a clock signal whose frequency and amplitude remain unchanged. The pair of delayed clock signals are the first delayed clock signal CLK _ P and the second delayed clock signal CLK _ M. Since a pair of delayed clock signals are transmitted to the differential clock transmission line, the first delayed clock signal is labeled Tline _ p in the drawing, and the second delayed clock signal is labeled Tline _ m in fig. 4.

The transmission line clock driving circuit comprises two transistors, two resistors and a current source, wherein the drain electrode of each transistor is connected with one resistor, one ends of the two resistors, which are not connected with the transistors, are connected together to be connected with a voltage VDD, the sources of the two transistors are connected together and then are connected with the positive end of the current source, the negative end of the current source is connected with a power ground, a fixed clock signal is input into the grid electrode of each transistor, and the output of the drain electrode of each transistor is connected with a differential clock transmission line.

The clock tree transmission unit transmits rising edges of a first output signal TCD _ OUTP and a second output signal TCD _ OUTN output by the VTC to the plurality of delay quantization units;

each delay quantization unit performs first sampling on the first output signal TCD _ OUTP and the second output signal TCD _ OUTN when a first delay clock signal CLK _ P transmitted by the first differential clock transmission line arrives, performs second sampling on the first output signal TCD _ OUTP and the second output signal TCD _ OUTN when a second delay clock signal CLK _ M transmitted by the second differential clock transmission line arrives, and outputs the first output signal TCD _ OUTP and the second output signal TCD _ OUTN to the digital coding circuit;

the differential clock transmission lines comprise a first differential clock transmission line and a second differential clock transmission line which have the same internal structure, and the number of the delay quantization units is determined by the precision of the ultra-high speed time encoder.

Illustratively, when the precision of the TDC is 8-bit precision, the number of delay quantization units is 128.

The digital coding circuit can correspondingly code the output of each delay quantization unit and convert the output into a binary coding output result.

With reference to fig. 2 and fig. 3, the conventional VTC module is used to convert the analog voltage domain input signal into the time domain signal with the delay difference. The process is divided into three stages, wherein the first stage is as follows: the sampling hold circuit samples an input analog domain differential input signal according to a sampling clock CLK _ SH, and respectively saves signals Vin + and Vin- (wherein, the voltage difference value between Vin + and Vin-is defined as delta V) in CAP _ P and CAP _ N, so that the upper voltage values V + and V-of the capacitive devices CAP _ P and CAP _ N are equal to the analog input voltages VIP and VIN; the second stage is as follows: a discharge branch consisting of current mirrors (IDC _ P and IDC _ N) linearly discharges CAP _ P and CAP _ N, so that V + and V-linearly drop during the high level of the clock CLK _ VTC; the third stage is as follows: the threshold detection circuit threshold detects the voltages V + and V-producing two rising edges TCD _ OUTP and TCD _ OUTN with a time difference Δ T that is linearly proportional to the input voltage difference Δ V due to the linear discharge of the capacitor.

Referring to fig. 4, the TDC module of the present invention mainly includes a clock driving circuit, a transmission line impedance matching unit, a differential clock transmission line, a plurality of delay quantization units, a clock tree transmission unit, and a digital coding circuit. According to the time difference delta T between the VTC output signals TCD _ OUTP and TCD _ OUTN, the differential clock transmission line matched with the delay quantization unit is designed for transmitting the reference delay, so that the delay quantization unit quantizes the reference delay in the transmission line, outputs a corresponding digital code, and then converts the digital code into a binary system by a digital coding circuit for outputting.

Referring to fig. 4, from top to bottom, the upper line is a first delay reference line, and the lower line is a second delay reference line.

Referring to the delay quantization unit in fig. 4, each delay quantization unit includes two D flip-flops and an exclusive-or gate, wherein a clock terminal of one D flip-flop is connected to a clock signal in the first output signal TCD _ OUTP transmitted by the clock tree transmission unit, a clock terminal of the other D flip-flop is connected to a clock signal in the second output signal TCD _ OUTP transmitted by the clock tree transmission unit, data terminals of the two D flip-flops are simultaneously connected to the first clock differential transmission line and the second clock differential transmission line, output terminals of the two D flip-flops are connected to the exclusive-or gate, and an output of the exclusive-or gate is connected to the digital coding unit.

Referring to fig. 5, the left side of fig. 5 is a cross section of the differential clock transmission line, the right side is an internal top view of the differential clock transmission line, the outermost side of the clock line is a shielding layer (shielding layer) and the inner side of the shielding layer is a metal layer, a first distance between the first differential clock transmission line and the second differential clock transmission line, a second distance between the internal metal layer of each differential clock transmission line and the shielding layer, and a line width of the differential clock transmission line are in positive correlation with a time difference Δ T, where the time difference Δ T is a time difference between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN;

a first distance between the first differential clock transmission line Spine _ clkp and the second differential clock transmission line Spine _ clkp is converted into a parasitic capacitance C1, and the parasitic inductance is L1. The second distance between the inner protective layer and the metal layer of each differential clock transmission line is converted into a parasitic capacitance C2, and the line width is converted into a parasitic capacitance C3, and the wave velocity in the known lossless transmission line is calculated as follows:

assuming that the transmission line distance between the Tap _ p < n > port and the Tap _ p < n +1> port of the first differential clock transmission line is L _ tline, the transmission delay between the two Tap ports can be calculated as follows:

after the differential input signal passes through the sample-and-hold circuit, the voltage of the upper plate of the capacitor CAP _ P is Vip, the voltage of the upper plate of the capacitor CAP _ N is Vin, and after CLK _ VTC is enabled, the capacitors CAP _ P and CAP _ N are respectively and uniformly discharged by the current sources IDC _ P and IDC _ N, wherein the current sources IDC _ P and IDC _ N are i_dc. Therefore, the voltage of the capacitor plate varies as shown in FIG. 6, when the voltage drops to the threshold value, the threshold point V _ th of the detection circuit generates two pulse signals TCD _ OUTP and TCD _ OUTM,

the time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN is:

maxΔT＝2^a-1·t_delay

therefore, a is the precision of the TDC, and when Δ T is maximum, the difference between the input VIP and VIN is maximum, and the first distance, the second distance, and the line width are solved.

Referring to fig. 7, in which two TCD _ OUTP and TCD _ OUTN rising edges having a time difference Δ T are transported to 128 phase difference delay quantization hospital PDs as two sampling clock inputs by the clock tree transmission unit as shown in fig. 7 for waveform transmission in the differential clock transmission line; the delay quantization unit performs digital encoding according to the phase difference of the two samples. Since the transmission line is designed as a half-wavelength transmission line, assuming that T is 0, the output of each port of the transmission line is all 1, i.e., { Tap <0>, Tap <1>, …, Tap <126>, Tap <128> }, {11 … 11}, and after half cycle of the transmission line clock, T is Ttline/2, the output of each port of the half-wavelength transmission line is all 0, i.e., { Tap <0>, Tap <1>, …, Tap <126>, Tap <128> }, {00 … 00}, and the transmission of the intermediate state waveform from Tap < n > to Tap < n +1> is a standardized time interval. Therefore, two sets of digital code values are generated according to the twice sampling clocks of the TCD output signals TCD _ OUTP and TCD _ OUTN, and the number of the twice digital code changes is the interval between the input signals.

The invention provides an ultra-high speed time encoder based on transmission line traveling wave quantization, which is characterized in that a differential clock transmission line is designed as a delay reference, the frequency of a fixed clock signal is set to be twice of a sampling holding frequency, the time difference delta T between two rising edges TCD _ OUTP and TCD _ OUTN output by a TCD is controlled within the range of 0-pi/f _ tline through a discharge path, so that when the time difference delta T is smaller than the traveling wave transmission time between adjacent output ports TAP on a transmission line, the phase difference detection output is all-0 digital codes, and when the time difference delta T is equal to pi/f _ tline, the phase difference detection circuit inputs the phase difference for two times by 180 degrees, the phase difference output is all-1 digital codes, wherein the number of the output digital codes 1 and the difference value of the time difference delta T are in linear proportion, and the TDC quantization encoding mode taking transmission line delay as the reference is realized.

Example two

The invention provides a coding method based on transmission line traveling wave quantization, which uses an ultra-high speed time coder of embodiment I, and the coding method comprises the following steps:

the method comprises the following steps: determining a parameter of the differential clock transmission line based on a time difference Δ T between a first output signal TCD _ OUTP and a second output signal TCD _ OUTN outputted by the VTC outputted by the time converter;

wherein the parameters include: a first spacing between the first differential clock transmission line and the second differential clock transmission line, a second spacing between the inner metal layer and the shielding layer of each differential clock transmission line, and a line width of the differential clock transmission lines;

step two: when the differential clock transmission lines after the parameter determination transmit the delay clock signals, each delay quantization unit is obtained, when the first delay clock signal CLK _ P transmitted by the first differential clock transmission line arrives, the first output signal TCD _ OUTP and the second output signal TCD _ OUTN are sampled for the first time, when the second delay clock signal CLK _ M transmitted by the second differential clock transmission line arrives, the first output signal TCD _ OUTP and the second output signal TCD _ OUTN are sampled for the second time, and the digital coding circuit correspondingly codes the output of each delay quantization unit and converts the output into a binary coding output result.

Determining a parameter of the differential clock transmission line based on a time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN output by the VTC output of the time converter includes:

the method comprises the following steps: a time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN output based on the VTC output from the time converter;

step two: determining a maximum value in the time difference Δ T;

step three: determining the transmission time delay of the port of each differential clock transmission line connected with the adjacent delay quantization unit based on the maximum value and the precision of the ultra-high speed time encoder;

step four: based on the transmission delay, parameters of the differential clock transmission line are determined.

A first distance between the first differential clock transmission line Spine _ clkp and the second differential clock transmission line Spine _ clkp is converted into a parasitic capacitance C1, and the parasitic inductance is L1. The second distance between the inner protective layer and the metal layer of each differential clock transmission line is converted into a parasitic capacitance C2, and the line width is converted into a parasitic capacitance C3, and the wave velocity in the known lossless transmission line is calculated as follows:

assuming that the transmission line distance between the Tap _ p < n > port and the Tap _ p < n +1> port of the first differential clock transmission line is L _ tline, the transmission delay between the two Tap ports can be calculated as follows:

after the differential input signal passes through the sample-and-hold circuit, the voltage of the upper plate of the capacitor CAP _ P is Vip, the voltage of the upper plate of the capacitor CAP _ N is Vin, and after CLK _ VTC is enabled, the capacitors CAP _ P and CAP _ N are respectively uniformly discharged by the current sources IDC _ P and IDC _ NElectric, wherein current sources IDC _ P and IDC _ N are i_dc. Therefore, the voltage of the capacitor plate varies as shown in FIG. 7, when the voltage drops to the threshold value, the threshold point V _ th of the detection circuit generates two pulse signals TCD _ OUTP and TCD _ OUTM,

the time difference Δ T between the first output signal TCD _ OUTP and the second output signal TCD _ OUTN is:

maxΔT＝2^a-1·t_delay

therefore, a is the precision of the TDC, and when Δ T is maximum, the difference between the input VIP and VIN is maximum, and the first distance, the second distance, and the line width are solved.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.