阅读说明：本技术 一种时钟恢复系统电路 (Clock recovery system circuit ) 是由 鲍宜鹏 史兴强 杨晓刚 苗韵 傅建军 于 2021-08-03 设计创作，主要内容包括：本发明公开一种时钟恢复系统电路,属于集成电路领域,用于SOC系统时钟的恢复控制,其包括N位多路选择器、异或门、三分之二数字滤波器、M位分频器、三输入或门、G位计数器、L位计数器、比较单元、校准单元、精度单元；本电路可提供脉冲极性可控、软件可控、精度可控、可定时灵活的时钟校准系统；其中,通过极性控制信号SYNCPOL,控制检查边沿。三分之二数字滤波器获得稳定的脉冲信号,用于俘获L位计数器方向和数值,比较单元的结果控制校准的增加或减小的大小,精度单元控制最终校准值。(The invention discloses a clock recovery system circuit, which belongs to the field of integrated circuits and is used for recovery control of SOC system clocks, and the clock recovery system circuit comprises an N-bit multiplexer, an exclusive-OR gate, a two-thirds digital filter, an M-bit frequency divider, a three-input OR gate, a G-bit counter, an L-bit counter, a comparison unit, a calibration unit and a precision unit; the circuit can provide a clock calibration system with controllable pulse polarity, controllable software, controllable precision and flexible timing; wherein the check edge is controlled by a polarity control signal SYNCPOL. The two-thirds digital filter obtains a stable pulse signal for capturing the direction and the value of the L-bit counter, the result of the comparison unit controls the increasing or decreasing size of the calibration, and the precision unit controls the final calibration value.)

1. A clock recovery system circuit provides stable clock for SOC chip, which is characterized in that the clock recovery system circuit comprises an N-bit multiplexer, an exclusive-OR gate, a two-thirds digital filter, an M-bit frequency divider, a three-input OR gate, a G-bit counter, an L-bit counter, a comparison unit, a calibration unit and a precision unit;

the N-bit multiplexer selects a clock source, and the output end of the N-bit multiplexer is simultaneously connected with one end of the exclusive-OR gate and the G-bit counter; the other end of the exclusive-or gate is connected with a control signal SYNCPOL; the output end of the exclusive-OR gate is connected with a two-thirds digital filter, and the output end of the two-thirds digital filter is connected with an M-bit frequency divider;

three input ends of the three-input OR gate are respectively connected with the output end of the G-bit counter, the output end of the M-bit frequency divider and the software pulse signal SOFT _ PLUS, and the output end of the three-input OR gate is connected with the L-bit counter and the calibration unit;

the first input end of the comparison unit is connected with the frequency error limit value FILIM, the second input end of the comparison unit is connected with the output end of the OR gate, and the output end of the comparison unit is connected with the calibration unit; the calibration unit is connected with the precision unit, the system clock and the L-bit counter in sequence, the L-bit counter outputs the FEDIR value to the input end of the calibration unit, and the L-bit counter outputs the FECAP value to the second input end of the comparison unit.

2. The clock recovery system circuit of claim 1 wherein the N-bit multiplexer provides a different clock source for the entire system.

3. The clock recovery system circuit of claim 1 wherein the exclusive or gate is capable of flexibly controlling the polarity of the control signal SYNCPOL, the clock recovery system circuit providing the system with detection signals of different edges.

4. The clock recovery system circuit of claim 1 wherein said two-thirds digital filter is configured to filter out any interference to make the synchronization signal more stable.

5. The clock recovery system circuit of claim 1 wherein the M-bit frequency divider programmably binary prescales the input synchronous clock source to obtain a reasonable frequency range of the synchronous signal.

6. The clock recovery system circuit of claim 1, wherein the three input or gate is clocked through the system and provides a pulse generated by software programming or a pulse through an M-bit divider.

7. The clock recovery system circuit of claim 1 wherein the L-bit counter is an L-bit down or up counter driven by the system clock for recording the frequency error.

8. The clock recovery system circuit of claim 1, wherein the comparison unit is configured to compare a frequency error limit value, FILIM, of the software input to the FECAP value of the capture L-bit counter.

9. The clock recovery system circuit of claim 1, wherein the calibration unit is configured for clock frequency calibration, and wherein the calibration value is sized based on the result output by the comparison unit and the count direction of the capture L-bit counter.

10. The clock recovery system circuit of claim 1, wherein the precision unit is configured to control the precision of the calibration of the clock frequency, adjust the time taken to calibrate the frequency based on the magnitude of the precision, and adjust the precision of the calibrated frequency.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a clock recovery system circuit.

Background

Along with the popularization of intelligent wearable equipment and intelligent hardware and the rise of the internet of things, the SOC chip is widely applied to the fields of consumer electronics, industrial control, medical equipment, artificial intelligence and the like, and the application environment of the SOC chip is worse and worse, so that higher and higher requirements are provided for the clock of the SOC chip.

The existing clock recovery method for SOC chip: firstly, the system clock recovery of the SOC chip completely depends on the precision and the process of PLL or RC oscillator design, and the frequency output can be kept stable under certain environmental conditions; secondly, the frequency of the system clock is firstly tested, the tested parameter value is written into a memory and is applied to a PLL or an RC to ensure an oscillator, and the output frequency is ensured to be recovered to the frequency required by the system.

With the existing first clock recovery method, the following disadvantages are encountered: first, the design structure is complex. For example, units such as temperature compensation are required; secondly, when the environmental factors such as temperature, voltage and the like exceed the range included by the design, the recovery cannot be realized.

With the second type of test method, the following disadvantages are encountered: firstly, each chip test increases the test cost; secondly, it is not flexible enough, and each time the environment changes, it needs to be recalibrated, and then the tested parameter values are written into the memory.

Disclosure of Invention

The present invention is directed to a clock recovery system circuit to solve the above problems.

In order to solve the technical problem, the invention provides a clock recovery system circuit which provides a stable clock for an SOC chip and comprises an N-bit multiplexer, an exclusive-OR gate, a two-thirds digital filter, an M-bit frequency divider, a three-input OR gate, a G-bit counter, an L-bit counter, a comparison unit, a calibration unit and a precision unit;

the N-bit multiplexer selects a clock source, and the output end of the N-bit multiplexer is simultaneously connected with one end of the exclusive-OR gate and the G-bit counter; the other end of the exclusive-or gate is connected with a control signal SYNCPOL; the output end of the exclusive-OR gate is connected with a two-thirds digital filter, and the output end of the two-thirds digital filter is connected with an M-bit frequency divider;

three input ends of the three-input OR gate are respectively connected with the output end of the G-bit counter, the output end of the M-bit frequency divider and the software pulse signal SOFT _ PLUS, and the output end of the three-input OR gate is connected with the L-bit counter and the calibration unit;

the first input end of the comparison unit is connected with the frequency error limit value FILIM, the second input end of the comparison unit is connected with the output end of the OR gate, and the output end of the comparison unit is connected with the calibration unit; the calibration unit is connected with the precision unit, the system clock and the L-bit counter in sequence, the L-bit counter outputs the FEDIR value to the input end of the calibration unit, and the L-bit counter outputs the FECAP value to the second input end of the comparison unit.

Optionally, the N-bit multiplexer provides different clock sources for the entire system.

Optionally, the xor gate can flexibly control the polarity of the control signal SYNCPOL, and the clock recovery system circuit can provide detection signals of different edges for the system.

Optionally, the two-thirds digital filter is used for filtering any interference, so that the synchronization signal is more stable.

Optionally, the M-bit frequency divider performs programmable binary prescaler on the input synchronous clock source to obtain a synchronous signal within a reasonable frequency range.

Optionally, the three-input or gate is clocked through the system and provides a pulse generated by software programming or a pulse through an M-bit divider.

Optionally, the L-bit counter is an L-bit down or up counter driven by a system clock for recording the frequency error.

Optionally, the comparing unit is configured to compare the frequency error limit value FILIM input by the software with the FECAP value of the capture L-bit counter.

Optionally, the calibration unit is configured to calibrate a clock frequency, and determine a size of the calibration value according to a result output by the comparison unit and a count direction of the capture L-bit counter.

Optionally, the precision unit is configured to control the precision of the clock frequency calibration, and adjust the time used for calibrating the frequency and the precision of the calibrated frequency according to the precision.

The clock recovery system circuit provided by the invention is used for recovery control of an SOC (system on chip) system clock, and comprises an N-bit multiplexer, an exclusive-OR gate, a two-thirds digital filter, an M-bit frequency divider, a three-input OR gate, a G-bit counter, an L-bit counter, a comparison unit, a calibration unit and a precision unit; the circuit can provide a clock calibration system with controllable pulse polarity, controllable software, controllable precision and flexible timing; wherein the check edge is controlled by a polarity control signal SYNCPOL. The two-thirds digital filter obtains a stable pulse signal for capturing the direction and the value of the L-bit counter, the result of the comparison unit controls the increasing or decreasing size of the calibration, and the precision unit controls the final calibration value.

Drawings

Fig. 1 is a schematic circuit diagram of a timing recovery system according to the present invention;

fig. 2 is a schematic diagram of the counting behavior of the timing recovery system circuit provided by the present invention.

Detailed Description

The timing recovery system circuit according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a clock recovery system circuit which provides a stable clock for an SOC chip. The structure of the clock recovery system circuit is shown in fig. 1, and comprises an N-bit multiplexer, an exclusive or gate, a two-thirds digital filter, an M-bit frequency divider, a three-input or gate, a G-bit counter, an L-bit counter, a comparison unit, a calibration unit and a precision unit; the N-bit multiplexer selects a clock source, and the output end of the N-bit multiplexer is simultaneously connected with one end of the exclusive-OR gate and the G-bit counter; the other end of the exclusive-or gate is connected with a control signal SYNCPOL, and the control signal SYNCPOL is used for controlling the polarity of an input clock source and customizing rising edge sampling or falling edge sampling; the output end of the exclusive-OR gate is connected with a two-thirds digital filter, and the output end of the two-thirds digital filter is connected with an M-bit frequency divider; three input ends of the three-input OR gate are respectively connected with the output end of the G-bit counter, the output end of the M-bit frequency divider and the software pulse signal SOFT _ PLUS, and the output end of the three-input OR gate is connected with the L-bit counter and the calibration unit; the first input end of the comparison unit is connected with the FELIM value, the second input end of the comparison unit is connected with the output end of the OR gate, and the output end of the comparison unit is connected with the calibration unit; the calibration unit is connected with the precision unit, the system clock and the L-bit counter in sequence, the L-bit counter outputs the FEDIR value to the input end of the calibration unit, and the L-bit counter outputs the FECAP value to the second input end of the comparison unit.

The N-bit multiplexer can control the selection of a synchronous source, such as a GPIO external input signal, an LSE crystal oscillator clock and the like; the selected synchronous source will XOR the polarity control signal, select rising edge or falling edge to capture data. The exclusive-or gate can flexibly control the polarity of the control signal SYNCPOL, and the clock recovery system circuit can provide detection signals of different edges for a system. The two-thirds digital filter collects an input clock source to obtain a stable synchronous pulse signal. The M-bit frequency divider may perform programmable binary prescaler on the synchronization source to obtain a synchronization signal within a reasonable frequency range. The three-input OR gate controls the whole system in a timing mode, provides pulses generated by software programming or pulses passing through the M-bit frequency divider, and does not need to detect all the time when the environment of the chip does not change greatly within a certain time so as to save power consumption; the pulse signal may also be controlled by software programming. The L-bit counter is an L-bit down or up counter driven by the system clock for recording the frequency error, the direction and value of the L-bit counter are captured by the SYNC signal and used for the comparison unit and the calibration unit. The comparison unit compares the FECAP value of the L-bit counter captured by the SYNC signal pulse with the frequency error limit value FILIM, the value of the FILIM can be controlled by software, the counting result is used for controlling the size of the calibration value, and the captured counting direction is used for controlling the increase or decrease of the calibration value. And finally, controlling the final calibration value by the precision unit and judging a successful mark.

Fig. 2 shows the counting behavior of the L-bit counter of the circuit of the clock recovery system, which is a frequency error counter, and the counting behavior has the following modes:

mode 1, a reloading stage: the frequency error counter RELOADs the RELOAD value when each SYNC synchronization event occurs, the RELOAD value can be flexibly configured through software, a reasonable RELOAD value can be obtained according to the ratio of the target frequency to the synchronization source frequency, and the RELOAD value can be obtained according to the following formula:

where Ftarget is the target frequency and Fsync is the synchronization frequency.

Mode 2, the decrement phase: after the frequency error counter is reloaded, the decrementing phase is first entered until a zero value is reached, at which point the expected synchronization event is generated.

Mode 3, the increment phase: after reaching the zero value, it will then increment the count until it reaches the value C × FELIM, in which case it will eventually stop counting, generating a MISS (loss of pulse) event if no SYNC pulse is received in the meantime; where C is the error limit coefficient.

When a SYNC event is detected, the actual value and direction of the frequency error counter is captured as FECAP and FEDIR, and when a SYNC pulse event is detected during the countdown phase, meaning that the actual frequency is less than the target frequency, the frequency should be calibrated to be large. When the count detects a SYNC pulse event during the count up period, meaning that the actual frequency is greater than the target frequency, the frequency should be calibrated to be smaller.

The captured FECAP value will be compared to a set of limits and the result of the comparison used to generate a status indication and control the automatic fine tuning.

When the frequency error is lower than the tolerance limit value FELIM, the calibration value is not adjusted, and an OK event is fed back.

When the frequency error is higher than or equal to the tolerance limit value FELIM and is less than the warning limit value A FELIM, a certain fine adjustment operation is required, but only one-step fine adjustment is needed, the calibration value is increased or decreased by 1X, and an OK event is fed back; wherein A is a warning limit coefficient; and X is a fine adjustment step size coefficient.

When the frequency error is higher than or equal to the warning limit A and is less than the danger limit B, the fine adjustment operation which is stronger is required, the calibration value is increased or decreased by 2Y, and a WARN event is fed back; wherein B is a danger limit coefficient, and Y is a strong fine adjustment step length coefficient.

When the frequency error is higher than or equal to a dangerous limit value B × FELIM and is smaller than an error limit value C × FELIM, the fact that ultra-strong adjusting operation is needed is meant, the calibration value of the frequency error is increased or decreased by U × Z, and a SERI _ WARN event is fed back; wherein C is an error limit coefficient, U is a self-defined step length, which is generally selected to be more than or equal to 3, and Z is an ultra-strong fine-tuning step length coefficient.

The precision unit can define the values of parameters A, B, C, U, Z, X and Y and carry out multiplication operation, and the operation result is used for controlling the calibration precision and the calibration times.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.