Transistor and preparation method thereof
阅读说明:本技术 晶体管及其制备方法 (Transistor and preparation method thereof ) 是由 杨健 魏鸿基 王勇 郑坤 于 2019-11-29 设计创作,主要内容包括:本申请提供了一种晶体管及其制备方法,涉及半导体和通信技术领域。所述晶体管包括衬底和依次形成在所述衬底上的基极平台和基极接触电极;所述基极平台的两侧边缘设置有缺口,以使所述基极接触电极超出所述基极平台顶面的边缘。这样,能够在后续加工中对应减小Cbc的面积,提高功率增益。(The application provides a transistor and a preparation method thereof, and relates to the technical field of semiconductors and communication. The transistor comprises a substrate, and a base electrode platform and a base electrode contact electrode which are sequentially formed on the substrate; and notches are arranged on the edges of the two sides of the base electrode platform, so that the base electrode contact electrode exceeds the edge of the top surface of the base electrode platform. Thus, the area of Cbc can be reduced correspondingly in the subsequent processing, and the power gain can be improved.)
1. A transistor, characterized in that it comprises a substrate (110) and a base mesa (111) and a base contact electrode (124) formed in succession on said substrate (110); notches (120) are provided at both side edges of the base mesa (111) so that the base contact electrode (124) exceeds the edge of the top surface of the base mesa (111).
2. The transistor of claim 1, wherein the distance between the edge of the base mesa (111) and the edge of the base contact electrode (124) is D1, and D1 has a value in the range of: 0.2-0.8 μm.
3. The transistor of claim 1, wherein the notch (120) comprises a first notch (140), an edge of the first notch (140) meeting an edge of the base contact electrode (124).
4. The transistor of claim 3, wherein the notch (120) comprises a second notch (150), the second notch (150) being disposed at a side of the first notch (140), an edge of the second notch (150) being spaced apart from an edge of the base contact electrode (124) by a distance D2, D2 having a value in a range of: 0.2-0.8 μm.
5. Transistor according to claim 1, characterized in that the base mesa (111) comprises a collector contact electrode (112), a pedestal (113) and an epitaxial layer (114) arranged in this order from bottom to top.
6. A preparation method of a transistor is characterized by comprising the following steps:
sequentially forming a base mesa (111) and a base contact electrode (124) on a substrate (110);
and etching off partial materials on two side edges of the top surface of the base platform (111) to form a gap (120) so that the base contact electrode (124) exceeds the edge of the top surface of the base platform (111).
7. The method for manufacturing the transistor according to claim 6, wherein the notch (120) comprises a first notch (140) and a second notch (150), the second notch (150) is disposed at a side of the first notch (140), and the second notch (150) is formed by wet etching.
8. The preparation method of the transistor according to claim 7, wherein in the solution adopted in the wet etching, the ratio range of phosphoric acid to hydrogen peroxide is as follows: 3: 1-30: 1.
9. the method for manufacturing a transistor according to claim 7, wherein in the wet etching, a range of a ratio of a forward etching rate to a lateral etching rate is: 1: 1-5: 1.
Technical Field
The application relates to the technical field of semiconductors and communication, in particular to a transistor and a preparation method thereof.
Background
The existing power amplifier adopts a gallium arsenide heterojunction bipolar transistor (GaAsHBT), and has the advantages of high-frequency characteristic, high power density, high working efficiency, good linearity and the like. Among them, one of the main reasons for limiting the linearity of the Heterojunction Bipolar Transistor (HBT) is that the collector junction capacitance (Cbc) inside the HBT has a large area.
However, in the HBT, the area of Cbc is closely related to the area of the base mesa, and in the current mainstream process, no matter wet etching or dry etching is adopted, the edge of the top surface of the base mesa exceeds the edge of the base contact electrode, so the area of the base mesa is also large, and the area of Cbc is also large, thereby resulting in a small Power Gain (Power Gain).
Disclosure of Invention
In view of the above, the present application provides a transistor and a method for fabricating the same to improve the above-mentioned problems.
The embodiment of the application provides a transistor, which comprises a substrate (110), and a base platform (111) and a base contact electrode (124) which are sequentially formed on the substrate (110); notches (120) are provided at both side edges of the base mesa (111) so that the base contact electrode (124) exceeds the edge of the top surface of the base mesa (111).
In the transistor of the above embodiment, the distance between the edge of the base mesa (111) and the edge of the base contact electrode (124) is D1, and the value range of D1 is: 0.2-0.8 μm.
In the transistor of the above embodiment, the notch (120) includes a first notch (140), and an edge of the first notch (140) is connected to an edge of the base contact electrode (124).
In the transistor of the above embodiment, the notch (120) includes a second notch (150), the second notch (150) is disposed on a side of the first notch (140), a distance between an edge of the second notch (150) and an edge of the base contact electrode (124) is D2, and a value range of D2 is: 0.2-0.8 μm.
In the transistor of the above embodiment, the base platform (111) includes a collector contact electrode (112), a pedestal (113), and an epitaxial layer (114) sequentially disposed from bottom to top.
The embodiment of the application provides a preparation method of a transistor, which comprises the following steps:
sequentially forming a base mesa (111) and a base contact electrode (124) on a substrate (110);
and etching off partial materials at two side edges of the base platform (111) to form a gap (120) so that the base contact electrode (124) exceeds the edge of the top surface of the base platform (111).
In the preparation method of the transistor according to the above embodiment, the notch (120) includes a first notch (140) and a second notch (150), the second notch (150) is disposed on a side surface of the first notch (140), and the second notch (150) is formed by wet etching.
In the preparation method of the transistor in the above embodiment, in the solution used in the wet etching, the ratio of phosphoric acid to hydrogen peroxide is in the range: 3: 1-30: 1.
in the method for manufacturing a transistor according to the embodiment, in the wet etching, a range of a ratio of a forward etching rate to a lateral etching rate is as follows: 1: 1-5: 1.
the transistor and the preparation method thereof provided by the embodiment of the application have the beneficial effects that:
the base electrode platform is firstly positioned on the two side edges of the base electrode platform (111) to form notches, so that the width of the base electrode platform is reduced, the area of the base electrode platform is reduced, the base electrode contact electrode (124) exceeds the edge of the top surface of the base electrode platform (111), the area of Cbc can be correspondingly reduced in subsequent processing, and the power gain (Powergain) is improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a flowchart of a method for manufacturing a transistor according to an embodiment of the present disclosure.
Fig. 2 is a flow chart of forming a base mesa and a base.
Fig. 3 to 9 are schematic structural diagrams in the process of manufacturing a transistor.
Icon: 100-transistors; 110-a substrate; a 111-base mesa; 112-collector contact electrode; 113-a base; 114-an epitaxial layer; 120-notch; 121-emitter mesa; 122-emitter contact electrode; 123-a silicon nitride layer; 124-base contact electrode; 130-a photoresist layer; 140-a first gap; 150-second notch.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, in the HBT manufacturing process, no matter wet etching or dry etching is adopted, the edge of the top surface of the base mesa exceeds the edge of the base contact electrode, so the area of the base mesa is also large, and the area of Cbc is also large, resulting in a small Power Gain (Power Gain).
Note that the area referred to in this embodiment refers to the area corresponding to the cross section of the layer structure, i.e., the area of a section perpendicular to the paper surface in fig. 3 to 9. For example, the area of the base mesa refers to the area of the top surface of the base mesa.
Embodiments of the present application provide a transistor and a method for manufacturing the same, which can enable a base contact electrode to exceed an edge of a top surface of a base platform, and accordingly can correspondingly reduce an area of Cbc in subsequent processing, and improve power gain (PowerGain).
Referring to fig. 1, a method for manufacturing a
s1:
In this embodiment,
s11: referring to fig. 3, a
The material of the
S12: a
The material of the
S13: a
The material of the
S14: an
The material of the
S15: referring to fig. 4, a
Wherein the
The material of the
S16: a
Wherein
S17: a
S18: referring to fig. 5, the
Here, the etching is dry etching, light is exposed from the direction of the arrow in fig. 5, and the portion of the
S2: referring to fig. 6, portions of the material on the two side edges of the
The etching here is dry etching, light is exposed from the direction of the arrow in fig. 6, the portion of the
The side surface of the
The depth of the
In this embodiment, the
S3: referring to fig. 7, the side surfaces of
Wherein, the
Referring to fig. 8, experimental tests show that the lateral etching amount of the
In this embodiment, the
It is noted that, as long as the
In this embodiment, wet etching is used to simultaneously etch from the forward direction and the lateral direction of
S4: referring to fig. 9, the
After the
The present embodiment further provides a
The features of each layer structure formed in the above manufacturing method are included in each layer structure of the
The
The
first, a
The technical core mainly expressed in the embodiment is as follows: after one dry etch of
Only an example of applying the manufacturing method of the
The
It should be noted that the numerical values mentioned in the present application, including the length value, the ratio range, the etching rate ratio, etc., are only reliable numerical values obtained by the applicant through experiments and calculation, and are not limited to only these values. Those skilled in the art may make further experiments based on the scheme of the present application to obtain other values with similar effects, which do not depart from the core of the present application and should also fall within the scope of the protection claimed in the present application.
The materials used for the layer structures and the precursors in the present application are only the more reliable materials obtained by the applicant through experiments, and are not strictly limited to only use these materials. Those skilled in the art may make further experiments based on the solution of the present application to obtain other materials with similar effects, which do not depart from the core of the present application and should fall within the protection scope of the present application.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.