阅读说明：本技术 横向扩散金属氧化物半导体器件及其制造方法 (Lateral diffusion metal oxide semiconductor device and manufacturing method thereof ) 是由 高桦 孙贵鹏 罗泽煌 于 2018-08-01 设计创作，主要内容包括：本发明涉及一种横向扩散金属氧化物半导体器件及其制造方法。所述横向扩散金属氧化物半导体器件包括：衬底；漂移区,设置在所述衬底中；栅极结构,设置在所述衬底上,包括栅极介电层和栅极介电层上的栅极层；漏极区,设置在所述栅极结构的一侧的衬底中,与所述漂移区相接触；源极区,设置在所述栅极结构的另一侧的衬底中；及类栅结构,设置在所述漂移区上方、所述栅极结构与所述漏极区之间,所述类栅结构的材质与所述栅极层相同,所述类栅结构与所述栅极层之间绝缘。本发明通过在栅极层与漏极区之间的漂移区上方设置与栅极层之间绝缘的类栅结构,能够改善器件的HCI特性。(The invention relates to a lateral diffusion metal oxide semiconductor device and a manufacturing method thereof. The laterally diffused metal oxide semiconductor device includes: a substrate; a drift region disposed in the substrate; the grid structure is arranged on the substrate and comprises a grid dielectric layer and a grid layer on the grid dielectric layer; the drain region is arranged in the substrate on one side of the grid structure and is in contact with the drift region; the source region is arranged in the substrate on the other side of the gate structure; and the similar gate structure is arranged above the drift region and between the gate structure and the drain region, the material of the similar gate structure is the same as that of the gate layer, and the similar gate structure is insulated from the gate layer. According to the invention, the gate-like structure insulated from the gate electrode layer is arranged above the drift region between the gate electrode layer and the drain electrode region, so that the HCI characteristic of the device can be improved.)

1. A laterally diffused metal oxide semiconductor device, comprising:

a substrate;

a drift region disposed in the substrate;

the grid structure is arranged on the substrate and comprises a grid dielectric layer and a grid layer on the grid dielectric layer;

the drain region is arranged in the substrate on one side of the grid structure and is in contact with the drift region;

the source region is arranged in the substrate on the other side of the gate structure; and

the similar gate structure is arranged above the drift region and between the gate structure and the drain region, the material of the similar gate structure is the same as that of the gate layer, and the similar gate structure is insulated from the gate layer.

2. The laterally diffused metal oxide semiconductor device of claim 1, further comprising:

the metal silicide blocking layer covers the gate-like structure and covers the surface of the drift region between the gate-like structure and the drain region; and

and the metal silicide is formed on the surface of the drain region, the surface of the grid layer and the surface of the source region which are not covered by the metal silicide barrier layer.

3. The laterally diffused metal oxide semiconductor device of claim 2, further comprising:

the insulating layer is arranged on the grid layer, the metal silicide barrier layer, the drain region and the source region;

a metal field plate disposed on the insulating layer; and

a first contact hole contacting the metal field plate to lead out the metal field plate.

4. Laterally diffused metal oxide semiconductor device according to claim 2,

the metal silicide barrier layer comprises an oxide layer and an oxide etching barrier layer on the oxide layer, the transverse diffusion metal oxide semiconductor device further comprises an A contact hole, and the bottom of the A contact hole is located in the oxide etching barrier layer.

5. A method for manufacturing a laterally diffused metal oxide semiconductor device comprises the following steps:

obtaining a substrate, wherein a drift region is formed in the substrate;

forming a gate dielectric layer on the substrate;

forming a gate material on the gate dielectric layer;

photoetching and etching the grid material by using a first photoetching plate to form a grid layer and a grid-like structure separated from the grid layer, wherein the grid-like structure is arranged above the drift region, and the first photoetching plate comprises a grid layer pattern and a grid-like structure pattern; and

and forming a drain region and a source region, wherein the drain region is formed in the substrate on one side of the gate layer and is in contact with the drift region, the source region is formed in the substrate on the other side of the gate layer, and the gate-like structure is positioned between the gate layer and the drain region.

6. The method of claim 5, further comprising the steps of, after the step of forming the drain and source regions:

forming a metal silicide blocking layer, wherein the metal silicide blocking layer covers the similar gate structure and also covers the surface of the drift region between the similar gate structure and the drain region; and

and forming metal silicide on the surface of the drain region, the surface of the grid layer and the surface of the source region which are not covered by the metal silicide barrier layer.

7. The method of claim 6, further comprising the steps of:

forming an insulating layer on the gate layer, the metal silicide barrier layer, the drain region and the source region; and

a metal field plate is formed on the insulating layer.

8. The method of claim 7, further comprising the step of forming a first contact hole in contact with the metal field plate and leading the metal field plate out.

9. The method as claimed in claim 6, wherein the metal silicide blocking layer comprises an oxide layer and an oxide etching blocking layer on the oxide layer, and further comprising a step of forming a first contact hole after the step of forming the metal silicide on the surface of the drain region, the surface of the gate layer and the surface of the source region which are not covered by the metal silicide blocking layer, wherein the bottom of the first contact hole is located in the oxide etching blocking layer.

10. The method of claim 5, wherein the step of forming a gate material over the gate dielectric layer is depositing polysilicon.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a laterally diffused metal oxide semiconductor device and a manufacturing method of the laterally diffused metal oxide semiconductor device.

Background

The Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device is easy to form a higher channel lateral electric field and an oxide layer longitudinal electric field due to the fact that the LDMOS device works under higher voltage, so that carriers are subjected to impact ionization in the conveying process, and extra electron-hole pairs are generated. Part of the hot carriers enter the gate oxide layer, so that the threshold voltage of the device is increased, the saturation current and the carrier mobility are reduced, and the effect of Hot Carrier Injection (HCI) is called.

Therefore, the HCI effect is generally as small as possible while ensuring other parameters of the device (e.g., breakdown voltage, on-resistance, etc.).

Disclosure of Invention

In view of this, it is desirable to provide a laterally diffused metal oxide semiconductor device capable of improving HCI characteristics.

A laterally diffused metal oxide semiconductor device, comprising: a substrate; a drift region disposed in the substrate; the grid structure is arranged on the substrate and comprises a grid dielectric layer and a grid layer on the grid dielectric layer; the drain region is arranged in the substrate on one side of the grid structure and is in contact with the drift region; the source region is arranged in the substrate on the other side of the gate structure; and the similar gate structure is arranged above the drift region and between the gate structure and the drain region, the material of the similar gate structure is the same as that of the gate layer, and the similar gate structure is insulated from the gate layer.

In one embodiment, the method further comprises the following steps: the metal silicide blocking layer covers the gate-like structure and covers the surface of the drift region between the gate-like structure and the drain region; and the metal silicide is formed on the surface of the drain region, the surface of the grid layer and the surface of the source region which are not covered by the metal silicide barrier layer.

In one embodiment, the method further comprises the following steps: the insulating layer is arranged on the grid layer, the metal silicide barrier layer, the drain region and the source region; a metal field plate disposed on the insulating layer; a first contact hole contacting the metal field plate to lead out the metal field plate.

In one embodiment, the metal silicide blocking layer comprises an oxide layer and an oxide etching blocking layer on the oxide layer, and the lateral diffusion metal oxide semiconductor device further comprises a first contact hole, wherein the bottom of the first contact hole is located in the oxide etching blocking layer.

According to the lateral diffusion metal oxide semiconductor device, the grid-like structure insulated from the grid layer is arranged above the drift region between the grid layer and the drain region, so that the HCI (hydrogen storage interface) characteristics of the device can be improved.

It is also desirable to provide a method of fabricating a laterally diffused metal oxide semiconductor device.

A method for manufacturing a laterally diffused metal oxide semiconductor device comprises the following steps: obtaining a substrate, wherein a drift region is formed in the substrate; forming a gate dielectric layer on the substrate; forming a gate material on the gate dielectric layer; photoetching and etching the grid material by using a first photoetching plate to form a grid layer and a grid-like structure separated from the grid layer, wherein the grid-like structure is arranged above the drift region, and the first photoetching plate comprises a grid layer pattern and a grid-like structure pattern; and forming a drain region and a source region, wherein the drain region is formed in the substrate on one side of the gate layer and is in contact with the drift region, the source region is formed in the substrate on the other side of the gate layer, and the gate-like structure is positioned between the gate layer and the drain region.

In one embodiment, after the step of forming the drain region and the source region, the method further includes the following steps: forming a metal silicide blocking layer, wherein the metal silicide blocking layer covers the similar gate structure and also covers the surface of the drift region between the similar gate structure and the drain region; and forming metal silicide on the surface of the drain region, the surface of the grid layer and the surface of the source region which are not covered by the metal silicide barrier layer.

In one embodiment, the method further comprises the following steps: forming an insulating layer on the gate layer, the metal silicide barrier layer, the drain region and the source region; a metal field plate is formed on the insulating layer.

In one embodiment, the method further comprises the step of forming a first contact hole in contact with the metal field plate and leading out the metal field plate.

In one embodiment, the metal silicide blocking layer comprises an oxide layer and an oxide etching blocking layer on the oxide layer, and the method further comprises a step of forming a first contact hole after the step of forming the metal silicide on the surface of the drain region, the surface of the gate layer and the surface of the source region which are not covered by the metal silicide blocking layer, wherein the bottom of the first contact hole is positioned in the oxide etching blocking layer.

In one embodiment, the step of forming the gate material on the gate dielectric layer is depositing polysilicon.

According to the manufacturing method of the lateral diffusion metal oxide semiconductor device, the pattern of the first photoetching plate is reasonably designed, and the similar gate structure separated from the gate layer is arranged above the drift region between the gate layer and the drain region, so that the HCI characteristic of the device can be improved. The method does not need to increase a photoetching plate and does not have strict requirements on an online process. And the characteristics of the device can be finely adjusted only by adjusting the pattern of the first photoetching plate and correspondingly changing the characteristics of the gate-like structures such as size, number, spacing and the like, so that the HCI characteristics of the device can be more reasonably adjusted to meet the requirement of the reliability of the device.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a LDMOS device;

FIG. 2 is a flow chart of a method of fabricating a lateral diffused metal oxide semiconductor device in one embodiment;

fig. 3a to 3h are schematic cross-sectional views of a ldmos device in a manufacturing process according to an embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

Fig. 1 is a schematic structural diagram of a ldmos device in an embodiment, which includes a substrate 10, a drift region 20, a gate structure, a drain region 40, a source region 50, and a gate-like structure 66. Wherein the drift region 20 is provided in the substrate. A gate structure is disposed on the substrate 10, the gate structure including a gate dielectric layer 62 and a gate layer 64 on the gate dielectric layer 62. The drain region 40 is disposed in the substrate 10 on one side of the gate structure (in the substrate 10 disposed on the right side of the gate structure in fig. 1), in contact with the drift region 20; in one embodiment in the drift region 20. The source region 50 is disposed in the substrate 10 on the other side of the gate structure (in the substrate 10 disposed on the left side of the gate structure in fig. 1). A gate-like structure 66 is disposed over the drift region 20, between the gate structure and the drain region 40. The gate-like structure 66 is made of the same material as the gate layer 64, and in the embodiment shown in fig. 1, the gate layer 64 is made of polysilicon gate, and the gate-like structure 66 is made of polysilicon. In the embodiment shown in fig. 1, the number of gate-like structures 66 is 2, and in other embodiments, different numbers of gate-like structures 66, such as 1, 3, 4, etc., may be provided according to the specific situation and electrical parameter requirements of the device. The gate-like structures 66 are insulated from the gate layer 64, and particularly, the insulating medium may be filled between the gate-like structures 66 and the gate layer 64, and for embodiments in which the gate-like structures 66 are multiple, the insulating medium may also be filled between adjacent gate-like structures 66. The gate-like structure 66 can be used as a field plate, and the shape thereof is not limited, and generally, a shape which is easy to manufacture can be selected according to the implementation difficulty of the process.

In the laterally diffused metal oxide semiconductor device, the gate-like structure 66 insulated from the gate layer 64 is arranged above the drift region 20 between the gate layer 64 and the drain region 40, so that the HCI (hydrogen-induced interface) characteristics of the device can be improved. Meanwhile, the structure can correspondingly optimize the surface electric field intensity of the device to a certain degree, and meanwhile, the structure also has certain help for reducing the on-resistance of the device.

In one embodiment, the substrate 10 is a semiconductor substrate, and the material thereof may be undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. In the embodiment shown in fig. 1, the material of substrate 10 is monocrystalline silicon.

In one embodiment, the substrate 10 has the second conductivity type, the drift region 20 has the first conductivity type, and the drain region 40 and the source region 50 have the first conductivity type. In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

The substrate 10 may be a P-type semiconductor substrate or an N-type semiconductor substrate, for example, a P-type semiconductor substrate may be selected for an N-type high voltage device, and an N-type semiconductor substrate may be selected for a P-type high voltage device. In the embodiment shown in fig. 1, the substrate 10 is a P-type semiconductor substrate.

The drift region 20 has a different conductivity type depending on the type of the particular LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in fig. 1, the drift region 20 is an N-type drift region. In general, the doping concentration of the drift region 20 is low, which is lower than the doping concentration of the drain region 40 and the source region 50.

In one embodiment, the gate dielectric layer 62 may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 62 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).

In one embodiment, the gate layer 64 is a polysilicon material, and in other embodiments, a metal nitride, a metal silicide or a similar compound may be used as the material of the gate layer 64.

In one embodiment, the minimum distance between the gate-like structure 66 and the gate layer 64 (i.e., the closest linear distance of the gate-like structure 66 to the gate layer 64) is between 0.15 microns and 0.2 microns.

In the present embodiment, the drain region 40 and the source region 50 are the drain and source heavily doped with N-type doped ions.

In the embodiment shown in fig. 1, the LDMOS device further includes a metal Silicide block (SAB) layer 72. A metal silicide blocking layer 72 covers the gate-like structure 66 and also covers the surface of the drift region 20 between the gate-like structure 66 and the drain region 40. A metal silicide 42 is formed on the surface of the drain region 40, a metal silicide 65 is formed on the surface of the gate layer 64, and a metal silicide 52 is formed on the surface of the source region 50. The provision of a metal silicide may reduce contact resistance. Self-aligned metal silicide (salicide) is a relatively simple and convenient contact metallization process, but in the fabrication process of a semiconductor device, some regions require salicide process and some regions require non-self-aligned metal silicide (non-salicide) process, and for devices requiring non-salicide process, the characteristics of the salicide are utilized to cover the regions requiring non-salicide with a material that does not react with metal. Such a material for covering a non-salicide device is referred to as a salicide block film (SAB).

In one embodiment, the material of the metal silicide (including the metal silicide 42, the metal silicide 52, and the metal silicide 65) may be CoSix, NiSix, PtSix, or a combination thereof.

In one embodiment, the metal silicide block layer 72 comprises an oxide layer, such as silicon oxide. Further, the metal silicide blocking layer 72 may also be a multi-layer structure, for example, including an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top. In one embodiment, the nitride layer is silicon nitride. In one embodiment, the oxynitride layer is silicon oxynitride.

In the embodiment shown in fig. 1, the LDMOS device further comprises an insulating layer 74 and a metal field plate 80. An insulating layer 74 is disposed on the gate layer 64, the metal silicide block layer 72, the drain region 40 and the source region 50, and a metal field plate 80 is disposed on the insulating layer 74. The thickness of the insulating layer 74 can be adjusted according to the device characteristics, for example, decreasing the thickness of the insulating layer 74 can increase the depletion of the drift region, and increasing the thickness can decrease the depletion of the drift region. In one embodiment, the material of the insulating layer 74 is silicon oxide. The structure of the metal field plate 80 arranged on the insulating layer 74 can improve the surface electric field of the device and enhance the depletion of the drift region of the device, thereby improving the withstand voltage (BV) of the device. It is understood that in other embodiments, other field plate structures known in the art, such as electrode field plate structures (e.g., polysilicon electrode field plate structures), may be used or combined to improve the device surface electric field.

In one embodiment, a contact hole structure with a large width (named as a nail contact hole in this specification) is used instead of the structure in which the metal field plate 80 is provided on the insulating layer 74. In this embodiment, the metal silicide blocking layer 72 includes an oxide layer and an oxide etching blocking layer on the oxide layer, and the oxide etching blocking layer is configured to ensure that the bottom of the hole stays in the oxide etching blocking layer (so that the bottom of the hole does not etch into the oxide layer) when the first contact hole is etched, so that the depletion of the electric field in the drift region can be accurately adjusted by adjusting the thickness of the oxide layer, thereby improving the device characteristics. In one embodiment, the oxide layer is made of silicon oxide, and the oxide etch stop layer is made of nitride, such as silicon nitride. In one embodiment, the metal silicide blocking layer 72 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer stacked in this order from bottom to top. That is, the gate-like structure 66 is suitable for various field plate structures (e.g., the aforementioned insulating layer 74+ metal field plate 80, electrode field plate structure, first contact hole structure, etc.).

In the embodiment shown in fig. 1, the LDMOS device further comprises a first contact hole 92. The first contact hole 92 contacts the metal field plate 80 to lead out the metal field plate 80. In one embodiment, the first contact hole 92 leads the metal field plate 80 out and then to ground.

In the embodiment shown in fig. 1, the LDMOS device further comprises a second contact hole 94. The second contact hole 94 is electrically connected to the gate layer 64, and further, the second contact hole 94 is electrically connected to the metal silicide 65 to electrically connect to the gate layer 64, and the gate is led out. In the embodiment shown in fig. 1, the LDMOS device further comprises a third contact hole 96 and a fourth contact hole 98. The third contact hole 96 is electrically connected to the drain region 40, and further, the third contact hole 96 is electrically connected to the metal silicide 42 to electrically connect to the drain region 40. The fourth contact hole 98 is electrically connected to the source region 50, and further, the fourth contact hole 98 is electrically connected to the metal silicide 52 to electrically connect to the source region 50.

The first contact hole 92, the second contact hole 94, the third contact hole 96, the fourth contact hole 98 and the first contact hole are filled with a conductive material, wherein the conductive material may be any suitable conductive material known to those skilled in the art, including but not limited to a metal material; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.

In one embodiment, the first contact hole 92, the second contact hole 94, the third contact hole 96, the fourth contact hole 98 and the first contact hole may be filled with the same conductive material, such as tungsten metal, or may be filled with different conductive materials.

It will be appreciated that in embodiments where a first contact hole is provided, there is no need to provide an insulating layer 74 and a metal field plate 80, and therefore no need to provide a first contact hole 92.

In the embodiment shown in fig. 1, the LDMOS device further includes a body region 30. The body region 30 is located on a side of the gate layer 64 remote from the drift region 20 and is spaced from the drift region 20. Source regions 50 are formed in the body regions 30. The body region 30 has an opposite conductivity type to the drift region 20, i.e. the body region 30 has a second conductivity type. In the embodiment shown in fig. 1, body region 30 is a P-shaped body region.

In one embodiment, a body extraction region (not shown in fig. 1) of the same conductivity type as body region 30 may be provided in body region 30. For example, if the body region 30 is P-type, the body region extraction region may also be P-type, and the impurity doping concentration thereof is greater than that of the body region, for example, the body region extraction region is heavily doped with P-type impurities.

In the embodiment shown in fig. 1, the LDMOS device further comprises side walls 76. The spacers 76 are disposed on a side of the gate-like structure away from the gate-like structure 66, and are also disposed on a side of the gate-like structure 66 away from the gate-like structure (for the gate-like structure 66 embodiment, outside of the outermost one of the gate-like structures 66). The sidewall spacers 76 may be made of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

In one embodiment, a first contact hole is provided on at least a portion of the surface of the metal silicide block layer 72. The first contact hole may be partially located on the surface of the metal silicide blocking layer 72 above the gate layer 64, partially located on the surface of the metal silicide blocking layer 72 above the sidewall 76, and partially located on the surface of the metal silicide blocking layer 72 on the surface of the substrate 10 between the sidewall 76 and the drain region 40; alternatively, the first contact hole may also be only located on the surface of the metal silicide blocking layer 72 on the surface of the substrate 10 between the sidewall 76 and the drain region 40; still alternatively, the first contact hole may also be partially located on the surface of the metal silicide blocking layer 72 above the sidewall 76 and partially located on the surface of the metal silicide blocking layer 72 on the surface of the substrate 10 between the sidewall 76 and the drain region 40.

In one embodiment, the fourth contact 98 of the source and the first contact are electrically connected together and grounded, so that the depletion of the drift region can be enhanced, and the breakdown voltage of the device can be improved.

The fourth contact hole 98 and the first contact hole may be electrically connected by electrically connecting the same metal layer or metal interconnection structure, or by other suitable means.

In one example, in order to enhance the depletion of the drift region, the width of the first contact hole is greater than the widths of the first contact hole 92, the second contact hole 94, the third contact hole 96 and the fourth contact hole 98, which refer to the diameters of the contact holes in the direction of the line connecting the source region 50 and the drain region 40 and the extension thereof.

In the embodiment shown in fig. 1, the drain region 40 is not provided with a Shallow Trench Isolation (STI) structure, which can greatly reduce the on-resistance of the device compared to the technology of providing an STI structure to improve HCI at polysilicon.

The present application further provides a method for manufacturing a laterally diffused metal oxide semiconductor device, and fig. 2 is a flow chart of the method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment, which includes the following steps:

s210, acquiring the substrate.

A drift region is formed in the substrate. Referring to fig. 3a, in one embodiment, the substrate 10 is a semiconductor substrate, and the material thereof may be undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), stacked-on-insulator silicon (SSOI), stacked-on-insulator silicon-germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. In the embodiment shown in fig. 1, the material of substrate 10 is monocrystalline silicon.

In one embodiment, the substrate 10 has the second conductivity type, the drift region 20 has the first conductivity type, and the drain region 40 and the source region 50 have the first conductivity type. In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

The substrate 10 may be a P-type semiconductor substrate or an N-type semiconductor substrate, for example, a P-type semiconductor substrate may be selected for an N-type high voltage device, and an N-type semiconductor substrate may be selected for a P-type high voltage device. In the embodiment shown in fig. 1, the substrate 10 is a P-type semiconductor substrate.

The drift region 20 has a different conductivity type depending on the type of the particular LDMOS device. For example, if the LDMOS device is an N-type LDMOS device, the drift region 20 is an N-type drift region; if the LDMOS device is a P-type LDMOS device, the drift region 20 is a P-type drift region. In the embodiment shown in fig. 1, the drift region 20 is an N-type drift region. In general, the doping concentration of the drift region 20 is low, which is lower than the doping concentration of the drain region 40 and the source region 50.

The drift region 20 may be formed using a suitable method, such as a doping process. The doping is generally carried out by means of ion implantation. For example, if an N-type high voltage device is prepared, N-type ions are doped in a region of the substrate 10 where the drift region 20 is to be formed, so as to form an N-type drift region in the substrate; if a P-type high-voltage device is prepared, P-type ions are doped on the substrate 10 to form a P-type drift region. The higher the required doping concentration, the higher the implant dose during the implantation should be accordingly.

And S220, forming a gate dielectric layer on the substrate.

Referring to fig. 3b, in one embodiment, the gate dielectric layer 62 may comprise a conventional dielectric material such as silicon oxide, nitride and oxynitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 62 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).

The gate dielectric layer 62 may be formed by processes known in the art, such as a thermal oxidation process.

And S230, forming a gate material on the gate dielectric layer.

In one embodiment, the gate material is polysilicon, but in other embodiments, metal nitride, metal silicide or the like may be used as the gate material.

In one embodiment, the gate material may be formed by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering, Physical Vapor Deposition (PVD), or the like. The thickness of the gate material may be an appropriate thickness according to the size of the device, and is not particularly limited herein.

In one embodiment, the LDMOS device may be fabricated by two deposition processes of the gate material, wherein step S230 may be any one of the deposition processes.

And S240, photoetching by using a first photoetching plate and etching the grid material to form a grid layer and a grid-like structure.

The first photoetching plate comprises a grid layer pattern and a grid-like structure pattern, the grid layer pattern and the grid-like structure pattern are defined by photoresist on the grid material through photoetching and are used as etching barrier layers, and then the grid material is etched to form a grid layer 64 and a grid-like structure 66. Referring to fig. 3c, a gate-like structure 66 is formed over the drift region 20 and separated from the gate layer 64.

Referring to fig. 3c, in one embodiment, a body region 30 may also be formed in the substrate 10 prior to forming the gate-like structure 66. The body region 30 is located on a side of the gate layer 64 remote from the drift region 20 and is spaced from the drift region 20. The body region 30 has an opposite conductivity type to the drift region 20 and in the embodiment shown in figure 3c the body region 30 is a P-shaped body region. The body region 30 may be formed by, for example, ion implantation, for example, after step S230 and before step S240, body region lithography and etching are performed to remove the gate material at the position where the body region is to be formed, and then P-type dopant impurities, such as boron, are implanted into the region of the substrate 10 where the body region is to be formed by ion implantation, and after implantation, the body region 30 may be formed by thermal diffusion.

And S250, forming a drain region and a source region.

The drain region 40 is disposed in the substrate 10 on one side of the gate layer 64 (in the substrate 10 disposed on the right side of the gate layer 64 in fig. 3 d), in contact with the drift region 20; in one embodiment in the drift region 20. The source region 50 is provided in the substrate 10 on the other side of the gate layer 64 (in the substrate 10 on the left side of the gate layer 64 in fig. 3 d). In one embodiment, the drain region 40 and the source region 50 have a first conductivity type. For example, the drain region 40 and the source region 50 are N-type, which may also be source and drain heavily doped with N-type dopant ions.

In one embodiment, the method of forming the source and drain includes performing source-drain ion implantation into the area of the semiconductor substrate where the source and drain are to be formed, and forming the drain region 40 and the source region 50 in the substrate 10 on both sides of the gate layer 64, respectively. The patterned photoresist layer exposing the predetermined drain region 40 and the source region 50 may be first formed by using a photolithography process, and then source and drain ion implantation may be performed using the patterned photoresist layer as a mask, and finally the patterned photoresist layer may be removed by using, for example, ashing.

Subsequently, an annealing process may be performed, and the annealing process may use any annealing method known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, spike annealing, laser annealing, etc., for example, a rapid thermal annealing process is performed to activate the dopants in the source/drain regions by using a high temperature of 900 to 1050 ℃, and simultaneously repair the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. In addition, depending on the product requirements and functional considerations, Lightly Doped Drains (LDDs) may be formed between the source/drain regions and the gates, respectively.

According to the manufacturing method of the lateral diffusion metal oxide semiconductor device, the pattern of the first photoetching plate is reasonably designed, and the grid-like structure 66 separated from the grid layer 64 is arranged above the drift region 20 between the grid layer 64 and the drain region 40, so that the HCI characteristic of the device can be improved. The method does not need to increase a photoetching plate and does not have strict requirements on an online process. And the characteristics of the device can be finely adjusted only by adjusting the pattern of the first reticle and correspondingly changing the characteristics of the gate-like structures 66 such as size, number, spacing and the like, so that the HCI characteristics of the device can be more reasonably adjusted to meet the requirement of the reliability of the device.

In one embodiment, step S240 is followed by the step of forming the sidewall spacers 76. The spacers 76 are disposed on a side of the gate-like structure away from the gate-like structure 66, and are also disposed on a side of the gate-like structure 66 away from the gate-like structure (for the gate-like structure 66 embodiment, outside of the outermost one of the gate-like structures 66). The sidewall spacers 76 may be made of one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the spacers 76 are deposited and then etched.

In one embodiment, step S250 is followed by step S260: and forming a metal silicide barrier layer. Referring to fig. 3e, a metal silicide blocking layer 72 covers the gate-like structure 66 and also covers the surface of the drift region 20 between the gate-like structure 66 and the drain region 40.

In one embodiment, the metal silicide blocking layer 72 includes an oxide layer, a nitride layer, and an oxynitride layer stacked in this order from bottom to top, the oxide layer including, for example, silicon oxide, the nitride layer including, for example, silicon nitride, and the oxynitride layer including silicon oxynitride. The metal silicide blocking layer 72 may also comprise other suitable materials, for example, the metal silicide blocking layer 72 may further comprise at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-doped silicon nitride layer, and the like.

In one embodiment, the method of forming the metal silicide block layer 72 is as follows:

a layer of metal silicide blocking material is first deposited to cover the gate layer 64, the sidewalls 76, the source region 50 and the drain region 40. To simplify the process, a deposited layer of metal silicide blocking material may cover the entire surface of the substrate 10, which may be deposited by a method such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

Next, as shown in fig. 3e, the metal silicide blocking material layer is patterned to form a metal silicide blocking layer 72. Specifically, a patterned mask layer, such as a patterned photoresist layer, may be formed on the metal silicide blocking material layer, the patterned mask layer defines the metal silicide blocking layer 72 to be formed, the metal silicide blocking material layer is etched by using the patterned mask layer as a mask to form the metal silicide blocking layer 72, the etching process may use dry etching or wet etching to etch the metal silicide blocking material layer, and finally the patterned mask layer is removed.

In the embodiment shown in fig. 3e, the finally formed metal silicide blocking layer 72 exposes a portion of the top surface of the gate layer 64, the surface of the drain region 40, the surface of the source region 50, and the like, so as to facilitate the subsequent formation of metal silicide.

It is to be understood that in one embodiment, the metal silicide blocking layer 72 also fills the gap between the gate-like structure 66 and the gate layer 64 (in the case of multiple gate-like structures 66, the metal silicide blocking layer 72 also fills the gap between adjacent gate-like structures 66), and insulation between the gate layer 64 and the gate-like structure 66 is required, so that the metal silicide blocking layer 72 filled with the insulation is possible. In other embodiments, the gap between the gate-like structure 66 and the gate layer 64 may be filled with other insulating materials. The gate layer 64 and the gate-like structure 66 form a hollow structure, which can also remain insulated, but is not technically feasible.

Step S260 is followed by step S270: and forming metal silicide on the surface of the drain region, the surface of the grid layer and the surface of the source region which are not covered by the metal silicide barrier layer.

To reduce the contact resistance, a metal silicide layer is formed on a portion of the surface of the source region 50, a portion of the surface of the drain region 40, and a portion of the surface of the gate layer 64, wherein the metal silicide layer may include a material of CoSix, NiSix, PtSix, or a combination thereof.

In one embodiment, a method of forming a metal silicide layer includes the steps of: first, as shown in fig. 3f, a metal or other metal substitute, which may include nickel (nickel), cobalt (cobalt), and platinum (platinum) or a combination thereof, is deposited to form a metal layer 81. The substrate is then heated to cause silicidation of the metal layer 81 with the underlying silicon layer to form metal silicide 42, metal silicide 52, and metal silicide 65, and the unreacted metal layer is then removed using an etchant that attacks the metal layer 81 but not the metal silicide, as shown in fig. 3 g.

In one embodiment, step S270 is followed by step S280: and forming an insulating layer on the gate layer, the metal silicide barrier layer, the drain region and the source region.

Referring to fig. 3h, in one embodiment, the insulating layer 74 is silicon oxide. The thickness of the insulating layer 74 can be adjusted according to the device characteristics, for example, decreasing the thickness of the insulating layer 74 can increase the depletion of the drift region, and increasing the thickness can decrease the depletion of the drift region.

In one embodiment, step S290 is further included after step S280: a metal field plate is formed on the insulating layer. A layer of metal is deposited over insulating layer 74 and the metal remains as metal field plate 80 using photolithography and etching processes.

In one embodiment, the metal silicide block layer 72 includes an oxide layer and an oxide etch stop layer on the oxide layer. Step S270 is followed by a step of forming an first contact hole, where the bottom of the first contact hole is located in the oxide etching stopper layer. The oxide etching barrier layer is arranged to ensure that the bottom of the first contact hole stays in the oxide etching barrier layer when the first contact hole is etched.

In one embodiment, step S290 is followed by a step of forming a contact hole. The contact holes may include the first contact hole 92, the second contact hole 94, the third contact hole 96, and the fourth contact hole 98, or the second contact hole 94, the third contact hole 96, the fourth contact hole 98, and the first contact hole.

The first contact hole 92 contacts the metal field plate 80 to lead out the metal field plate 80. In one embodiment, the first contact hole 92 leads the metal field plate 80 out and then to ground.

The second contact hole 94 is electrically connected to the gate layer 64, and further, the second contact hole 94 is electrically connected to the metal silicide 65 to electrically connect to the gate layer 64, and the gate is led out. The third contact hole 96 is electrically connected to the drain region 40, and further, the third contact hole 96 is electrically connected to the metal silicide 42 to electrically connect to the drain region 40. The fourth contact hole 98 is electrically connected to the source region 50, and further, the fourth contact hole 98 is electrically connected to the metal silicide 52 to electrically connect to the source region 50.

The first contact hole 92, the second contact hole 94, the third contact hole 96 and the fourth contact hole 98 are filled with a conductive material, wherein the conductive material may be any suitable conductive material known to those skilled in the art, including but not limited to a metal material; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al.

In one embodiment, the first contact hole 92, the second contact hole 94, the third contact hole 96 and the fourth contact hole 98 may be filled with the same conductive material, such as tungsten metal, or may be filled with different conductive materials.

In one embodiment, a step of forming an interlayer dielectric (ILD) is further included after the step of forming the contact hole and before the step of forming the contact hole S290. Subsequently, an interlayer dielectric covers the insulating layer 74 and the metal field plate 80.

The interlayer dielectric may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed using a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

In one embodiment, the deposited interlayer dielectric may also be planarized by a planarization method (e.g., chemical mechanical polishing CMP) to provide a planar surface for the interlayer dielectric.

In one embodiment, a method of forming a contact hole includes the steps of:

first, a patterned mask layer (e.g., a patterned photoresist layer) is formed on the surface of the interlayer dielectric, the patterned mask layer defining the pattern and location of the first contact hole 92, the second contact hole 94, the third contact hole 96, and the fourth contact hole 98, etc., which are to be formed.

And etching the interlayer medium by using the patterned mask layer as a mask to form a first contact hole, a second contact hole, a third contact hole and a fourth contact hole respectively. The patterned masking layer is then removed, using methods known to those skilled in the art.

Finally, the first, second, third and fourth contact holes are filled with a conductive material to form the final first, second, third and fourth contact holes 92, 94, 96 and 98, as shown in fig. 1.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.