阅读说明：本技术 阵列基板、阵列基板的制造方法及显示装置 (Array substrate, manufacturing method of array substrate and display device ) 是由 梅雪茹 于 2019-10-08 设计创作，主要内容包括：本申请公开了一种阵列基板、阵列基板的制造方法及显示装置,该阵列基板包括基板,及形成在基板上的栅极层、有源层和源漏极层,栅极层与有源层和源漏极层之间形成有绝缘层；有源层包括层叠设置的石墨烯层和二硫化钼层,至少一层石墨烯层位于有源层背离基板的一侧,并与源漏极层接触。本申请改进了阵列基板的结构,提高了阵列基板上的有源层的载流子浓度和迁移率,进而提高阵列基板的性能。(The application discloses an array substrate, a manufacturing method of the array substrate and a display device, wherein the array substrate comprises a substrate, a grid layer, an active layer and a source drain layer, wherein the grid layer, the active layer and the source drain layer are formed on the substrate; the active layer comprises graphene layers and molybdenum disulfide layers which are arranged in a stacked mode, and at least one graphene layer is located on one side, away from the substrate, of the active layer and is in contact with the source drain electrode layer. The structure of the array substrate is improved, the carrier concentration and the mobility of the active layer on the array substrate are improved, and the performance of the array substrate is further improved.)

1. The array substrate is characterized by comprising a substrate, a grid layer, an active layer and a source drain layer, wherein the grid layer, the active layer and the source drain layer are formed on the substrate; the active layer comprises graphene layers and molybdenum disulfide layers which are arranged in a stacked mode, and at least one graphene layer is located on one side, away from the substrate, of the active layer and is in contact with the source drain layer.

2. The array substrate of claim 1, wherein the active layer comprises two graphene layers, and a molybdenum disulfide layer between the two graphene layers.

3. The array substrate of claim 2, wherein the molybdenum disulfide layer comprises a single layer of molybdenum disulfide of less than or equal to 3.

4. The array substrate of claim 3, wherein the number of carbon layers included in the graphene layer is less than or equal to 10.

5. The array substrate of any of claims 1 to 4, wherein the insulating layer comprises a gate insulating layer; the grid layer, the grid insulating layer and the active layer are sequentially formed on the substrate, and the source drain layer is formed on the active layer and the grid insulating layer.

6. The array substrate of any one of claims 1 to 4, wherein the insulating layer comprises a gate insulating layer and an interlayer dielectric layer; the active layer, the grid electrode insulating layer and the grid electrode layer are sequentially formed on the substrate, the interlayer dielectric layer is formed on the active layer and the grid electrode layer, and the source drain electrode layer is formed on the interlayer dielectric layer and penetrates through the interlayer dielectric layer to be in contact with the active layer.

7. A method for manufacturing an array substrate includes:

providing a substrate;

forming a gate layer on the substrate;

forming a gate insulating layer covering the gate electrode layer on the substrate;

forming a laminated graphene layer and a molybdenum disulfide layer on the gate insulating layer to form an active layer, wherein at least one graphene layer is positioned on one side of the active layer, which is far away from the substrate;

and forming a source drain layer on the gate insulating layer and the active layer.

8. The method of manufacturing an array substrate according to claim 7, wherein the forming of the graphene layer and the molybdenum disulfide layer stacked on the gate insulating layer to constitute the active layer comprises:

and sequentially forming a first graphene layer, a molybdenum disulfide layer and a second graphene layer on the gate insulating layer to form the active layer.

9. A method for manufacturing an array substrate includes:

providing a substrate;

forming a laminated graphene layer and a molybdenum disulfide layer on the substrate to form an active layer, wherein at least one graphene layer is positioned on one side of the active layer, which is far away from the substrate;

forming a gate insulating layer on the active layer;

forming a gate electrode layer on the gate insulating layer;

forming an interlayer dielectric layer on the gate layer and the active layer;

and forming a source drain layer which is in contact with the active layer on the interlayer dielectric layer.

10. A display device comprising the array substrate according to any one of claims 1 to 7.

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.

Background

With the development of novel display technologies such as flexible display, Micro LED (Micro LED, μ LED) display, organic light-Emitting Diode (OLED) display, and the like, the performance requirements for important driving elements are higher and higher, such as high mobility, fast driving, low loss, and the like.

As an important driving element in various display technologies, a Thin Film Transistor (TFT) array substrate has a performance directly related to a display effect of a novel display technology. The active layer, which is the most important component of the thin film transistor array substrate, has a great influence on the performance of the thin film transistor array substrate.

Disclosure of Invention

The application provides an array substrate, a manufacturing method of the array substrate and a display device, and aims to improve the structure of the array substrate, improve the carrier concentration and the mobility of an active layer on the array substrate and further improve the performance of the array substrate.

In order to solve the above problems, in a first aspect, the present application provides an array substrate, including a substrate, and a gate layer, an active layer, and a source drain layer formed on the substrate, wherein an insulating layer is formed between the gate layer and the active layer and between the gate layer and the source drain layer; the active layer comprises graphene layers and molybdenum disulfide layers which are arranged in a stacked mode, and at least one graphene layer is located on one side, away from the substrate, of the active layer and is in contact with the source drain layer.

Optionally, the active layer comprises two graphene layers, and a molybdenum disulfide layer located between the two graphene layers.

Optionally, the molybdenum disulfide layer comprises a single layer of molybdenum disulfide in an amount less than or equal to 3.

Optionally, the number of carbon layers included in the graphene layer is less than or equal to 10.

Optionally, the insulating layer comprises a gate insulating layer; the grid layer, the grid insulating layer and the active layer are formed on the substrate, and the source drain layer is formed on the active layer and the grid insulating layer.

Optionally, the insulating layer includes a gate insulating layer and an interlayer dielectric layer; the active layer, the grid electrode insulating layer and the grid electrode layer are sequentially formed on the substrate, the interlayer dielectric layer is formed on the active layer and the grid electrode layer, and the source drain electrode layer is formed on the interlayer dielectric layer and penetrates through the interlayer dielectric layer to be in contact with the active layer.

In a second aspect, the present application provides a method for manufacturing an array substrate, including:

providing a substrate;

forming a gate layer on the substrate;

forming a gate insulating layer covering the gate electrode layer on the substrate;

forming a laminated graphene layer and a molybdenum disulfide layer on the gate insulating layer to form an active layer, wherein at least one graphene layer is positioned on one side of the active layer, which is far away from the substrate;

and forming a source drain layer on the gate insulating layer and the active layer.

Optionally, the forming of the stacked graphene layer and molybdenum disulfide layer on the gate insulating layer to constitute an active layer includes:

and sequentially forming a first graphene layer, a molybdenum disulfide layer and a second graphene layer on the gate insulating layer to form the active layer.

In a third aspect, the present application provides a method for manufacturing an array substrate, including:

providing a substrate;

forming a laminated graphene layer and a molybdenum disulfide layer on the substrate to form an active layer, wherein at least one graphene layer is positioned on one side of the active layer, which is far away from the substrate;

forming a gate insulating layer on the active layer;

forming a gate electrode layer on the gate insulating layer;

forming an interlayer dielectric layer on the gate layer and the active layer;

and forming a source drain layer which is in contact with the active layer on the interlayer dielectric layer.

Optionally, the forming of the stacked graphene layer and molybdenum disulfide layer on the substrate to constitute the active layer includes:

and sequentially forming a first graphene layer, a molybdenum disulfide layer and a second graphene layer on the substrate to form the active layer.

In a fourth aspect, the present application provides a display device, including the array substrate as described above, where the array substrate includes a substrate, and a gate layer, an active layer, and a source drain layer formed on the substrate, and an insulating layer is formed between the gate layer and the active layer and between the gate layer and the source drain layer; the active layer comprises graphene layers and molybdenum disulfide layers which are arranged in a stacked mode, and at least one graphene layer is located on one side, away from the substrate, of the active layer and is in contact with the source drain layer.

Has the advantages that: in this application, the active layer of array substrate is including the graphite alkene layer and the molybdenum disulfide layer of range upon range of setting, and at least one deck graphite alkene layer is located one side that the active layer deviates from the base plate to with the source drain layer contact of array substrate. Molybdenum disulfide as a typical two-dimensional transition metal chalcogenide has the characteristics of adjustable band gap and high carrier concentration, and graphene has the characteristic of high conductivity and can provide a large amount of free electrons for molybdenum dioxide. The graphene layer and the molybdenum disulfide layer are laminated together to form an active layer of the array substrate, so that at least one graphene layer is positioned on one side of the active layer, which is far away from the substrate, and is contacted with the source drain layer of the array substrate, the active layer has higher carrier concentration, meanwhile, the contact potential barrier of the active layer and the source drain layer is reduced, the carrier mobility of the active layer is improved, and the performance of the array substrate is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram illustrating a gate layer formed on a substrate according to an embodiment of an array substrate provided in the present application;

FIG. 2 is a schematic diagram illustrating a structure of a gate insulating layer formed in an embodiment of an array substrate provided in the present application;

fig. 3 is a schematic structural view illustrating the formation of an active layer in an embodiment of an array substrate provided in the present application;

fig. 4 is a schematic structural diagram of forming a source drain layer in an embodiment of an array substrate provided in the present application;

FIG. 5 is a schematic diagram illustrating a structure of a passivation layer formed in an embodiment of an array substrate provided in the present application;

FIG. 6 is a schematic diagram illustrating an ITO layer formed on an embodiment of an array substrate according to the present disclosure;

FIG. 7 is a schematic flow chart illustrating a method of fabricating an array substrate according to another embodiment of the present disclosure;

FIG. 8 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating an array substrate;

fig. 9 is a schematic structural diagram of another embodiment of an array substrate provided in the present application.

An array substrate 10; an array substrate 10 a; a substrate 11; a substrate 11 a; a gate layer 12; a gate layer 12 a; a gate insulating layer 13; a gate insulating layer 13 a; an interlayer dielectric layer 14; an active layer 15; an active layer 15 a; a graphene layer 151; a graphene layer 151 a; a molybdenum disulfide layer 152; a molybdenum disulfide layer 152 a; a source drain layer 16; a source drain layer 16 a; a passivation layer 17; a passivation layer 17 a; an indium tin oxide layer 18; indium tin oxide layer 18 a.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be considered as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not set forth in detail in order to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

The application provides an array substrate. The following are detailed below.

Referring to fig. 4, the array substrate 10 includes a substrate 11, and a gate layer 12, an active layer 15, and a source drain layer 16 formed on the substrate 11, with an insulating layer formed between the gate layer 12 and the active layer 15 and the source drain layer 16. The source and drain electrode layer 16 includes a source electrode and a drain electrode connected to two sides of the active layer 15, the source electrode, the drain electrode and the active layer 15 are all separated from the gate electrode layer 12 by an insulating layer, the number and the structure of the insulating layers are specifically determined according to the arrangement manner of the gate electrode layer 12, the active layer 15 and the source and drain electrode layer 16 on the substrate 11, and the structure of the insulating layer will be described in detail below, and will not be described again.

In one embodiment, as shown in fig. 3, the active layer 15 may include a graphene layer 151 and molybdenum disulfide (MoS) layer stacked on each other₂) A layer 152, wherein at least one graphene layer 151 is located on the side of the active layer 15 facing away from the substrate 11 and is in contact with the source drain layer 16.

It can be understood that molybdenum disulfide, as a typical two-dimensional transition metal chalcogenide, has a tunable band gap characteristic, and a carrier concentration thereof is high, while graphene has a high conductivity characteristic, and can provide a large amount of free electrons for molybdenum dioxide. The graphene layer 151 and the molybdenum disulfide layer 152 are laminated together to form the active layer 15 of the array substrate 10, so that at least one graphene layer 151 is located on one side of the active layer 15, which is away from the substrate 11, and is in contact with the source drain layer 16 of the array substrate 10, the contact barrier between the active layer 15 and the source drain layer 16 is reduced while the active layer 15 has higher carrier concentration, the carrier mobility of the active layer 15 is improved, and the performance of the array substrate 10 is improved.

In addition, the graphene and the molybdenum disulfide have high mechanical strength, and the graphene layer 151 and the molybdenum disulfide layer 152 are laminated together to form the active layer 15 of the array substrate 10, so that the structural strength of the active layer 15 can be improved, and the array substrate 10 is more suitable for a flexible display device.

Alternatively, the active layer 15 may include two graphene layers 151 and a molybdenum disulfide layer 152 between the two graphene layers 151, so that the structure and the manufacturing process are simpler while the active layer 15 has better carrier mobility and mechanical properties.

Of course, the graphene layer 151 and the molybdenum disulfide layer 152 included in the active layer 15 may also be one or more layers, such as: the active layer 15 may include a graphene layer 151 and a molybdenum disulfide layer 152, with the graphene layer 151 overlying the molybdenum disulfide layer 152. Alternatively, the active layer 15 includes multiple graphene layers 151 and multiple molybdenum disulfide layers 152 that are sequentially arranged at intervals, and the topmost layer of the active layer 15 is the graphene layer 151.

In one embodiment, the molybdenum disulfide layer 152 may include a single molybdenum disulfide layer of less than or equal to 3, so that the molybdenum disulfide layer 152 has a higher carrier concentration, and at the same time, the time for forming the molybdenum disulfide layer 152 is reduced and the overall thickness of the array substrate 11 is reduced.

Of course, the number of the molybdenum disulfide layer 152 may be greater than 3, which may be determined by the performance requirement of the array substrate 10.

In an embodiment, the number of carbon layers included in the graphene layer 151 may be less than or equal to 10, so as to reduce the time for forming the graphene layer 151 and reduce the overall thickness of the array substrate 11 while effectively reducing the interface barrier between the active layer 15 and the source/drain electrode layer 16. The number of carbon layers included in the graphene layer 151 may be 1, 2, 5, and the like, which is not limited herein.

In an embodiment, as shown in fig. 4, the insulating layer may include a gate insulating layer 13. The gate electrode layer 12, the gate insulating layer 13 and the active layer 15 are sequentially formed on the substrate 11, the source drain layer 16 is formed on the active layer 15 and the gate insulating layer 13, and a source and a drain of the source drain layer 16 are in contact with both sides of the active layer 15, respectively. Wherein the gate insulating layer 13 covers the gate layer 12 to prevent the gate layer 12 from contacting the active layer 15.

Alternatively, the material of the gate insulating layer 13 may be silicon oxide (SiO)_x) (ii) a Or from silicon oxide (SiO)_x) And silicon nitride (SiN)_x) A composite layer formed by laminating the two; or from silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And silicon oxynitride (S)_iNO) a composite layer formed by laminating the three; or from silicon nitride (SiN)_x) Silicon oxide (SiO)_x) And aluminum oxide (Al)₂O₃) A composite layer formed by laminating the three components. The gate insulating layer 13 may be made of aluminum nitride (AlN) or hafnium oxide (HfO)₂) And a high-K dielectric layer.

In one embodiment, the substrate 11 is a transparent substrate 11. Specifically, the substrate 11 may be a transparent glass substrate 11, or a transparent flexible substrate 11 made of a material such as Polyimide (PI), polyethylene terephthalate (PET), Cyclic Olefin Copolymer (COC), or polyether sulfone resin (PES), or the like.

In one embodiment, the material of the gate layer 12 may be a composite layer of molybdenum and copper, or a composite layer of molybdenum and aluminum.

In one embodiment, the source/drain layer 16 may be made of a metal material such as copper, aluminum, or cobalt, a composite layer of molybdenum and copper, or a composite layer of molybdenum and aluminum.

As shown in fig. 5, a Passivation (PV) layer may be further formed on the source/drain layer 16, and a via hole may be opened on the passivation layer 17 and extend from a top surface of the passivation layer 17 to an upper surface of the source/drain layer 16. The passivation layer 17 may be made of silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Silicon oxynitride (S)_iNO), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Or an insulating material such as Boron Nitride (BN).

As shown in fig. 6, an Indium Tin Oxide (ITO) layer may also be formed on the passivation layer 17 and patterned to form a pixel electrode. Wherein the indium tin oxide layer 18 is in contact with the source drain layer 16 through a via of the passivation layer 17.

In another embodiment, as shown in fig. 7, the insulating layer of the array substrate 10a includes a gate insulating layer 13a and an interlayer dielectric (ILD) layer 14; the active layer 15a, the gate insulating layer 13a, and the gate electrode layer 12a of the array substrate 10a are sequentially formed on the substrate 11a, and the gate insulating layer 13a is positioned between the active layer 15a and the gate electrode layer 12a to separate the active layer 15a from the gate electrode layer 12 a. The interlayer dielectric layer 14 is formed on the active layer 15a and the gate layer 12a, and the source drain layer 16a is formed on the interlayer dielectric layer 14, so that the source drain layer 16a is separated from the gate layer 12a, the source drain layer 16a is prevented from contacting with the gate layer 12a, and the source drain layer 16a penetrates through the interlayer dielectric layer 14 to contact with the active layer 15 a.

Optionally, a passivation layer 17a is further formed on the source drain layer 16a and the interlayer dielectric layer 14a, and an indium tin oxide layer 18a is further formed on the passivation layer 17a, and the indium tin oxide layer 18a is patterned to form a pixel electrode.

The active layer 15a, the gate insulating layer 13a, the gate layer 12a, the source drain layer 16a and the passivation layer 17a may be made of the same material as the active layer 15, the gate insulating layer 13, the gate layer 12, the source drain layer 16 and the passivation layer 17, and thus, the description thereof is omitted.

The material of the interlayer dielectric layer 14 may be silicon nitride or silicon dioxide, etc.

As shown in fig. 8, the present application further provides a manufacturing method of an array substrate, the manufacturing method of the array substrate includes, but is not limited to, steps S110 to S150, and the detailed description of steps S110 to S150 is as follows:

110. a substrate 11 is provided.

The substrate 11 is a transparent substrate 11, for example, a glass substrate 11, a plastic substrate 11, or the like, and may be a flexible substrate 11.

120. As shown in fig. 1, a gate layer 12 is formed on a substrate 11.

The specific manufacturing process comprises the following steps: depositing a metal layer on the substrate 11, wherein the material of the metal layer is the material of the gate layer 12. Then, the metal layer is patterned by a photomask process including photoresist coating, exposure, development, etching, photoresist stripping, etc. to form the gate layer 12.

130. As shown in fig. 2, a gate insulating layer 13 covering the gate layer 12 is formed on the substrate 11.

The step of forming the gate insulating layer 13 may refer to the step of forming the gate layer 12, and is not described herein again.

140. As shown in fig. 3, a graphene layer 151 and a molybdenum disulfide layer 152 are stacked on the gate insulating layer 13 to constitute the active layer 15, and at least one graphene layer 151 is located on a side of the active layer 15 facing away from the substrate 11.

Both the graphene layer 151 and the molybdenum disulfide layer 152 may be prepared by a solution method, a vapor deposition method, or a transfer technique. In the process of forming the graphene layer 151 and the molybdenum disulfide layer 152, different numbers of graphene layers 151 and molybdenum disulfide layers 152 can be obtained by controlling conditions such as film formation time, so as to adjust the mobility of the active layer 15.

The number and the stacking manner of the graphene layers 151 and the molybdenum disulfide layers 152 included in the active layer 15 may specifically refer to the above description of the structure of the active layer 15, and are not described herein again.

150. As shown in fig. 4, a source-drain layer 16 is formed on the gate insulating layer 13 and the active layer 15.

The step of forming the source/drain layer 16 may refer to the step of forming the gate layer 12, and is not described herein again.

In one embodiment, forming the graphene layer 151 and the molybdenum disulfide layer 152 stacked on the gate insulating layer 13 to constitute the active layer 15 includes:

a first graphene layer, a molybdenum disulfide layer 152, and a second graphene layer are sequentially formed on the gate insulating layer 13 to constitute the active layer 15. The first graphene layer is the graphene layer 151 located on the lower side of the molybdenum disulfide layer 152 in fig. 3, and the first graphene layer is the graphene layer 151 located on the upper side of the molybdenum disulfide layer 152 in fig. 3.

Optionally, after the source/drain layer 16 is formed on the gate insulating layer 13 and the active layer 15, steps S160 and S170 may be further included, which are specifically described as follows:

160. as shown in fig. 5, a passivation layer 17 is formed on the source drain layer 16, and a via hole extending from a top surface of the passivation layer 17 to an upper surface of the source drain layer 16 is formed on the passivation layer 17.

170. As shown in fig. 6, an indium tin oxide layer 18 is formed on the passivation layer 17 and patterned to form a pixel electrode; wherein the indium tin oxide layer 18 is in contact with the source drain layer 16 through a via of the passivation layer 17.

As shown in fig. 7 and 9, the present application further provides another method for manufacturing an array substrate, including but not limited to steps S210 to S260, and the steps S210 to S260 are described in detail as follows:

210. a substrate 11a is provided.

220. A graphene layer 151a and a molybdenum disulfide layer 152a are laminated on the substrate 11a to constitute an active layer 15a, and at least one graphene layer 151a is located on a side of the active layer 15a facing away from the substrate 11 a.

230. A gate insulating layer 13a is formed on the active layer 15 a.

240. The gate electrode layer 12a is formed on the gate insulating layer 13 a.

250. An interlayer dielectric layer 14 is formed on the gate layer 12a and the active layer 15 a.

260. A source drain layer 16a is formed on the interlayer dielectric layer 14 in contact with the active layer 15 a.

Alternatively, the forming of the stacked graphene layer 151a and molybdenum disulfide layer 152a on the substrate 11a to constitute the active layer 15a includes:

a first graphene layer, a molybdenum disulfide layer 152, and a second graphene layer are sequentially formed on the substrate 11a to constitute an active layer 15 a. The first graphene layer is the graphene layer 151a located on the lower side of the molybdenum disulfide layer 152a in fig. 7, and the first graphene layer is the graphene layer 151a located on the upper side of the molybdenum disulfide layer 152a in fig. 7.

Optionally, after the source/drain layer 16a in contact with the active layer 15a is formed on the interlayer dielectric layer 14, steps S270 and S280 may be further included, which are specifically described as follows:

270. a passivation layer 17a is formed on the source drain layer 16a and the interlayer dielectric layer 14, and a via hole extending from a top surface of the passivation layer 17a to an upper surface of the source drain layer 16a is formed on the passivation layer 17 a.

280. Forming an indium tin oxide layer 18a on the passivation layer 17a, and patterning to form a pixel electrode; wherein the indium tin oxide layer 18a contacts the source drain layer 16a through a via of the passivation layer 17 a.

It can be understood that, in the array substrate obtained by the two array substrate manufacturing methods, the active layer includes the graphene layer and the molybdenum disulfide layer which are stacked, and at least one graphene layer is located on the side of the active layer away from the substrate and is in contact with the source/drain layer. The active layer has higher carrier concentration, meanwhile, the contact potential barrier between the active layer and the source drain layer is reduced, the carrier mobility of the active layer is improved, and the performance of the array substrate is further improved. In addition, the structural strength of the active layer can be improved, so that the array substrate is more suitable for a flexible display device.

It should be noted that, in the above embodiment of the array substrate, only the above structure is described, and it should be understood that, in addition to the above structure, the array substrate of the present application may further include any other necessary structure such as a buffer layer as needed, and the specific structure is not limited herein.

The present application provides a display device, where the display device includes the array substrate as described above, or an array substrate manufactured by the array substrate manufacturing method as described above, and the specific structure of the array substrate refers to the foregoing embodiments.

The display device may be any display device having the array substrate, such as a flexible display device, a micro light emitting diode display device, an organic light emitting diode display device, and the like, and is not limited herein.

The array substrate, the manufacturing method of the array substrate, and the display device provided in the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the above embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.