阅读说明：本技术 一种宽范围单调线性可调频率时钟电路 (Wide-range monotonous linear adjustable frequency clock circuit ) 是由 吴益民 熊辉涛 王鹏飞 于 2019-10-31 设计创作，主要内容包括：本发明公开一种宽范围单调线性可调频率时钟电路,包括：充电阵列,所述充电阵列是一个数字可调,对充电电流可以进行单调线性调节的电流源或电流镜阵列；参考电压电路,用于产生一个参考电压；比较控制电路,所述比较控制电路的第一输入端与所述充电阵列相连,所述比较控制电路的第二输入端与所述参考电压电路相连；所述比较控制电路包括比较器,充电电容及控制逻辑。本发明易于实现,功耗低且成本不高,完美的适应用无线充电、雾化器等需要频率调制的应用场合。(The invention discloses a wide-range monotonous linear adjustable frequency clock circuit, which comprises: the charging array is a current source or a current mirror array which is digitally adjustable and can perform monotonous linear adjustment on charging current; a reference voltage circuit for generating a reference voltage; a first input end of the comparison control circuit is connected with the charging array, and a second input end of the comparison control circuit is connected with the reference voltage circuit; the comparison control circuit comprises a comparator, a charging capacitor and control logic. The invention is easy to realize, has low power consumption and low cost, and is perfectly suitable for application occasions requiring frequency modulation, such as wireless charging, atomizers and the like.)

1. A wide-range monotonic linearly tunable frequency clock circuit, comprising: the charging array is a current source or a current mirror array which is digitally adjustable and can perform monotonous linear adjustment on charging current; a reference voltage circuit for generating a reference voltage; a first input end of the comparison control circuit is connected with the charging array, and a second input end of the comparison control circuit is connected with the reference voltage circuit; the comparison control circuit comprises a comparator, a charging capacitor and control logic.

2. The wide-range monotonic linearly tunable frequency clock circuit of claim 1, wherein: the charging array consists of a certain number of charging units, each charging unit comprises an independent basic current source or current mirror, and the current source or current mirror of each charging unit has the same current; the charging unit comprises a controllable charging unit and a normally open charging unit.

3. The wide-range monotonic linearly tunable frequency clock circuit of claim 2, wherein: the charging array comprises a unit control module for independently controlling each controllable charging unit to be turned off or turned on; the output end of the unit control module is connected with the control end of each controllable charging unit through a bus, so that the number of the controllable charging units which are turned off or turned on is ensured to be monotonically increased or monotonically decreased; wherein: the number of controllable charging units determines the range of output charging current, namely the range of output frequency; the number of normally-on charging units determines the minimum output charging current, i.e., the minimum output clock frequency.

4. A broad range monotonic linearly tunable frequency clock circuit according to claim 2 or 3, wherein: the output of the charging unit is the current of a current source or a current mirror of the charging unit, the output ends of all the charging units are connected together and used as the output of the whole charging array, and the output end of the charging array is connected with the first input end of the comparison control circuit.

5. The wide-range monotonic linearly tunable frequency clock circuit of claim 1, wherein: the reference voltage circuit is connected with a resistor in series, and a reference voltage proportional to the current of the charging array is obtained by the resistor through the current proportional to the current of the charging array, namely the output of the reference voltage circuit is a reference voltage.

6. The wide-range monotonic linearly tunable frequency clock circuit of claim 1, wherein: the comparison control circuit comprises a charging capacitor, a comparator and control logic; the charging capacitor is powered by the charging array, the voltage obtained after the charging of the charging capacitor is compared with the reference voltage generated by the reference voltage circuit in the comparator, the comparator transmits the comparison result to the control logic, and the control logic controls the charging capacitor to charge and discharge.

7. The wide-range monotonic linearly tunable frequency clock circuit of any one of claims 1-6, wherein: and finally, the comparison control circuit outputs a clock, and the frequency of the clock and the starting number of the charging units are linearly changed.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a wide-range monotonous linear adjustable frequency clock circuit.

Background

In frequency conversion modulation applications, such as wireless chargers, atomizers, etc., precise modulation of frequency over a wide range is required. The wireless charger modulates the frequency to realize the transmission of digital signals. In the atomizer scheme, the output control frequency needs to be followed and matched according to the resonant frequency of the atomizing plate so as to realize the maximum conversion efficiency.

In order to realize frequency adjustability, in the prior art, a high-frequency source clock is adopted for fine frequency division, and the clock adjustability is realized by changing a frequency division coefficient; in order to obtain the adjustment accuracy of 0.1%, the frequency of the source clock needs to be 1000 times of the output frequency, so that the frequency of the source clock is required to be higher, and the power consumption of the source clock is also higher.

Upon retrieval, patent application No.: 201621009690.8 discloses a clock generation circuit with adjustable oscillation frequency, which comprises the following devices connected in sequence: the band-gap reference circuit, the digital-to-analog converter, the voltage-controlled oscillator and the signal shaping circuit; the output end of the band-gap reference circuit outputs a constant reference voltage, the digital-to-analog converter receives a preset value and the constant reference voltage and outputs an analog voltage VR, and the preset value is a voltage set value or a frequency set value; the voltage-controlled oscillator receives the analog voltage VR and outputs a sawtooth wave voltage V1; the signal shaping circuit receives the sawtooth wave voltage V1 and outputs a clock signal CLK with a duty cycle of 50%. The circuit is complex and the oscillation frequency is changed by voltage controlled resistors, which greatly increases the cost of the application.

Disclosure of Invention

In order to solve the problems, the invention provides a wide-range monotone linear adjustable frequency clock circuit which is easy to implement, low in power consumption and low in cost.

The technical scheme adopted by the invention for solving the problem is as follows:

a wide-range monotonic linearly tunable frequency clock circuit comprising: the charging array is a current source or a current mirror array which is digitally adjustable and can perform monotonous linear adjustment on charging current; a reference voltage circuit for generating a reference voltage; a first input end of the comparison control circuit is connected with the charging array, and a second input end of the comparison control circuit is connected with the reference voltage circuit; the comparison control circuit comprises a comparator, a charging capacitor and control logic; the charging array charges the charging capacitor, the voltage charged by the capacitor is fed back to the comparator, the comparator compares the voltage of the charging capacitor with the reference voltage VREF transmitted by the reference voltage circuit and transmits the comparison result to the control logic, and the control logic controls the charging capacitor to charge and discharge, so that the charging capacitor is charged and discharged periodically, the high and low level periodically output by the comparator is square waves, and the comparison control circuit outputs clock signals.

Furthermore, the charging array is composed of a certain number of charging units, each charging unit comprises an independent basic current source or current mirror, and the current source or current mirror of each charging unit has the same current; the charging unit comprises a controllable charging unit and a normally open charging unit.

Furthermore, the charging array comprises a unit control module for independently controlling each controllable charging unit to be turned off or turned on; the output end of the unit control module is connected with the control end of each controllable charging unit through a bus, so that the number of the controllable charging units which are turned off or turned on is ensured to be monotonically increased or monotonically decreased; wherein: the number of controllable charging units determines the range of output charging current, namely the range of output frequency; the number of normally-on charging units determines the minimum output charging current, i.e., the minimum output clock frequency.

Furthermore, the output of the charging unit is the current of a current source or a current mirror of the charging unit, the output ends of all the charging units are connected together to be used as the output of the whole charging array, and the output end of the charging array is connected with the first input end of the comparison control circuit.

Furthermore, a resistor is connected in series in the reference voltage circuit, and a reference voltage proportional to the current of the charging array is obtained by passing the current proportional to the charging array through the resistor, that is, the output of the reference voltage circuit is a reference voltage.

Further, the comparison control circuit comprises a charging capacitor, a comparator and control logic; the charging capacitor is powered by the charging array, the voltage obtained after the charging of the charging capacitor is compared with the reference voltage generated by the reference voltage circuit in the comparator, the comparator transmits the comparison result to the control logic, and the control logic controls the charging capacitor to charge and discharge.

Further, the comparison control circuit outputs a clock, the frequency of the clock is related to the output current of the charging array, the output reference voltage of the reference voltage circuit and the size of the charging capacitor, and the structure ensures that the frequency of the output clock changes in proportion to the number of the charging units which are turned on.

The invention has the beneficial effects that: the wide-range monotone linear adjustable frequency clock circuit comprises a charging array, a reference voltage circuit and a comparison control circuit, wherein a first input end of the comparison control circuit is connected with the charging array, and a second input end of the comparison control circuit is connected with the reference voltage circuit; the comparison control circuit comprises a comparator, a charging capacitor and control logic; the charging array charges the charging capacitor, the voltage charged by the capacitor is fed back to the comparator, the comparator compares the voltage of the charging capacitor with the reference voltage VREF transmitted by the reference voltage circuit and transmits the comparison result to the control logic, and the control logic controls the charging capacitor to charge and discharge, so that the charging capacitor is charged and discharged periodically, the high and low level periodically output by the comparator is square waves, and the comparison control circuit outputs clock signals. The output clock frequency f of the clock signal is in linear relation with the charging current proportion m, and the minimum value and the maximum value of the clock frequency can be adjusted by setting the number of normally open charging units and the total number of charging units, namely, the monotonous linear adjustment of the wide range of the output frequency is realized.

Therefore, the technology provided by the invention can realize a wide-range monotonous linear adjustable frequency clock circuit, saves power consumption and external cost compared with the traditional voltage-controlled resistance frequency modulation mode, and perfectly adapts to application occasions requiring frequency modulation such as wireless charging, atomizers and the like.

Drawings

FIG. 1 is a schematic circuit diagram of the present invention.

Fig. 2 is a circuit diagram of the present invention.

Fig. 3 is a schematic diagram of a charging array in an embodiment of the invention.

Fig. 4 is a circuit connection diagram of the charging unit according to the embodiment of the invention.

The reference numbers illustrate: 1. a charging array; 2. a reference voltage circuit; 3. and a comparison control circuit.

Detailed Description

Fig. 1-4 show a wide-range monotonic linear tunable clock circuit implemented by the present invention.

As shown in fig. 1 and 2, the wide-range monotonic linear adjustable frequency clock circuit comprises a charging array 1, a reference voltage circuit 2 and a comparison control circuit 3; a first input end of the comparison control circuit 3 is connected with the charging array 1, the charging array 1 provides adjustable current to be output to the comparison control circuit 3, and a second input end of the comparison control circuit 3 is connected with the reference voltage circuit 2; the comparison control circuit 3 comprises a comparator, a charging capacitor and a control logic.

In this embodiment, a structure diagram of the charging array is shown in fig. 3, the charging array includes a plurality of charging units and a unit control module inside, a circuit of the charging unit is shown in fig. 4, and is composed of a current mirror and a switch, a current of the current mirror is controlled by a voltage of Vbias to obtain a fixed current mirror current Im, the on and off of the current mirror is controlled by a control signal CTRL, the control signal may be one signal or a plurality of signals, depending on a control mode of the unit control module, the charging unit outputs a current of the current mirror, and the output is COM; the outputs COM of all the charging units in the charging array are connected together to synthesize an output which is connected to the comparison control circuit and used as the charging current of the charging capacitor.

The output charging current I21 of the charging array is m Im, where m is the number of charging cells turned on in the charging array.

The charging unit comprises a controllable charging unit and a normally open charging unit, wherein the controllable charging unit is controlled by a unit control module, when the frequency of a clock needs to be adjusted, the number of the opened controllable charging units can be monotonically increased or monotonically decreased by the unit control module, and the control signal for adjusting the clock is converted into a thermometer code signal to realize independent control on each controllable charging unit, so that the charging current is monotonically changed.

The current of the normally-on charging unit is the minimum current that the charging array can generate, which determines the minimum frequency of the clock circuit.

In the present embodiment, as shown in fig. 2, the reference voltage circuit 2 obtains the reference voltage VREF from the rated current source I22 through the resistor R21.

I22 is proportional to the current Im of the charging unit, i.e. I22 ═ n × Im, where n is the proportionality coefficient between I22 and the current Im of the charging unit.

The reference voltage VREF I22R 21 n Im R21.

In the present embodiment, as shown in fig. 2, the comparison control circuit includes a charging capacitor circuit, a comparator a21, a comparator a22, and control logic; the charge capacitor circuit includes switch S21, switch S22, switch S23, switch S24, capacitor C21, and capacitor C22.

The opening or closing of the switch S21, the switch S22, the switch S23, and the switch S24 is controlled by control logic; wherein the switch S21 is closed and opened in unison with the switch S24, and the switch S22 is closed and opened in unison with the switch S23.

The closing and opening of switch S21 and switch S24 is opposite to the closing and opening of switch S22 and switch S23.

For capacitor C21, when switch S21 is closed and switch S22 is open, the charging current charges C21, charging the voltage of C21 to the reference voltage VREF; when switch S21 is open and switch S22 is closed, C21 discharges; the same applies to the charging and discharging operations of the switch S23, the switch S24 and the capacitor C22.

The capacitor C21 and the capacitor C22 have the same size, and C21 is equal to C22, so that the duty ratio of the output clock frequency is ensured to be 50%.

The comparator A21 and the comparator A22 respectively compare the voltage of the capacitor C21 and the capacitor C22 with the VREF voltage, the comparison result of the comparator is sent to the control logic module, and the control logic module controls the capacitor C21 and the capacitor C22 to realize the charge-discharge switching of the capacitor C21 and the capacitor C22.

The capacitor obtains the charge Q ═ VREF ═ C ═ I11 × (t), where t is the charging time, and the charge Q ═ VREF ═ C ═ R21/(m × (m) Im) is obtained in one charging.

The clock frequency output by the control logic is f =1/(2t), and since the output voltages of C21 and C22 compared after charging control the rising and falling of the clock respectively, the cycle of the clock output is 2t, and the clock frequency output by the control logic is f =1/(2 t).

The output clock frequency f is m/(2 x n C R21), and the clock frequency is related to the capacitance C, the resistance R21, the charging current ratio m, and the current ratio n of the reference voltage.

The frequency of the output clock frequency f is in linear relation with the charging current proportion m, and the minimum value and the maximum value of the adjustable clock frequency are realized by setting the number of normally open charging units and the total number of charging units, namely the wide-range monotonous linear adjustment of the output frequency is realized.

The above embodiments are merely illustrative of the preferred embodiments of the present invention, and not restrictive, and various changes and modifications to the technical solutions of the present invention may be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are intended to fall within the scope of the present invention defined by the appended claims.