阅读说明：本技术 自动生产线产品计数信号产生电路 (Automatic production line product counting signal generating circuit ) 是由 曾晓红 凌云 郭艳杰 王兵 于 2017-11-16 设计创作，主要内容包括：一种自动生产线产品计数信号产生电路,包括计数信号传感器、可控可逆计数器、译码器、抗干扰阈值选择器、RS触发器、振荡器。计数信号传感器输出计数初始脉冲；可控可逆计数器的输入为计数初始脉冲、采样时钟脉冲、加计数限幅控制信号和减计数限幅控制信号,输出为限幅累积计数值；译码器输入为限幅累积计数值,输出为译码输出信号、加计数限幅控制信号和减计数限幅控制信号；抗干扰阈值选择器的输入为译码输出信号,输出为第一置位信号和第二置位信号；RS触发器的输入为第一置位信号和第二置位信号,输出为计数脉冲。所述电路能够滤除产品计数脉冲中单个或者连续的正、负窄脉冲干扰,可以应用在各种需要进行产品计数的生产线。(A counting signal generating circuit for automatic production line products comprises a counting signal sensor, a controllable reversible counter, a decoder, an anti-interference threshold selector, an RS trigger and an oscillator. The counting signal sensor outputs counting initial pulses; the input of the controllable reversible counter is counting initial pulse, sampling clock pulse, counting-up amplitude limiting control signal and counting-down amplitude limiting control signal, and the output is amplitude limiting accumulated count value; the decoder inputs the amplitude limiting accumulated count value and outputs a decoding output signal, an adding counting amplitude limiting control signal and a subtracting counting amplitude limiting control signal; the input of the anti-interference threshold selector is a decoding output signal, and the output is a first set signal and a second set signal; the RS trigger inputs a first set signal and a second set signal and outputs a counting pulse. The circuit can filter single or continuous positive and negative narrow pulse interference in product counting pulses, and can be applied to various production lines needing product counting.)

1. An automatic production line product count signal generating circuit, characterized by:

the device comprises a counting signal sensor, a controllable reversible counter, a decoder, an anti-interference threshold selector, an RS trigger and an oscillator;

the counting signal sensor outputs counting initial pulses; the input of the controllable reversible counter is counting initial pulse, sampling clock pulse, counting-up amplitude limiting control signal and counting-down amplitude limiting control signal, and the output is amplitude limiting accumulated count value for counting the sampling clock pulse; the decoder inputs the amplitude limiting accumulated count value and outputs a decoding output signal, an adding counting amplitude limiting control signal and a subtracting counting amplitude limiting control signal; the input of the anti-interference threshold selector is a decoding output signal, and the output is a first set signal and a second set signal; the input of the RS trigger is a first set signal and a second set signal, and the output is a counting pulse; the oscillator outputs a sampling clock pulse.

2. The automated production line product count signal generating circuit of claim 1, wherein: the lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; n is an integer greater than or equal to 2; the function of the controllable reversible counter is to be controlled in an up-counting state, a down-counting state or a limiting and keeping state by the level state of the counting initial pulse and the up-counting limiting control signal and the down-counting limiting control signal.

3. The automated production line product count signal generating circuit of claim 2, wherein: when the level state of the counting initial pulse is a counting control state and the counting amplitude limiting control signal is invalid, the controllable reversible counter is in the counting state; when the level state of the counting initial pulse is a count-down control state and the count-down amplitude limiting control signal is invalid, the controllable reversible counter is in the count-down state; otherwise the controllable up-down counter is in the clipping hold state.

4. The automated production line product count signal generating circuit of claim 3, wherein: the decoder has the function of decoding the amplitude limiting accumulated count value to obtain N +1 decoding output signals; the N +1 decoded output signals are composed of y0, y1, … …, yN, and only one of y0, y1, … …, yN is valid; valid signals in the y0, y1, … … and yN correspond to 0, 1, … … and N in the amplitude limiting accumulated count value one by one; when the output of the controllable up-down counter is larger than N, yN in the N +1 decoding output signals is effective; when the yN in the decoded output signal is effective, adding a counting amplitude limiting control signal to be effective; the countdown clipping control signal is active when y0 is active in the decoded output signal.

5. The automated production line product count signal generating circuit of claim 4, wherein: the function of the anti-interference threshold selector is to make the first set signal valid when yN and one of N-XU decoded output signals adjacent to yN are valid; when one of y0 and the XD decoded output signals adjacent to y0 is valid, the second set signal is asserted; the XU is an anti-interference upper limit threshold value and is an integer which is greater than N/2 and less than or equal to N; XD is an anti-interference lower threshold value which is an integer greater than or equal to 0 and less than N/2.

6. The automated production line product count signal generating circuit of claim 5, wherein: the RS trigger has the function that when the input first setting signal is effective and the second setting signal is ineffective, the counting pulse is set to be 1; setting the counting pulse to 0 when the input first setting signal is invalid and the second setting signal is valid; when the input first set signal and the second set signal are both invalid, the state of the counting pulse is not changed.

7. The automated production line product count signal generating circuit of claim 5, wherein: the RS trigger has the function of setting the counting pulse to be 0 when the input first setting signal is effective and the second setting signal is ineffective; when the input first setting signal is invalid and the second setting signal is valid, setting the counting pulse to be 1; when the input first set signal and the second set signal are both invalid, the state of the counting pulse is not changed.

8. The automated production line product count signal generating circuit of any of claims 1-7, wherein: the reversible amplitude limiting counter consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.

Technical Field

The invention relates to the field of automatic production line control, in particular to a product counting signal generating circuit of an automatic production line.

Background

The photoelectric detection counting technology mainly depends on the light emitted by the infrared sensor to detect the product to be counted in the detection channel, and the receiving sensor generates a pulse signal due to the shielding of the product and is used for counting and recording. Due to the reasons of irregular shape, translation or shaking of slope sliding, falling overturning and the like of a product to be counted, counting pulses generated by the photoelectric sensor contain front edge shaking interference pulses and rear edge shaking interference pulses, and when the counting pulses are directly used as the counting pulses, counting errors can be caused.

The linear array CCD/CMOS technology is a continuous grain counting method, the CCD/CMOS camera can scan and count materials on a channel, and the feeding is stopped when a set quantity is reached.

Disclosure of Invention

In order to solve the problems of the existing automatic production line product counting signal generation, the invention provides a counting signal generation circuit of an automatic production line product, which comprises a counting signal sensor, a controllable reversible counter, a decoder, an anti-interference threshold selector, an RS trigger and an oscillator.

The counting signal sensor outputs counting initial pulses; the input of the controllable reversible counter is counting initial pulse, sampling clock pulse, counting-up amplitude limiting control signal and counting-down amplitude limiting control signal, and the output is amplitude limiting accumulated count value for counting the sampling clock pulse; the decoder inputs the amplitude limiting accumulated count value and outputs a decoding output signal, an adding counting amplitude limiting control signal and a subtracting counting amplitude limiting control signal; the input of the anti-interference threshold selector is a decoding output signal, and the output is a first set signal and a second set signal; the input of the RS trigger is a first set signal and a second set signal, and the output is a counting pulse; the oscillator outputs a sampling clock pulse.

The lower limit amplitude of the amplitude limiting accumulated count value is 0, and the upper limit amplitude is N; n is an integer greater than or equal to 2; the function of the controllable reversible counter is to be controlled in an up-counting state, a down-counting state or a limiting and keeping state by the level state of the counting initial pulse and the up-counting limiting control signal and the down-counting limiting control signal.

When the level state of the counting initial pulse is a counting control state and the counting amplitude limiting control signal is invalid, the controllable reversible counter is in the counting state; when the level state of the counting initial pulse is a count-down control state and the count-down amplitude limiting control signal is invalid, the controllable reversible counter is in the count-down state; otherwise the controllable up-down counter is in the clipping hold state.

The decoder has the function of decoding the amplitude limiting accumulated count value to obtain N +1 decoding output signals; the N +1 decoded output signals are composed of y0, y1, … …, yN, and only one of y0, y1, … …, yN is valid; valid signals in the y0, y1, … … and yN correspond to 0, 1, … … and N in the amplitude limiting accumulated count value one by one; when the output of the controllable up-down counter is larger than N, yN in the N +1 decoding output signals is effective; when the yN in the decoded output signal is effective, adding a counting amplitude limiting control signal to be effective; the countdown clipping control signal is active when y0 is active in the decoded output signal.

The function of the anti-interference threshold selector is to make the first set signal valid when yN and one of N-XU decoded output signals adjacent to yN are valid; when one of y0 and the XD decoded output signals adjacent to y0 is valid, the second set signal is asserted; the XU is an anti-interference upper limit threshold value and is an integer which is greater than N/2 and less than or equal to N; XD is an anti-interference lower threshold value which is an integer greater than or equal to 0 and less than N/2.

The RS trigger has the function that when the input first setting signal is effective and the second setting signal is ineffective, the counting pulse is set to be 1; setting the counting pulse to 0 when the input first setting signal is invalid and the second setting signal is valid; when the input first set signal and the second set signal are both invalid, the state of the counting pulse is not changed. The RS trigger has the function of setting the counting pulse to be 0 when the input first setting signal is effective and the second setting signal is ineffective; when the input first setting signal is invalid and the second setting signal is valid, setting the counting pulse to be 1; when the input first set signal and the second set signal are both invalid, the state of the counting pulse is not changed.

The reversible amplitude limiting counter consists of a reversible counter with single clock input and an amplitude limiting and adding and subtracting control circuit; the up-down counter has an up-down control input and an enable input.

The invention has the beneficial effects that: the circuit can automatically filter out positive narrow pulse interference and negative narrow pulse interference in a product counting pulse signal, and can also filter out continuous positive pulse interference or continuous negative pulse interference; the effect of filtering continuous pulse interference can be adjusted by adjusting the upper limit amplitude of the controllable reversible counter or changing the size of the anti-interference upper limit threshold and the anti-interference lower limit threshold.

Drawings

FIG. 1 is a diagram of an embodiment of an automatic production line product count signal generation circuit;

FIG. 2 is a count signal sensor embodiment;

fig. 3 shows an embodiment of the controllable up-down counter when N is 6;

fig. 4 is an embodiment of a decoder and immunity threshold selector when N is 6;

FIG. 5 is an RS flip-flop embodiment;

FIG. 6 is an oscillator embodiment;

fig. 7 is a schematic diagram of the anti-interference effect for the counting pulse when N is 6.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 shows an embodiment of an automatic production line product counting signal generating circuit. In fig. 1, the count signal sensor 100 outputs a count initial pulse P1; the controllable reversible counter 101 has the input of a counting initial pulse P1, a sampling clock pulse CLK, an adding counting amplitude limiting control signal KU and a subtracting counting amplitude limiting control signal KD and the output of an amplitude limiting accumulated count value X1, wherein the upper limit amplitude and the lower limit amplitude of the amplitude limiting accumulated count value X1 are respectively N and 0; the decoder 102 inputs the amplitude limiting accumulated count value X1 and outputs a decoding output signal X2, an up-counting amplitude limiting control signal KU and a down-counting amplitude limiting control signal KD; the input of the immunity threshold selector 103 is a decoding output signal X2, and the output is a first set signal SE1 and a second set signal RE 1; the RS flip-flop 104 has the input of a first set signal SE1 and a second set signal RE1, and the output of the RS flip-flop is a counting pulse P2; the oscillator 105 outputs a sampling clock pulse CLK.

In the following embodiment of the automatic production line product count signal generation circuit, N is 6.

FIG. 2 shows an embodiment of a counting signal sensor, which uses an ohm-dragon correlation type photoelectric switch, and a light projector 201 is E3 ZG-T61-S; the model of the light receiver 202 is E3ZG-T61-S, the output end OUT1 adopts NPN triode collector open circuit output, the resistor R201 is the collector resistor of the light receiver, and the counting initial pulse P1 is output from the end OUT1 of the light receiver 202. In fig. 2, + VCC is the power supply of the photoelectric switch, and GND is the common ground. The counting signal sensor can also adopt other correlation type photoelectric switches or light curtain sensors, and the pulse output form of the photoelectric switches or the light curtain sensors can also be other forms of output types. The counting signal sensor is arranged on a channel through which the product to be counted passes; the lanes may be single row product conveyor lanes, ramp roll off lanes or drop off lanes of product, or the like.

Fig. 3 shows an embodiment of the controllable up-down counter when N is 6. In fig. 3, T flip-flops FF1, FF2, FF3 and not gate FN1, and gates FA4, FA5, FA6 and FA7, or gates FO1 and FO2 form an up-down counter, and nand gates FA1, FA2 and FA3 form an amplitude limiting and up-down control circuit, which together form a controllable up-down counter; the trigger inputs CP of the T flip-flops FF1, FF2, FF3 are all active on the falling edge. The level states of the count start pulse P1 include a high level and a low level, and in the embodiment of fig. 3, the high level and the low level states of P1 are an up-count control state and a down-count control state, respectively. The high state and the low state of P1 may be set to the down-count control state and the up-count control state, respectively.

In the up-down counter input of fig. 3, CE is from the output of the amplitude limiting and up-down control circuit, and x11, x12 and its inverted input signal are from the non-inverted and inverted outputs of T flip-flops FF1, FF 2; the counting initial pulse P1 and the sampling clock pulse CLK come from the outside of the controllable reversible counter; CE is the enable input of the up-down counter, and the input to which P1 is connected is the up-down control input of the up-down counter. When CE is 0, all the outputs of and gates FA4, FA5, FA6, and FA7 are 0, all the outputs of or gates FO1 and FO2 are 0, all the T inputs of FF1, FF2, and FF3 are 0, and the output of the up-down counter is kept unchanged. When CE is 1 and P1 is 1, the T input of the T flip-flop FF1 is 1, and becomes a T' flip-flop; the P1 opens the and gates FA4, FA6, the T input of FF2 is 1 when x11 equals 1, the T input of FF3 is 1 when x11 and x12 simultaneously equal 1, the up-down counter operates in a synchronous up-count state, i.e. the controllable up-down counter performs up-count on the falling edge of the sampling clock CLK. When CE is 1 and P1 is 0, the T input of the T flip-flop FF1 is 1, and becomes a T' flip-flop; the P1 opens the and gates FA5, FA7 through the not gate FN1, the T input of FF2 is 1 when x11 equals 0, the T input of FF3 is 1 when x11, x12 simultaneously equals 0, the up-down counter operates in a synchronous down-count state, i.e., the controllable up-down counter performs down-count on the falling edge of the sampling clock CLK. When P1 is connected to the up/down control input terminal of the up/down counter in fig. 3 through the inverter, the high level and the low level of P1 control the controllable up/down counter to be in the down-counting state and the up-counting state, respectively.

The input signal plus-counting amplitude limiting control signal KU, the minus-counting amplitude limiting control signal KD and the counting initial pulse P1 of the amplitude limiting and plus-minus control circuit in the figure 3 are all from the outside of the controllable reversible counter, the plus-counting amplitude limiting control signal KU and the minus-counting amplitude limiting control signal KD are both effective at low level, namely, the plus-counting amplitude limiting is carried out when KU is 0, and the minus-counting amplitude limiting is carried out when KD is 0. When P1 is 1 and KU is 0, the nand gate FA1 outputs low, the and gate FA3 outputs low, and CE is 0; alternatively, when P1 is 0 and KD is 0, the nand gate FA2 outputs low, and the and gate FA3 outputs low, CE being 0. When CE is 0, the controllable up-down counter is in a slice hold state and does not count on the falling edge of the sampling clock pulse CLK.

In fig. 3, the T flip-flops FF3, FF2, FF1 are controlled by the state of P1 whether to count and to count up or down only at the time of the falling edge of the sampling clock CLK input at their clock input CP; at the non-falling edge time of CLK, changes in P1 do not affect the x13, x12, x11 output by FF3, FF2, FF 1. The output of the controllable up-down counter is controlled by the value of P1 at the falling edge of the sampling clock pulse, i.e. the output of the controllable up-down counter is related to the value of the sample at the falling edge of the sampling clock pulse P1 and is controlled by the value of the sample at the falling edge of the sampling clock pulse P1. The output of the controllable up-down counter can also be controlled to change by the value of P1 at the time of the rising edge of the sampling clock pulse.

The T flip-flop in fig. 3 may be formed using a JK flip-flop or a D flip-flop, for example, the J, K input terminals of the JK flip-flop are connected in parallel as the T input terminal. When N is other values, the number of T flip-flops and corresponding circuits in fig. 3 may be increased or decreased, and the clipping and addition/subtraction control circuits may be changed. The controllable reversible counter can also be formed by combining a gate with a reversible counter such as 74HC191, CD4516 and the like.

The decoder has the function of decoding the amplitude limiting accumulated count value to obtain N +1 decoding output signals; the N +1 decoding output signals consist of y0, y1, … … and yN, and only one of y0, y1, … … and yN is valid; valid signals in y0, y1, … … and yN correspond to 0, 1, … … and N in the amplitude limiting accumulated count value one by one; when the output of the controllable up-down counter is greater than N, yN in the N +1 decoded output signals is valid. Fig. 4 shows an embodiment of the decoder and immunity threshold selector when N is 6. The FD1 is a 3-line-8-line decoder 74HC138, the FA0 is an and gate, and the FD1 and the FA0 together form a decoder. The 3-bit binary outputs X13, X12 and X11 of the clipped accumulated count value X1 are respectively connected to the 3-bit address input terminals a2, a1 and a0 of the FD1, the 3 enable input terminals E1, E2 and E3 of the FD1 are respectively connected with 0, 0 and 1, and the FD1 works in a decoding state. X2 has 7 decoded output signals, of which y0,y1, y2, y3, y4 and y5 are directly output from the decoding output end of the FD2

Output, y6 is output from the output of AND gate FA0, 2 inputs of AND gate FA0 are connected to FD1

An output end; when the clipped accumulated count value X1 is equal to N, i.e., equal to 6, and the clipped accumulated count value X1 is greater than N, i.e., equal to 7, in the overrun output state, yN, i.e., y6 is valid. Y0, y1, y2, y3, y4, y5 and y6 which are all active low constitute decoded output signals X2, y0, y1, y2, y3, y4, y5 and y6 which are respectively in one-to-one correspondence with 0, 1, 2, 3, 4, 5 and 6 of the sliced accumulated count value X1. The over-limit output state of the clipping accumulated count value X1 is only X1-7, and the decoding output end of FD1The signals correspond; the overrun state of the controllable reversible counter is possible to appear only in the initial state when the system is started, and the output overrun state can not appear after the controllable reversible counter enters a normal amplitude limiting counting interval after counting down. The function of the decoder can be realized by 1 or more decoder chips or a combinational logic circuit composed of gates.

In fig. 4, y6 in the decoded output signal is simultaneously output as the count-up slice control signal KU; when the clipping accumulated count value X1 reaches N, i.e., equal to 6, and X1 is greater than N, i.e., in the overrun output state, KU is equal to 0, and the controllable up-down counter is controlled not to perform the up-counting. Y0 in the decoded output signal is simultaneously output as a countdown amplitude limiting control signal KD; when the clipped cumulative count value X1 reaches 0, i.e., is equal to 0, KD becomes 0, and the controllable up-down counter is controlled not to perform down-counting. The realized function is that when the yN in the decoding output signal is effective, the counting amplitude limiting control signal KU is added to be effective; the countdown clipping control signal KD is active when y0 is active in the decoded output signal.

The function of the anti-interference threshold selector is to make the first set signal valid when yN and one of N-XU decoded output signals adjacent to yN are valid; the second set signal is asserted when one of y0 and the XD decoded output signals adjacent to y0 are asserted. When N is equal to 6, the interference resistance upper threshold XU has a value range of 4, 5, 6, and the interference resistance lower threshold XD has a value range of 0, 1, 2. In fig. 4, the embodiment of the threshold selector for immunity against interference is composed of nand gates FA8 and FA9, y6 and y5 are connected to the input end of the nand gate FA8, and as long as the clip accumulated count value X1 is greater than or equal to 5, that is, any 1 of y6 and 1 decoded output signal y5 adjacent to y6 is valid, the first set signal SE1 is valid, and the upper threshold value for immunity against interference XU is equal to 5; y0 is connected to the input end of the nand gate FA9 (FA 9 plays the role of not gate at this time), y0 is valid only when the clip accumulated count value X1 is equal to 0, the second set signal RE1 is valid, and the interference resistance lower limit threshold XD is equal to 0 at this time. Changing the number of decoding output signals connected to the input end of the NAND gate FA8, and only connecting y6 to the input end of the NAND gate FA8, wherein only the amplitude limiting accumulated count value X1 is greater than or equal to 6, namely y6 is effective, the first set signal SE1 is effective, and at the moment, the anti-interference upper limit threshold XU is equal to 6; when y6, y5 and y4 are connected to the input end of the nand gate FA8, as long as the clip accumulated count value X1 is greater than or equal to 4, that is, any 1 of y6 and the 2 decoding output signals y5 and y4 adjacent to y6 is valid, the first set signal SE1 is valid, and at this time, the upper interference resistance threshold XU is equal to 4; when y0 and y1 are connected to the input end of the nand gate FA9, as long as the clip accumulated count value X1 is less than or equal to 1, that is, any 1 of y0 and 1 decoded output signal y1 adjacent to y0 is valid, the second set signal RE1 is valid, and at this time, the lower interference resistance threshold XD is equal to 1; when y0, y1, and y2 are connected to the input terminal of the nand gate FA9, as long as the clip accumulated count value X1 is less than or equal to 2, that is, any 1 of y0 and the 2 decoded output signals y1 and y2 adjacent to y0 is valid, the second set signal RE1 is valid, and the interference rejection lower limit threshold XD is equal to 1.

In fig. 4, the high levels of the first set signal SE1 and the second set signal RE1 are active; the nand gates FA8 and FA9 are changed to and gates, and the first set signal SE1 and the second set signal RE1 become active low. Selecting one of yN and N-XU decoded output signals adjacent to yN to be valid, and selecting one of y0 and XD decoded output signals adjacent to y0 to be valid, and making the second set signal valid as an or logic; in this embodiment, the decoder output is active low and the immunity threshold selector uses and gates to perform the or function. When the output of the decoder is active high, the immunity threshold selector may use an or gate or a nor gate to implement the above-mentioned or logic function.

Fig. 5 is an RS flip-flop embodiment. In fig. 5, the nor gates FO3 and FO4 constitute RS flip-flops, and the first set signal SE1 and the second set signal RE1 are both active high; the first set signal SE1 is a set signal of an RS flip-flop, and the second set signal RE1 is a reset signal of the RS flip-flop; the count pulse P2 is output from the non-inverting output terminal of the RS flip-flop. When SE1 is active and RE1 is inactive, a count pulse P2 output from the in-phase output terminal FO4 is set to 1; when the SE1 is invalid and the RE1 is valid, setting the counting pulse P2 to be 0; when both SE1 and RE1 are inactive, the state of the count pulse P2 is unchanged. The count pulse P2 may also be output from the inverting output, i.e., the output of the or gate FO 3. The RS flip-flop may also take other forms.

Fig. 6 is an oscillator embodiment. In fig. 6, the CMOS not gates FN2 and FN3, the resistor R97, and the capacitor C97 constitute a multivibrator, and the sampling clock CLK is output from the FN3 output terminal. The frequency of CLK is changed by adjusting the values of resistor R97 and capacitor C97. The oscillator may also employ other types of multivibrators.

In the embodiment where N is 6, the interference-resistant upper threshold XU is 5, and the interference-resistant lower threshold XD is 0; when the amplitude limiting accumulated count value X1 is greater than or equal to 5, the output SE1 is at high level, and the count pulse P2 is set to 1; when the clip accumulated count value X1 is equal to or less than 0, the output RE1 is at a high level, and the count pulse P2 is set to 0.

Fig. 7 is a schematic diagram of the anti-interference effect for the counting pulse when N is 6. In fig. 7, a sampling value P1 of 15 sampling clock pulses CLK for counting the initial pulse P1, a sliced accumulated count value X1 of each sampling point, and a resultant count pulse P2 are shown. The sampling value P1 is the value of the initial pulse P1 counted when the sampling clock pulse CLK counts edges; the controllable invertible counter is controlled by the 2 states of the counting initial pulse to count up or down the sampling clock pulse CLK respectively, and the controllable invertible counter is controlled by the value of the counting initial pulse P1 when the sampling clock pulse CLK counts edges to count up or down the sampling clock pulse CLK respectively. The 6 sampled values P1 of the CLK pair count initial pulse P1, which are set before sample point 1 of CLK in fig. 7, are all 0, and the count pulse P2 is 0. In fig. 7, positive pulse interference occurs before sample 2 of CLK and after sample 3 of count initial pulse P1, which results in that X1 samples at sample 2 and sample 3 to obtain interference value 1 of P1; the counting initial pulse P1 shows a positive narrow pulse interference between sample point 4 and sample point 5 of CLK, but the positive narrow pulse width is smaller than the sampling period and between 2 sample points, and the sampling result is not affected, i.e. the sampling process automatically filters out the positive narrow pulse interference. The counting initial pulse P1 starts to change from 0 to 1 after the sampling point 6 of CLK, 2 times of edge jitter occurs in the process of changing from 0 to 1, wherein the 2 nd positive narrow pulse jitter interference is automatically filtered by the sampling process, and the values of the sampling point 7 and the sampling point 8 are 1 and 0 respectively. In fig. 7, the sample value P1, the count pulse P2, and the clipped cumulative count value X1 obtained at sample point 1 to sample point 15 of the clock pulse CLK are shown in table 1.

Table 1 sample points 1-15, sample value P1, clip count cumulative value X1, and count pulse P2

Observing the conditions of the sampling points in the table 1, wherein at the sampling point 1, X1 is less than or equal to XD, RE1 is effective, SE1 is ineffective, and P2 is set to be 0; at sample points 2-4, X1 is greater than XD and less than XU, SE1 and RE1 are both inactive, and P2 is maintained at 0; at sampling points 5-6, X1 is less than or equal to XD, RE1 is effective, SE1 is ineffective, and P2 is set to 0; at sample point 7, X1 is greater than XD and less than XU, both SE1 and RE1 are inactive, and P2 remains 0; at sampling point 8, X1 is less than or equal to XD, RE1 is effective, SE1 is ineffective, and P2 is set to 0; at sample points 9-12, X1 is greater than XD and less than XU, SE1 and RE1 are both inactive, and P2 is maintained at 0; at sampling points 13-15, X1 is equal to or greater than XU, SE1 is active, RE1 is inactive, and P2 is set to 1. When N is 6, the counting interval of the controllable reversible counter is 0-N; at sample 5 in table 1, X1 has reached the lower limit amplitude of 0, at sample 6, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also no longer counted down, and X1 remains at the lower limit amplitude of 0; at sample 14, X1 has reached the upper limit amplitude of 6, at sample 15, P1 ═ 1 (i.e., at this time, P1 ═ 1), X1 is also not counted up, and X1 remains at the upper limit amplitude of 6.

Fig. 7 shows the anti-glitch effect of the count signal generating circuit when the count initial pulse P1 is 0, and the condition and process of the count initial pulse P1 changing from 0 to 1. The counter signal generating circuit has the same conditions and processes of resisting negative pulse interference when the counter initial pulse P1 is 1, changing the counter initial pulse P1 from 1 to 0, resisting positive pulse interference when the counter initial pulse P1 is 0, and changing the counter initial pulse P1 from 0 to 1.

The 6 sampling values P1 of the CLK pair count initial pulse P1 before the sampling point 31 of the clock pulse CLK are all 1, and the count pulse P2 is 1. The sample value P1, the clipped cumulative count value X1 and the count pulse P2 from sample point 31 to sample point 45 are shown in table 2.

Sample values P1, clipped cumulative count X1 and count pulses P2 of samples 31-45 of table 2

Observing the conditions of the sampling points in the table 2, wherein X1 is more than or equal to XU at the sampling points 31-32, SE1 is effective, RE1 is ineffective, and P2 is set to be 1; at sample point 33, X1 is greater than XD and less than XU, both SE1 and RE1 are inactive, and P2 remains 1; at a sampling point 34, X1 is larger than or equal to XU, SE1 is effective, RE1 is ineffective, and P2 is set to be 1; at sample points 35-42, X1 is greater than XD and less than XU, SE1 and RE1 are both inactive, and P2 is maintained at 1; since the sampling value P1 is in the state of more than 0 and less than 1 between the sampling points 31-42, the result of the accumulation counting of the controllable invertible counter is that the amplitude limiting accumulated count value X1 tends to decrease until the sampling point 43, X1 is less than or equal to XD, RE1 is valid, SE1 is invalid, and P2 is set to 0; at sample points 44-45, X1 is less than or equal to XD, RE1 is active, SE1 is inactive, and P2 is set to 0. At sample 43 in table 2, X1 has reached the lower limit amplitude of 0, and at samples 44-45, P1 ═ 0 (i.e., at this time, P1 ═ 0), X1 is also not counted down, and X1 is maintained at the lower limit amplitude of 0.

In the present embodiment, where N is 6, the counting pulse P2 and the counting start pulse P1 are in phase relationship. If the function of the controllable up-down counter is changed to: when P1 is equal to 1, the controllable reversible counter counts down; when P1 is equal to 0, the controllable up-down counter performs count-up, and there is an inverse correlation between the count pulse P2 and the count initial pulse P1. Or the counting pulse P2 is changed to be output from the nor gate FO3 in fig. 6, the function is changed to set the counting pulse P2 to 0 when SE1 is active and RE1 is inactive; when the SE1 is invalid and the RE1 is valid, setting the counting pulse P2 to be 1; when both SE1 and RE1 are inactive, the state of the count pulse P2 is unchanged; at this time, there is an inverse correlation between the counting pulse P2 and the counting start pulse P1. If the above modification is performed simultaneously, the counting pulse P2 and the counting start pulse P1 are in phase.

Taking the in-phase relationship between the count pulse P2 and the count initial pulse P1 as an example, it can be concluded from tables 1 and 2 and the working principle of the circuit that, because the controllable reversible counter has an accumulation effect, when the number of 1's in the sample value of the count initial pulse P1 is greater than 0 within a period of time, the amplitude-limited accumulated count value X1 tends to increase, so that X1 is greater than or equal to XU and the count pulse P2 is set to 1; when the number of 0's is more than 1 in the sampling values of the count initial pulse P1 within a period of time, the slice accumulated count value X1 tends to decrease, X1 is made less than or equal to XD, and the count pulse P2 is set to 0; the characteristic enables the controllable reversible counter of the circuit of the invention to have self-starting capability, amplitude limiting function and count 0 in the sampling value P1 of the initial pulse P1, so that the controllable reversible counter enters a normal amplitude limiting counting interval to carry out amplitude limiting, addition and subtraction counting.

Because the upper interference resistance threshold XU is an integer greater than N/2 and less than or equal to N, the lower interference resistance threshold XD is an integer greater than or equal to 0 and less than N/2, and the first set signal SE1 and the second set signal RE1 cannot be simultaneously effective, the output of the RS flip-flop cannot be uncertain in logic state.

The counting pulse P2 and the counting start pulse P1 are in phase. When the counting initial pulse P1 enables the amplitude limiting accumulated count value X1 to be smaller than or equal to the interference resistance lower limit threshold value XD and the counting pulse P2 is set to be 0, as long as the amplitude limiting accumulated count value X1 is smaller than the interference resistance upper limit threshold value XU all the time, the counting pulse P2 cannot become 1; when the initial pulse P1 is counted so that the clip accumulated count value X1 is equal to or greater than the interference resistance upper threshold XU and the count pulse P2 is set to 1, the count pulse P2 does not become 0 as long as the clip accumulated count value X1 is always greater than the interference resistance lower threshold XD. When both P1 and P2 are low, a positive pulse corresponding to the positive pulse in P1 can be output from P2 as long as the positive pulse appearing in P1 causes values of 1 to appear continuously in the P1 sample values at equal to or more than XU, or, the positive pulse appearing in the P1 sample values at XU +1, and so on; when both P1 and P2 are at a high level, as long as a negative pulse occurring in P1 causes values equal to or greater than N-XD of 0 to continuously occur in the P1 sample value, or N-XD +1 of 0 to continuously occur in N-XD + 2P 1 sample values, or the like, a negative pulse corresponding to the negative pulse in P1 can be output from P2. When the counting initial pulse P1 is changed from 0 to 1, the counting pulse P2 needs the clipping accumulated count value X1 to be delayed by adding a count for several sampling pulse periods, so that the clipping accumulated count value X1 is greater than or equal to the anti-interference upper limit threshold XU, and P2 is set to 1; when the count initial pulse P1 changes from 1 to 0, the count pulse P2 needs the clip accumulated count value X1 to be delayed by counting down for several sampling pulse periods, so that the clip accumulated count value X1 is less than or equal to the interference resistance lower limit threshold XD, and P2 is set to 0. When the value of the anti-interference upper limit threshold XU is larger, the condition that the counting pulse P2 is changed from 0 to 1 is more rigorous, and the low-level positive pulse interference resisting effect of the circuit is better; when the value of the anti-interference lower limit threshold value XD is smaller, the condition that the counting pulse P2 is changed from 1 to 0 is more rigorous, and the high-level negative pulse interference resisting effect of the circuit is better. When the value of N is increased, the conditions that the counting pulse P2 is changed from 0 to 1 and from 1 to 0 are strictly changed by the counting signal generating circuit, the anti-interference effect is improved, but the delay time of the counting pulse P2 relative to the counting initial pulse P1 is increased; when the value of N becomes small, the condition that the count pulse P2 changes from 0 to 1 and from 1 to 0 becomes wide, the interference suppression effect becomes small, but the delay time of the count pulse P2 with respect to the count start pulse P1 becomes small.

The period of the sampling clock pulse is determined based on the pulse width of the count initial pulse P1, the changing speed, and the width of the interference pulse. For example, if the pulse width of the counting start pulse P1 on a certain production line is at least 10ms, the jitter interference is usually not more than one tenth of the pulse width of the counting start pulse P1, so the period of the sampling clock pulse can be selected to be about 1ms, and N is in the range of 3 to 7.

All or part of functions of a controllable reversible counter, an anti-interference threshold selector, a decoder, an RS trigger and an oscillator in the counting signal generating circuit can be realized by PAL, GAL, CPLD, FPGA or other programmable logic devices and logic units.

Except for the technical features described in the specification, the method is the conventional technology which is mastered by a person skilled in the art.