阅读说明：本技术 用于时间数字转换器的温度计码转二进制码电路 (Thermometer code to binary code circuit for time-to-digital converter ) 是由 谢生 郭晓东 于 2019-09-25 设计创作，主要内容包括：本发明公开了一种用于时间数字转换器的温度计码转二进制码电路,所述电路包括：LUT筛选电路和RAM存储电路,温度计码作为输入信号,接入LUT筛选电路,筛选电路中的LUT单元对输入信号的高5位取反,将取反结果与输入信号的最低位相与,得到输出信号,并将输出信号作为控制信号接入RAM存储电路的读使能端；当读使能端拉高时,对应RAM存储电路中的二进制码在下一个时钟上升沿被读出,实现温度计码向二进制码的转换。本发明解决了基于FPGA的时间数字转换器中译码过程中存在的“冒泡”问题,提高了FPGA型时间数字转换器的整体性能。(The invention discloses a thermometer code to binary code circuit for a time-to-digital converter, which comprises: the temperature meter code is used as an input signal and is accessed to the LUT screening circuit, an LUT unit in the screening circuit inverts the high 5 bits of the input signal, the inversion result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal and is accessed to a read enable end of the RAM storage circuit; when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized. The invention solves the problem of bubbling in the decoding process of the FPGA-based time-to-digital converter, and improves the overall performance of the FPGA-based time-to-digital converter.)

1. A thermometer code to binary code circuit for a time to digital converter, the circuit comprising: an LUT screening circuit and a RAM memory circuit,

the thermometer code is used as an input signal and is accessed into an LUT screening circuit, an LUT unit in the screening circuit inverts the high 5 bits of the input signal, the inversion result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal and is accessed into a read enable end of an RAM storage circuit;

when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized.

2. The thermometer code to binary code circuit for a time-to-digital converter of claim 1, further comprising: and storing the binary codes corresponding to the thermometer codes into a RAM storage circuit.

3. The thermometer code to binary code circuit for time-to-digital converter as claimed in claim 1, wherein said LUT filtering circuit filters out bubble code segments by logic operation and outputs a read enable signal.

4. The thermometer code to binary code circuit for time-to-digital converter as claimed in claim 3, wherein said LUT filter circuit filters out bubble code segments by logic operation specifically as:

sequentially inputting every adjacent 6 bits into a corresponding LUT from the 0 th bit to the highest bit;

the LUT screening circuit only outputs logic 1 on the LUT with 000001 code segment as input, and the other LUTs output logic 0, thereby enabling the corresponding RAM to read out binary numbers.

Technical Field

The invention relates to the field of integrated circuit measurement, in particular to a decoding circuit which is applied to a time-to-digital converter based on an FPGA and used for converting thermometer codes into binary codes.

Background

The time interval measurement technology has great significance to national economy and national defense industrial construction, and is an accurate time interval measurement technology, in particular to a picosecond (1ps is 10 ═ 10)¹²s) order of magnitude is more important. The method has very important application in the theoretical research fields of molecular biology, nuclear physical detection, astronomical observation and the like, and the engineering practice fields of laser ranging, high-precision positioning, food and drug safety monitoring and the like.

Currently, the most widely used high-precision time interval measurement technology is the time To Digital Converter (TDC) technology, and the most important technical index is the measurement precision. Most industrial-scale time-to-digital converters are implemented primarily using Application Specific Integrated Circuits (ASICs). Compared with an ASIC type TDC, the TDC based on the FPGA has the advantages of low development cost, short period and the like. Meanwhile, with the progress of the manufacturing technology of the integrated circuit, the manufacturing process of the FPGA is greatly improved, and the delay of the internal connecting line and the logic unit of the FPGA is smaller and smaller, so that the TDC can also achieve high measurement precision.

In the FPGA-based time-to-digital converter, a tap signal output by a delay chain is a thermometer code, and a decoding circuit is required to convert the thermometer code into a binary code for subsequent numerical calculation. The accuracy and speed of the decoding circuit greatly affect the measurement accuracy and speed of the time-to-digital converter. However, the thermometer code of the tap output may exhibit irregularities, so-called "bubbling", for various reasons, such as: the FPGA chip has process deviation in the manufacturing process, so that the delay time of carry units in a carry chain is inconsistent, taking Xilinx Artix 7 series FPGA as an example, a large delay with the carry time of 91ps appears in every 4 adjacent carry units, and as the carry time of the carry unit is large, the set-up time of a trigger may not be met, so that a tap value cannot be normally latched. The carry time of the next stage carry unit is shorter, and the tap signal can be correctly latched by a trigger, so that the tail end of the valid bit of the thermometer code generates a bubbling phenomenon; for another example: clock signals in the FPGA clock network cannot reach each trigger at the same time, but certain clock skew exists, and if the clock skew of two adjacent triggers used for latching carry signals in a carry chain is large, the trigger at the next stage latches the carry signals in advance of the trigger at the previous stage, and the bubbling phenomenon can also be caused.

The serious bubbling phenomenon can greatly reduce the precision of converting thermometer code into binary code (decoding), thereby influencing the precision of a time-to-digital converter and bringing great difficulty to the design of a thermometer code into binary code circuit. Document [1] proposes a method and a device for decoding and converting thermometer codes into binary codes based on an FPGA chip. The principle is that the thermometer code is divided into a plurality of window values through a sliding window, and the one-hot codes corresponding to the thermometer code are obtained by sequencing true values corresponding to the window values, so that bubble error correction is realized. Meanwhile, the one-hot code is converted into a binary code by using a pipeline structured coding algorithm. The thermometer code to binary code circuit disclosed by the document can well realize the filtering of a thermometer code 'bubble' code segment, but the decoding algorithm is complex, the utilization rate of FPGA resources is not high, and the decoding time is long. Meanwhile, the decoder disclosed in the document has poor time sequence characteristics, and a pipeline structure is used for eliminating the time sequence problem caused by too large logic path delay, so that more trigger resources are occupied.

Reference documents:

[1]Wang Y,Kuang J,Liu C,et al.A 3.9-ps RMS Precision Time-to-DigitalConverter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA[J].IEEETransactions on Nuclear Science,2017,64(10):2713-2718.

disclosure of Invention

In order to solve the problem of bubbling in the decoding process of the FPGA-based time-to-digital converter, the invention designs a thermometer code-to-binary code circuit with strong fault tolerance, high decoding speed and good time sequence characteristic from the specific hardware circuit level, thereby improving the overall performance of the FPGA-based time-to-digital converter, and the details are described in the following:

a thermometer code to binary code circuit for a time-to-digital converter, the circuit comprising: an LUT screening circuit and a RAM memory circuit,

the thermometer code is used as an input signal and is accessed into an LUT screening circuit, an LUT unit in the screening circuit inverts the high 5 bits of the input signal, the inversion result is compared with the lowest bit of the input signal to obtain an output signal, and the output signal is used as a control signal and is accessed into a read enable end of an RAM storage circuit;

when the read enable terminal is pulled high, the binary code in the corresponding RAM storage circuit is read out at the next clock rising edge, and the conversion from the thermometer code to the binary code is realized.

Wherein the circuit further comprises: and storing the binary codes corresponding to the thermometer codes into a RAM storage circuit.

Further, the LUT screening circuit filters out bubble code segments through logic operation and outputs a read enable signal.

The LUT screening circuit specifically filters out the bubble code segment through logic operation as follows:

sequentially inputting every adjacent 6 bits into a corresponding LUT from the 0 th bit to the highest bit;

the LUT screening circuit only outputs logic 1 on the LUT with 000001 code segment as input, and the other LUTs output logic 0, thereby enabling the corresponding RAM to read out binary numbers.

The technical scheme provided by the invention has the beneficial effects that:

1. the invention uses the RAM unit to realize the conversion from thermometer code to binary code, does not use complex combinational logic, and can keep good time sequence characteristic even if a pipeline structure is not inserted;

2. the invention carries out logical negation and logical AND operation on every adjacent 6 bits in the thermometer code by using an LUT (lookup table) screening circuit, accurately identifies the 000001 code segment, filters the bubbling code segment, and can carry out fault-tolerant decoding on the thermometer code with 4 bubbling bits at most;

3. the invention stores the binary codes corresponding to each thermometer code into the corresponding RAM in advance by initializing the memory, and can read the binary codes by only one clock cycle in a RAM reading mode, thereby realizing the conversion from the thermometer codes to the binary codes and effectively improving the decoding speed.

In conclusion, the thermometer code to binary code circuit designed by the invention can effectively improve the decoding precision and speed, and is beneficial to improving the overall performance of the FPGA type time-to-digital converter.

Drawings

FIG. 1 is a schematic diagram of a thermometer code to binary code circuit;

FIG. 2 is a block diagram of a thermometer code to binary code circuit;

FIG. 3 is a logic diagram of an internal implementation of a LUT;

FIG. 4 is a schematic view of a thermometer code;

fig. 5 is a structural diagram of a RAM cell.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.