Array substrate, manufacturing method and display panel
阅读说明:本技术 阵列基板及制作方法和显示面板 (Array substrate, manufacturing method and display panel ) 是由 钟德镇 郑会龙 张军 杨国栋 于 2019-09-17 设计创作,主要内容包括:本发明提供一种阵列基板,包括在阵列基板的公共电极上覆盖第二绝缘层;形成在第二绝缘层上的第三绝缘层;形成在第三绝缘层上的相互间隔的多个像素电极,每个像素电极通过接触孔与一个对应的TFT导电连接;其中,每个像素电极为具有像素电极条与第一狭缝的图案化结构,第三绝缘层被蚀刻而形成相互间隔的多个绝缘层图案,每个绝缘层图案与一个像素电极条相对应,绝缘层图案与像素电极条具有相同的图案且两者上下相互重叠,第二绝缘层采用能被干蚀刻的材料,第三绝缘层采用能被湿蚀刻的材料。本发明还提供一种阵列基板的制作方法及显示面板。该阵列基板能够改善绝缘层蚀刻后的膜厚均一性问题,从而降低面内不同区域驱动电压的差异。(The invention provides an array substrate, which comprises a second insulating layer covered on a common electrode of the array substrate; a third insulating layer formed on the second insulating layer; a plurality of pixel electrodes formed on the third insulating layer at intervals, each of the pixel electrodes being electrically connected to a corresponding one of the TFTs through the contact hole; each pixel electrode is a patterning structure with a pixel electrode strip and a first slit, the third insulating layer is etched to form a plurality of insulating layer patterns which are spaced from each other, each insulating layer pattern corresponds to one pixel electrode strip, the insulating layer patterns and the pixel electrode strips have the same pattern and are overlapped with each other up and down, the second insulating layer is made of a material capable of being dry-etched, and the third insulating layer is made of a material capable of being wet-etched. The invention also provides a manufacturing method of the array substrate and a display panel. The array substrate can improve the problem of film thickness uniformity of the etched insulating layer, so that the difference of driving voltages of different areas in the surface is reduced.)
1. An array substrate, comprising:
a substrate (11);
a plurality of TFTs (12) formed in an array on the substrate (11);
a first insulating layer (13) covering the plurality of TFTs (12);
a flat layer (14) covering the first insulating layer (13);
a common electrode (15) formed on the planarization layer (14);
a second insulating layer (16) covering the common electrode (15);
a third insulating layer (17) formed on the second insulating layer (16);
a plurality of pixel electrodes (18) formed on the third insulating layer (17) and spaced from each other, each pixel electrode (18) being electrically connected to a corresponding one of the TFTs (12) through a contact hole (19);
wherein each pixel electrode (18) is a patterned structure having a pixel electrode bar (181) and a first slit (182), the third insulating layer (17) is etched to form a plurality of insulating layer patterns (170) spaced from each other, each insulating layer pattern (170) corresponds to one pixel electrode (18), the insulating layer patterns (170) and the pixel electrodes (18) have the same pattern and are overlapped with each other in an up-and-down manner, the second insulating layer (16) is made of a material capable of being dry-etched, and the third insulating layer (17) is made of a material capable of being wet-etched.
2. The array substrate according to claim 1, wherein the second insulating layer (16) is made of silicon nitride, silicon oxide or silicon oxynitride, and the third insulating layer (17) is made of aluminum oxide or zinc oxide.
3. The array substrate of claim 1, wherein the film thickness of the third insulating layer (17) is proportional to the number of pixels of the array substrate.
4. The array substrate of claim 1, wherein each of the insulating layer patterns (170) has an insulating bar (171) and a second slit (172), the insulating bar (171) is overlapped with the pixel electrode bar (181) up and down, and the second slit (172) is up and down corresponding to and communicated with the first slit (182).
5. The array substrate of claim 4, wherein the second insulating layer (16) is exposed through the first slit (182) and the second slit (172).
6. The array substrate according to claim 1, wherein the contact hole (19) penetrates through the third insulating layer (17), the second insulating layer (16), the planarization layer (14) and the first insulating layer (13) to expose one conductive electrode corresponding to the TFT (12), and each pixel electrode (18) is electrically connected to the exposed conductive electrode of the corresponding TFT (12) through the contact hole (19).
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming a plurality of TFTs (12) arranged in an array on a substrate (11);
forming a first insulating layer (13) covering the plurality of TFTs (12);
forming a planarization layer (14) covering the first insulating layer (13), and patterning the planarization layer (14), removing the planarization layer (14) at a position corresponding to each contact hole (19) to expose the first insulating layer (13) thereunder;
depositing a first transparent conductive layer (150) on the planarization layer (14), and etching-patterning the first transparent conductive layer (150), removing the first transparent conductive layer (150) at a position corresponding to each TFT (12) to expose the planarization layer (14) thereunder, the first transparent conductive layer (150) forming a common electrode (15) after patterning;
forming a second insulating layer (16) covering the common electrode (15), the second insulating layer (16) also covering the exposed planarization layer (14) and the first insulating layer (13) at the same time;
forming a third insulating layer (17) covering the second insulating layer (16), wherein the second insulating layer (16) is made of a material capable of being dry-etched, the third insulating layer (17) is made of a material capable of being wet-etched, then the third insulating layer (17) at the position of each contact hole (19) is removed by a wet etching process, and then the second insulating layer (16) and the first insulating layer (13) at the position of each contact hole (19) are removed by a dry etching process, so that one conductive electrode (125) of each TFT (12) is exposed at the position of each contact hole (19);
depositing a second transparent conductive layer (180) on the third insulating layer (17), wherein the second transparent conductive layer (180) is filled in the contact hole (19) of each TFT (12) and is in contact with the exposed conductive electrode (125) of each TFT (12);
coating a photoresist (40) on the second transparent conductive layer (180), exposing and developing the photoresist (40) by using a photomask (50), and etching and patterning the second transparent conductive layer (180) by using the remained photoresist (40) as a mask, wherein the second transparent conductive layer (180) forms a plurality of pixel electrodes (18) after etching and patterning, each pixel electrode (18) is a patterned structure with a pixel electrode strip (181) and a first slit (182), and each pixel electrode (18) is electrically connected with one conductive electrode (125) of a corresponding TFT (12) through the contact hole (19);
after the second transparent conductive layer (180) is etched and patterned to form a plurality of pixel electrodes (18), continuing to perform a wet etching process on the third insulating layer (17) by using the remaining photoresist (40) as a mask, so that the third insulating layer (17) is etched to form a plurality of insulating layer patterns (170) spaced from each other, each insulating layer pattern (170) corresponding to one pixel electrode (18), the insulating layer patterns (170) and the pixel electrodes (18) having the same pattern and overlapping each other;
the photoresist (40) is removed.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming a plurality of TFTs (12) arranged in an array on a substrate (11);
forming a first insulating layer (13) covering the plurality of TFTs (12);
forming a planarization layer (14) covering the first insulating layer (13), and patterning the planarization layer (14), removing the planarization layer (14) at a position corresponding to each contact hole (19) to expose the first insulating layer (13) thereunder;
depositing a first transparent conductive layer (150) on the planarization layer (14), and etching-patterning the first transparent conductive layer (150), removing the first transparent conductive layer (150) at a position corresponding to each TFT (12) to expose the planarization layer (14) thereunder, the first transparent conductive layer (150) forming a common electrode (15) after patterning;
forming a second insulating layer (16) covering the common electrode (15), the second insulating layer (16) also covering the exposed planarization layer (14) and the first insulating layer (13) at the same time;
removing the second insulating layer (16) at the location of each contact hole (19) using a dry etching process to expose the underlying first insulating layer (13) at the location of each contact hole (19);
forming a third insulating layer (17) covering the second insulating layer (16), the third insulating layer (17) also covering the exposed first insulating layer (13), wherein the second insulating layer (16) is made of a material capable of being dry-etched, the third insulating layer (17) is made of a material capable of being wet-etched, then the third insulating layer (17) at the position of each contact hole (19) is removed by a wet etching process, and then the first insulating layer (13) at the position of each contact hole (19) is removed by a dry etching process, so as to expose one conductive electrode (125) of each TFT (12) at the position of each contact hole (19);
depositing a second transparent conductive layer (180) on the third insulating layer (17), wherein the second transparent conductive layer (180) is filled in the contact hole (19) of each TFT (12) and is in contact with the exposed conductive electrode (125) of each TFT (12);
coating a photoresist (40) on the second transparent conductive layer (180), exposing and developing the photoresist (40) by using a photomask (50), and etching and patterning the second transparent conductive layer (180) by using the remained photoresist (40) as a mask, wherein the second transparent conductive layer (180) forms a plurality of pixel electrodes (18) after etching and patterning, each pixel electrode (18) is a patterned structure with a pixel electrode strip (181) and a first slit (182), and each pixel electrode (18) is electrically connected with one conductive electrode (125) of a corresponding TFT (12) through the contact hole (19);
after the second transparent conductive layer (180) is etched and patterned to form the plurality of pixel electrodes (18), continuing to perform a wet etching process on the third insulating layer (17) by using the remaining photoresist (40) as a mask, so that the third insulating layer (17) is etched to form a plurality of insulating layer patterns (170) spaced from each other, each insulating layer pattern (170) corresponding to one pixel electrode (18), the insulating layer patterns (170) and the pixel electrodes (18) having the same pattern and overlapping each other;
the photoresist (40) is removed.
9. The method for manufacturing the array substrate according to claim 7 or 8, wherein the second insulating layer (16) is made of silicon nitride, silicon oxide or silicon oxynitride, and the third insulating layer (17) is made of aluminum oxide or zinc oxide.
10. A display panel comprising the array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 7 to 9.
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel.
Background
Liquid Crystal Displays (LCDs) have the advantages of good picture quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and various portable electronic products almost all use liquid crystal displays as display panels and are dominant in the field of flat panel displays.
A conventional display panel generally includes a Color Filter (CF) substrate, a Thin Film Transistor (TFT) substrate, and a Liquid Crystal (LC) sandwiched between the Color Filter substrate and the TFT substrate.
A thin film transistor liquid crystal display (TFT-LCD) may be classified into a vertical electric field type and a horizontal electric field type according to the direction of an electric field for driving liquid crystals. The vertical electric field type TFT-LCD needs to form a pixel electrode on a thin film transistor array substrate and form a common electrode on a color film substrate; and the horizontal electric field type TFT-LCD requires the pixel electrode and the common electrode to be simultaneously formed on the thin film transistor array substrate. The vertical electric field type TFT-LCD includes: twisted Nematic (abbreviated as TN) type TFT-LCD; the horizontal electric field type TFT-LCD includes: fringe Field Switching (FFS) -type TFT-LCD, In-Plane Switching (IPS) -type TFT-LCD. The horizontal electric field type TFT-LCD, especially FFS type TFT-LCD, has the advantages of high light transmittance, wide viewing angle, fast response speed, low power consumption and the like, and is widely applied to the field of liquid crystal displays.
However, after wet etching of the pixel electrode of the FFS tft array substrate, a dry etching process is added to a single insulating layer between the pixel electrode and the common electrode to thin the insulating layer below the slit between the pixel electrode strips of the pixel electrode, thereby forming an insulating layer structure with a slit.
The current solution to the above problems is to optimize the process precision of the equipment, enhance the monitoring precision of the Chemical Vapor Deposition (CVD) film thickness, improve the etching uniformity, and improve the uniformity of the insulating layer film thickness. The existing process technology cannot effectively monitor the U% of the etching of the insulating layer, the process optimization difficulty is high, a new monitoring machine needs to be purchased, and the cost is increased.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method and a display panel, which can solve the problem of film thickness uniformity after an insulating layer is etched, so that the difference of driving voltages in different areas in a plane is reduced.
The invention provides an array substrate, comprising:
a substrate;
a plurality of TFTs formed on the substrate in an array arrangement;
a first insulating layer covering the plurality of TFTs;
a planarization layer covering the first insulating layer;
a common electrode formed on the planarization layer;
a second insulating layer covering the common electrode;
a third insulating layer formed on the second insulating layer;
a plurality of pixel electrodes formed on the third insulating layer and spaced apart from each other, each pixel electrode being conductively connected to a corresponding one of the TFTs through a contact hole;
each pixel electrode is a patterned structure having a pixel electrode bar and a first slit, the third insulating layer is etched to form a plurality of insulating layer patterns spaced from each other, each insulating layer pattern corresponds to one pixel electrode, the insulating layer patterns and the pixel electrodes have the same pattern and are overlapped with each other in an up-and-down manner, the second insulating layer is made of a material capable of being dry-etched, and the third insulating layer is made of a material capable of being wet-etched.
Further, the second insulating layer is made of silicon nitride, silicon oxide or silicon oxynitride, and the third insulating layer is made of aluminum oxide or zinc oxide.
Further, the film thickness of the third insulating layer is proportional to the number of pixels of the array substrate.
Furthermore, each insulating layer pattern is provided with an insulating strip and a second slit, the insulating strip and the pixel electrode strip are overlapped up and down, and the second slit is corresponding to and communicated with the first slit up and down.
Further, the second insulating layer is exposed through the first slit and the second slit.
Further, the contact hole penetrates through the third insulating layer, the second insulating layer, the planarization layer, and the first insulating layer to expose one conductive electrode corresponding to the TFT, and each pixel electrode is conductively connected to the exposed conductive electrode of the corresponding TFT through the contact hole.
A manufacturing method of an array substrate comprises the following steps: forming a plurality of TFTs arranged in an array on a substrate;
forming a first insulating layer covering the plurality of TFTs;
forming a planarization layer covering the first insulating layer and patterning the planarization layer, removing the planarization layer at a position corresponding to each contact hole to expose the first insulating layer thereunder;
depositing a first transparent conductive layer on the planarization layer, and etching and patterning the first transparent conductive layer, removing the first transparent conductive layer at a position corresponding to each TFT to expose the planarization layer therebelow, the first transparent conductive layer forming a common electrode after patterning;
forming a second insulating layer covering the common electrode, the second insulating layer also covering the exposed planarization layer and the first insulating layer at the same time;
forming a third insulating layer covering the second insulating layer, wherein the second insulating layer is made of a material that can be dry-etched, the third insulating layer is made of a material that can be wet-etched, then the third insulating layer at each contact hole position is removed by a wet etching process, and then the second insulating layer and the first insulating layer at each contact hole position are removed by a dry etching process, so as to expose one conductive electrode of each TFT at each contact hole position;
depositing a second transparent conducting layer on the third insulating layer, wherein the second transparent conducting layer is filled into the contact hole of each TFT and is in contact with the exposed conducting electrode of each TFT;
coating a photoresist on the second transparent conductive layer, exposing and developing the photoresist by using a photomask, etching and patterning the second transparent conductive layer by using the left photoresist as a mask, forming a plurality of pixel electrodes after etching and patterning the second transparent conductive layer, wherein each pixel electrode is a patterned structure with a pixel electrode strip and a first slit, and each pixel electrode is in conductive connection with one conductive electrode of the corresponding TFT through the contact hole;
after the second transparent conductive layer is etched and patterned to form a plurality of pixel electrodes, continuing to perform a wet etching process on the third insulating layer by using the remaining photoresist as a mask, so that the third insulating layer is etched to form a plurality of insulating layer patterns which are spaced from each other, wherein each insulating layer pattern corresponds to one pixel electrode, the insulating layer patterns and the pixel electrodes have the same pattern, and the insulating layer patterns and the pixel electrodes are overlapped with each other up and down;
and removing the photoresist.
A manufacturing method of an array substrate comprises the following steps: forming a plurality of TFTs arranged in an array on a substrate;
forming a first insulating layer covering the plurality of TFTs;
forming a planarization layer covering the first insulating layer and patterning the planarization layer, removing the planarization layer at a position corresponding to each contact hole to expose the first insulating layer thereunder;
depositing a first transparent conductive layer on the planarization layer, and etching and patterning the first transparent conductive layer, removing the first transparent conductive layer at a position corresponding to each TFT to expose the planarization layer therebelow, the first transparent conductive layer forming a common electrode after patterning;
forming a second insulating layer covering the common electrode, the second insulating layer also covering the exposed planarization layer and the first insulating layer at the same time;
removing the second insulating layer at the position of each contact hole by using a dry etching process to expose the first insulating layer below at the position of each contact hole;
forming a third insulating layer covering the second insulating layer, the third insulating layer also covering the exposed first insulating layer, wherein the second insulating layer is made of a material capable of being dry-etched, the third insulating layer is made of a material capable of being wet-etched, then the third insulating layer at each contact hole position is removed by a wet etching process, and then the first insulating layer at each contact hole position is removed by a dry etching process, so that one conductive electrode of each TFT is exposed at each contact hole position;
depositing a second transparent conducting layer on the third insulating layer, wherein the second transparent conducting layer is filled into the contact hole of each TFT and is in contact with the exposed conducting electrode of each TFT;
coating a photoresist on the second transparent conductive layer, exposing and developing the photoresist by using a photomask, etching and patterning the second transparent conductive layer by using the left photoresist as a mask, forming a plurality of pixel electrodes after etching and patterning the second transparent conductive layer, wherein each pixel electrode is a patterned structure with a pixel electrode strip and a first slit, and each pixel electrode is in conductive connection with one conductive electrode of the corresponding TFT through the contact hole;
after the second transparent conductive layer is etched and patterned to form the plurality of pixel electrodes, continuing to perform a wet etching process on the third insulating layer by using the remaining photoresist as a mask, so that the third insulating layer is etched to form a plurality of insulating layer patterns which are spaced from each other, wherein each insulating layer pattern corresponds to one pixel electrode, the insulating layer patterns and the pixel electrodes have the same pattern, and the insulating layer patterns and the pixel electrodes are overlapped with each other up and down;
and removing the photoresist.
Further, the second insulating layer is made of silicon nitride, silicon oxide or silicon oxynitride, and the third insulating layer is made of aluminum oxide or zinc oxide.
The invention also provides a display panel which comprises the array substrate manufactured by the manufacturing method of the array substrate.
The array substrate, the manufacturing method and the display panel provided by the invention have the advantages that the second insulating layer and the third insulating layer with different etching characteristics are arranged between the common electrode and the pixel electrode, wherein the second insulating layer is made of a material capable of being dry-etched, the third insulating layer is made of a material capable of being wet-etched, when the third insulating layer is removed by wet etching at a position corresponding to the first slit of the pixel electrode due to different etching characteristics, the second insulating layer at the lower layer cannot be damaged, the second insulating layer can be prevented from being mistakenly etched, the lower common electrode is better protected, the common electrode cannot be exposed, Short circuit (Short) risk is not easy to occur between the pixel electrode and the common electrode, the process yield is improved, in addition, the precision requirement on the etching time of the third insulating layer is not high due to the existence of the second insulating layer, the etching can be stopped after the third insulating layer is completely and fully etched, the problem that the second insulating layer is etched by mistake due to insufficient etching of the third insulating layer or over etching of the third insulating layer caused by improper control of the etching rate is solved, and the process flexibility is improved; meanwhile, the second insulating layer is arranged on the common electrode to protect the common electrode, the third insulating layer is wet-etched to form a plurality of insulating layer patterns which are spaced from each other, the thickness of the third insulating layer among the insulating layer patterns is reduced, the common electrode can be more exposed, the fringe electric field between the pixel electrode and the common electrode is greatly enhanced, the saturation voltage (Vsat) can be greatly reduced, and the purpose of saving power consumption is achieved.
Drawings
FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIGS. 2a-2k are schematic views illustrating a manufacturing process of an array substrate according to a first embodiment of the invention;
fig. 3a-3k are schematic views illustrating a manufacturing process of an array substrate according to a second embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the present invention will be made with reference to the accompanying drawings and examples.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and as shown in fig. 1, an embodiment of the present invention provides an array substrate, including: a
Each
In the present embodiment, each
The second insulating
For example, the second insulating
As will be understood by those skilled in the art, a plurality of scan lines (not shown) and a plurality of data lines (not shown) are disposed on the array substrate, a plurality of pixel units are defined by the scan lines and the data lines being insulated from each other and crossing each other, a
In the present embodiment, the film thickness of the third insulating
In this embodiment, the film thickness of the second insulating
In summary, in the array substrate provided by the present invention, two types of second insulating layers 16 and third insulating layers 17 with different etching characteristics are disposed between the common electrode 15 and the pixel electrode 18, wherein the second insulating layer 16 is made of a material capable of being dry-etched, the third insulating layer 17 is made of a material capable of being wet-etched, and when the third insulating layer 17 is removed by wet etching at a position corresponding to the first slit 182 of the pixel electrode 18, due to different etching characteristics, the second insulating layer 16 below is not damaged, so that the second insulating layer 16 is prevented from being erroneously etched, the common electrode 15 below is better protected, the common electrode 15 is not exposed, a Short (Short) risk is not easily generated between the pixel electrode 18 and the common electrode 15, and the yield of the manufacturing process is improved, and due to the existence of the second insulating layer 16, the requirement on the accuracy of the etching time of the third insulating layer 17 is not high, the etching can be stopped after the third insulating layer 17 is completely and fully etched, so that the problem of mis-etching the second insulating layer 16 due to the insufficient etching of the third insulating layer 17 or the over etching of the third insulating layer 17 caused by improper etching rate control is avoided, and the process flexibility is improved.
Meanwhile, because the second insulating
First embodiment
Fig. 2a to 2k are schematic views illustrating a manufacturing process of an array substrate according to a first embodiment of the present invention, for manufacturing the array substrate, as shown in fig. 2a to 2k, the manufacturing method includes: a plurality of
Forming a first insulating
Forming a second insulating
The second transparent
The second transparent
After the second transparent
The
Second embodiment
Fig. 3a to 3k are schematic views illustrating a manufacturing process of an array substrate according to a second embodiment of the present invention, and the implementation manner of this embodiment is basically the same as that of the first embodiment, and the same parts are not repeated herein, but the differences include:
forming a second insulating
removing the second insulating
forming a third insulating
depositing a second transparent
coating a
after the second transparent
The
The invention also provides a display panel which comprises the array substrate manufactured by the manufacturing method of the array substrate.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
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