阅读说明：本技术 半导体装置
(Semiconductor device with a plurality of semiconductor chips
) 是由 石逸群
叶顺闵 于 2019-09-04 设计创作，主要内容包括：本发明公开了一种半导体装置,半导体装置包括一基底、一第一III-V族化合物层、一栅极、多个以高积集度排列设置的漏极沟槽以及至少一漏极。基底具有一第一侧以及与第一侧相反的一第二侧。第一III-V族化合物层设置在基底的第一侧。栅极设置在第一III-V族化合物层上。各漏极沟槽自基底的第二侧朝向第一侧延伸而贯穿基底,且多个漏极沟槽规则排列设置。漏极设置在多个漏极沟槽中的至少一个中。(The invention discloses a semiconductor device, which comprises a substrate, a first III-V compound layer, a grid, a plurality of drain electrode grooves arranged in a high-integration arrangement mode and at least one drain electrode. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is disposed on a first side of the substrate. A gate is disposed on the first III-V compound layer. Each drain electrode groove extends from the second side of the substrate to the first side and penetrates through the substrate, and the drain electrode grooves are regularly arranged. A drain is disposed in at least one of the plurality of drain trenches.)
1. A semiconductor device, comprising:
a substrate having a first side and a second side opposite the first side;
a first III-V compound layer disposed on the first side of the substrate;
a gate disposed on the first III-V compound layer;
a plurality of drain trenches arranged in a high-integration manner, wherein each drain trench extends from the second side of the substrate to the first side of the substrate and penetrates through the substrate, and the plurality of drain trenches are arranged regularly; and
at least one drain electrode is arranged in at least one of the drain electrode grooves.
2. The semiconductor device of claim 1, wherein each of the drain trenches comprises a stripe trench, and the plurality of drain trenches extend in a same direction and are parallel to each other.
3. The semiconductor device of claim 1, wherein each of the drain trenches comprises a stripe trench, and the plurality of drain trenches are staggered with respect to each other.
4. The semiconductor device of claim 1, wherein the plurality of drain trenches are separated from each other, and at least a portion of the plurality of drain trenches are arranged in a hexagonal pattern.
5. The semiconductor device according to claim 1, further comprising:
a contact trench extending through the substrate from the second side of the substrate toward the first side; and
a back contact structure disposed in the contact trench, wherein the back contact structure is electrically separated from the at least one drain.
6. The semiconductor device according to claim 5, further comprising:
a contact structure disposed on the first side of the substrate, wherein the contact structure is electrically connected to the backside contact structure.
7. The semiconductor device according to claim 1, further comprising:
a buffer layer disposed between the substrate and the first III-V compound layer;
a second III-V compound layer disposed between the buffer layer and the first III-V compound layer, wherein each of the drain trenches further extends through the buffer layer and is partially disposed in the second III-V compound layer; and
a source disposed on the first side of the substrate, wherein at least a portion of the first III-V compound layer is between the source and the second III-V compound layer.
8. The semiconductor device according to claim 7, wherein the first III-V compound layer comprises a lightly N-doped GaN layer and the second III-V compound layer comprises a heavily N-doped GaN layer.
9. The semiconductor device according to claim 7, further comprising:
a third III-V compound layer disposed on the first side of the substrate, wherein at least a portion of the first III-V compound layer is between the third III-V compound layer and the second III-V compound layer.
10. The semiconductor device of claim 9, wherein the third III-V compound layer comprises a P-type doped gallium nitride layer.
11. The semiconductor device according to claim 9, wherein the third III-V compound layer has an opening provided corresponding to the gate.
12. The semiconductor device according to claim 9, further comprising:
a nitride layer disposed on the first side of the substrate, wherein at least a portion of the nitride layer is between the gate and the first III-V compound layer.
13. The semiconductor device according to claim 12, further comprising:
a trench penetrating through the third III-V compound layer and disposed corresponding to the gate;
a fourth III-V compound layer at least partially disposed in the trench, wherein the nitride layer is disposed on the fourth III-V compound layer and at least partially disposed in the trench; and
a fifth III-V compound layer disposed on the nitride layer, wherein the gate is disposed on the fifth III-V compound layer.
14. The semiconductor device according to claim 13, wherein the fourth III-V compound layer comprises a gallium nitride layer and the fifth III-V compound layer comprises a P-type doped gallium nitride layer.
15. The semiconductor device according to claim 9, further comprising:
a sixth III-V compound layer disposed on the third III-V compound layer; and
a gate trench extending through the sixth III-V compound layer and the third III-V compound layer, wherein the gate is at least partially disposed in the gate trench.
16. The semiconductor device according to claim 15, wherein the sixth III-V compound layer comprises a heavily N-doped gallium nitride layer.
17. The semiconductor device according to claim 1, further comprising:
a gate trench disposed in the first III-V compound layer, wherein the gate is disposed in the gate trench.
18. The semiconductor device of claim 1, further comprising an insulating layer at least partially disposed in the plurality of drain trenches, wherein each of the drain trenches is filled with the insulating layer and the at least one drain.
19. The semiconductor device of claim 1, wherein each of said drain trenches is filled with said at least one drain.
20. The semiconductor device according to any one of claims 7 to 16, further comprising:
a source disposed on the first side of the substrate, wherein at least a portion of the first III-V compound layer is between the source and the second III-V compound layer, wherein the gate and the source are disposed within a transistor unit area, and at least two of the plurality of drain trenches are disposed within the transistor unit area.
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a drain trench.
Background
The III-V compounds are useful for forming many kinds of integrated circuit devices, such as high power field effect transistors, high frequency transistors, or High Electron Mobility Transistors (HEMTs), because of their semiconductor characteristics. In recent years, gallium nitride (GaN) series materials are suitable for high power and high frequency products because of their wide energy gap and high saturation rate. The gan-based semiconductor device can increase the switching speed because the piezoelectric effect of the material itself generates a two-dimensional electron gas (2DEG) having a high electron velocity and density. However, as performance requirements of related semiconductor devices become higher, design changes in structure and/or manufacturing processes are required to increase the density of transistors and/or to improve the electrical performance of semiconductor devices to meet product requirements.
Disclosure of Invention
The invention provides a semiconductor device, which utilizes a drain electrode groove arranged on the back side of a substrate and a drain electrode positioned in the drain electrode groove to achieve the effect of improving the density of transistors. In addition, the drain electrode grooves can be regularly arranged, so that the uniformity of the manufacturing process of each drain electrode groove is improved, and the effects of improving the qualified rate of the manufacturing process and/or improving the overall electrical performance are achieved.
According to an embodiment of the present invention, a semiconductor device includes a substrate, a first III-V compound layer, a gate, a plurality of drain trenches arranged in a highly integrated arrangement, and at least one drain. The substrate has a first side and a second side opposite to the first side. A first III-V compound layer is disposed on a first side of the substrate. A gate is disposed on the first III-V compound layer. Each drain electrode groove extends from the second side of the substrate to the first side and penetrates through the substrate, and the drain electrode grooves are regularly arranged. A drain is disposed in at least one of the plurality of drain trenches.
Drawings
Fig. 1 is a schematic view of a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a schematic view illustrating an arrangement of drain trenches in a semiconductor device according to an embodiment of the invention.
Fig. 3 is a schematic view illustrating an arrangement of drain trenches in a semiconductor device according to another embodiment of the present invention.
Fig. 4 is a schematic view illustrating an arrangement of drain trenches in a semiconductor device according to still another embodiment of the present invention.
Fig. 5 is a schematic view of a semiconductor device according to a second embodiment of the present invention.
Fig. 6 is a schematic view of a semiconductor device according to a third embodiment of the present invention.
Fig. 7 is a schematic view of a semiconductor device according to a fourth embodiment of the present invention.
Fig. 8 is a schematic view of a semiconductor device according to a fifth embodiment of the present invention.
Fig. 9 is a schematic view of a semiconductor device according to a sixth embodiment of the present invention.
Fig. 10 is a schematic view of a semiconductor device according to a seventh embodiment of the present invention.
Fig. 11 is a schematic view of a semiconductor device according to an eighth embodiment of the present invention.
Fig. 12 is a schematic view of a semiconductor device according to a ninth embodiment of the present invention.
Wherein the reference numerals are as follows:
10 base
10A first side
10B second side
12 buffer layer
14 second III-V compound layer
16 first III-V compound layer
16A third side
Fourth side of 16B
18 third III-V compound layer
18V opening
20 nitride layer
22 gate dielectric layer
24 isolation structure
30 first conductive layer
31 second conductive layer
32 insulating layer
40 seventh III-V compound layer
42 fourth III-V compound layer
44 fifth III-V compound layer
50 sixth III-V compound layer
101-109 semiconductor device
CS1 contact structure
CS2 back contact structure
D1 first direction
D2 second direction
DE drain electrode
GE grid
First part of P1
Second part of P2
Part three of P3
SE source
TA transistor unit area
TR1 drain trench
TR2 contact trench
TR3 groove
TR4 gate trench.
Detailed Description
The following detailed description of the invention has disclosed sufficient detail to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered as illustrative and not restrictive. It will be apparent to persons skilled in the relevant art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.
The meaning of the terms "on …", "above …", and/or "above …", etc., as used herein, should be read in the broadest manner such that "on …" means not only "directly on" something but also includes the meaning of being on something with other intervening features or layers therebetween, and "above …" or "above …" means not only "above" or "over" something, but may also include its meaning of being "above" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms such as "below …," "below …," "below …," "above …," "above …," "above …," and the like may be used herein to describe one component or feature's relationship to another component or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terms "forming" or "disposing" are used herein to describe the act of applying a layer of material to a substrate. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.
References herein to "one embodiment," "an embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Please refer to fig. 1. Fig. 1 is a schematic view of a semiconductor device according to a first embodiment of the present invention. As shown in fig. 1, the present embodiment provides a semiconductor device 101. The semiconductor device 101 includes a substrate 10, a first III-V compound layer 16, a gate electrode GE, at least one drain trench TR1, and at least one drain electrode DE. The substrate 10 has a first side 10A and a second side 10B, and the first side 10A and the second side 10B can be regarded as two sides of the substrate 10 opposite and/or opposite to each other in the thickness direction (e.g., the first direction D1 shown in fig. 1), but not limited thereto. The first III-V compound layer 16 may be disposed on the first side 10A of the substrate 10, and the gate electrode GE may be disposed on the first III-V compound layer 16. Each drain trench TR1 may extend from the second side 10B of the substrate 10 toward the first side 10A to penetrate the substrate 10, and the drain DE may be disposed in the drain trench TR 1.
Please refer to fig. 1, fig. 2, fig. 3 and fig. 4. Fig. 2 is a schematic diagram illustrating an arrangement of drain trenches TR1 in a semiconductor device according to an embodiment of the present invention, fig. 3 is a schematic diagram illustrating an arrangement of drain trenches TR1 in a semiconductor device according to another embodiment of the present invention, and fig. 4 is a schematic diagram illustrating an arrangement of drain trenches TR1 in a semiconductor device according to yet another embodiment of the present invention. As shown in fig. 1 and 2, in some embodiments, the semiconductor device 101 may include a plurality of drain trenches TR1 arranged in a high integration arrangement and a plurality of drain trenches TR1 arranged in a regular arrangement, and the drain DE may be disposed in at least one of the plurality of drain trenches TR 1. For example, in some embodiments, each of the drain trenches TR1 may include a stripe trench, and a plurality of the drain trenches TR1 may extend in the same direction and parallel to each other (as in the case shown in fig. 2). Further, a plurality of drains DE may be respectively disposed in the corresponding drain trenches TR1, or one drain DE may be disposed in the plurality of drain trenches TR 1. In other words, the drains DE disposed in the different drain trenches TR1 may be connected to each other or separated from each other. In addition, in some embodiments, the semiconductor device 101 may also include a plurality of gates GE, and each gate GE may be disposed corresponding to one drain DE, but not limited thereto. It should be noted that, by designing the drain trenches TR1 in a regular arrangement, the uniformity of the manufacturing process for forming the drain trenches TR1 (e.g., the uniformity of the depth of the drain trenches TR 1) can be improved, and the electrical uniformity among the plurality of semiconductor devices (e.g., transistors) corresponding to the drain electrode DE formed in the drain trenches TR1 can be improved. In addition, in some embodiments, as shown in fig. 1 and fig. 3, each of the drain trenches TR1 may include a stripe trench, and a plurality of the drain trenches TR1 may be staggered and connected to each other. In some embodiments, as shown in fig. 1 and 4, the plurality of drain trenches TR1 may be separated from each other, and at least a portion of the drain trenches TR1 may be arranged in a hexagonal manner, such as, but not limited to, the centers of six drain trenches TR1 in fig. 4 being connected to form a hexagonal shape. It should be noted that the arrangement of the drain trenches TR1 according to the present invention is not limited to the situation shown in fig. 2 to 4, but may be arranged in other types as needed.
To further illustrate, as shown in fig. 1, in some embodiments, the semiconductor device 101 may further include a buffer layer 12, a second III-V compound layer 14, a nitride layer 20, a gate dielectric layer 22, and a source SE. The buffer layer 12 may be disposed between the substrate 10 and the first III-V compound layer 16, and the second III-V compound layer 14 may be disposed between the buffer layer 12 and the first III-V compound layer 16. A nitride layer 20 may be disposed on the first side 10A of the substrate 10, and at least a portion of the nitride layer 20 may be located between the gate GE and the first III-V compound layer 16. The source SE may be disposed on the first side 10A of the substrate 10, and at least a portion of the first III-V compound layer 16 may be located between the source SE and the second III-V compound layer 14. In some embodiments, the buffer layer 12, the second III-V compound layer 14, the first III-V compound layer 16, and the nitride layer 20 may be sequentially stacked on the substrate 10 in the first direction D1, and the drain trench TR1 may further penetrate the buffer layer 12 and be partially disposed in the second III-V compound layer 14. In addition, the source SE may be partially disposed in the first III-V compound layer 16 through the nitride layer 20, and the source SE may be located at both sides of and/or around the gate GE in a horizontal direction (e.g., the second direction D2 shown in fig. 1), but not limited thereto. In some embodiments, the gate electrode GE and the source electrode SE may be disposed within a transistor unit area TA, and the at least one drain trench TR1 may be disposed within the transistor unit area TA. The transistor unit area TA may be an area where a single transistor is located, but is not limited thereto. In other words, a single transistor may correspond to one or more drain trenches TR1, and the drain trenches TR1 arranged in a highly integrated arrangement may reduce the influence on the electrical performance of the transistor when manufacturing process problems occur in the single drain trench TR 1.
In some embodiments, the substrate 10 may comprise a silicon substrate, a silicon carbide (SiC) substrate, a sapphire (sapphire) substrate, or other suitable substrate, and the buffer layer 12 may comprise a buffer material for assisting in epitaxially forming a III-V compound layer on the substrate 10, such that the material of the buffer layer 12 may comprise, for example, gallium nitride (gan), aluminum gallium nitride (aigan), or other suitable buffer material. In addition, the first and second III-V compound layers 16, 14 may include gallium nitride (GaN), indium gallium nitride (InGaN), and/or other suitable III-V compound semiconductor materials. In some embodiments, the III-V compound semiconductor layer 14 may include a single layer or multiple layers of the III-V compound materials described above. In some embodiments, the first III-V compound layer 16 and the second III-V compound layer 14 may be the same III-V compound material but have different doping concentrations. For example, the first III-V compound layer 16 may include a lightly doped N (light doped) GaN layer, and the second III-V compound layer 14 may include a heavily doped N (heavy doped) GaN layer, but is not limited thereto. The N-type dopant may include silicon, germanium, or other suitable dopants. The nitride layer 20 may be used as a barrier layer (barrier layer) or a cap layer in a semiconductor device, the nitride layer 20 may be formed using aluminum gallium nitride (alginn), aluminum indium nitride (AlInN) and/or aluminum nitride (AlN) as the barrier layer, and the nitride layer 20 may be formed using aluminum gallium nitride (algain), aluminum nitride (AlN), gallium nitride and/or silicon nitride as the cap layer, but the invention is not limited thereto. In addition, the nitride layer 20 may also include a single layer or multiple layers of a group III nitride material.
In some embodiments, the gate dielectric layer 22 may comprise a single layer or multiple layers of a dielectric material such as silicon nitride (e.g., Si)3N4) Silicon oxide (e.g. SiO)2) Alumina (e.g., Al)2O3) Hafnium oxide (e.g., HfO)2) Lanthanum oxide (e.g., La)2O3) Lutetium oxide (e.g., Lu)2O3) Lanthanum lutetium oxide (e.g., LaLuO)3) Or other suitable dielectric material, but not limited thereto. In addition, the gate electrode GE, the source electrode SE, and the drain electrode DE may respectively include a metal conductive material or other suitable conductive materials. The metal conductive material may include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), and titanium (Ti)(Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers or alloys of the above materials, but not limited thereto. For example, the drain electrode DE may be formed using the first conductive layer 30 partially formed in the drain trench TR1 and partially formed outside the drain trench TR1, and the first conductive layer 30 may include a single layer or multiple layers of the above-described conductive materials. Since the source SE and the gate GE of the semiconductor device 101 may be disposed on the front side of the first III-V compound layer 16 (e.g., the third side 16A shown in fig. 1) and the drain DE may be disposed on the back side of the first III-V compound layer 16 (e.g., the fourth side 16B shown in fig. 1), the semiconductor device 101 may be regarded as a vertical transistor structure, such as a vertical gallium nitride High Electron Mobility Transistor (HEMT), but is not limited thereto. Through the design of the vertical transistor structure, the occupied area of each transistor can be reduced, and the effect of improving the transistor density is further achieved. In addition, by designing the drain trench TR1, an epitaxial process may be performed on a relatively low-cost substrate 10 (e.g., a silicon substrate) to form a III-V compound layer instead of directly using a relatively high-cost III-V compound substrate (e.g., a gan substrate), which may help to reduce the production cost and improve the product competitiveness.
In some embodiments, the semiconductor device 101 may further include a third III-V compound layer 18 disposed on the first side 10A of the substrate 10, and at least a portion of the first III-V compound layer 16 may be located between the third III-V compound layer 18 and the second III-V compound layer 14. For example, the third III-V compound layer 18 may be disposed in the first III-V compound layer 16, and the third III-V compound layer 18 may have an opening 18V disposed corresponding to the gate GE in the first direction D1. In this case, the first portion P1 of the first III-V compound layer 16 may be located between the third III-V compound layer 18 and the second III-V compound layer 14, the second portion P2 of the first III-V compound layer 16 may be located in the opening 18V, and the third portion P3 of the first III-V compound layer 16 may be located between the nitride layer 20 and the third III-V compound layer 18. In some embodiments, the third III-V compound layer 18 and the second III-V compound layer 14 may be the same III-V compound material but have different types of doping. For example, the second III-V compound layer 14 may include a heavily N-doped gallium nitride layer, the third III-V compound layer 18 may include a lightly P-doped gallium nitride layer, the first portion P1 of the first III-V compound layer 16 may include an N-doped gallium nitride layer, the second portion P2 of the first III-V compound layer 16 may include an N-doped gallium nitride layer, and the third portion P3 of the first III-V compound layer 16 may include an unintentionally doped (UID) gallium nitride layer, but is not limited thereto. The P-type dopant may include magnesium or other suitable dopants. In some embodiments, the third III-V compound layer 18 may also have a different III-V compound material than the second III-V compound layer 14. In addition, the third III-V compound layer 18 may be regarded as a Current Blocking Layer (CBL), the first portion P1 of the first III-V compound layer 16 may be regarded as a drift region (drift region), the two-dimensional electron gas (2DEG) may be defined in the third portion P3 of the first III-V compound layer 16 and located near one side of the nitride layer 20 (e.g., a dotted line position in fig. 1), and the semiconductor device 101 may be regarded as a current-aperture vertical electron transistor (CAVET), but not limited thereto.
It should be noted that the structure of the semiconductor device of the present invention is not limited to the situation shown in fig. 1, and the drain trench TR1 and the drain DE penetrating through the substrate 10 from the back side (e.g., the second side 10B) of the substrate 10 of the present invention may also be matched with other types of semiconductor structures having the first III-V compound layer 16 on the front side (e.g., the first side 10A) of the substrate 10 as required.
The following description will mainly describe different parts of each embodiment, and in order to simplify the description, the description will not repeat the description of the same parts. In addition, the same components in the embodiments of the present invention are denoted by the same reference numerals to facilitate comparison between the embodiments.
Please refer to fig. 5. Fig. 5 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the invention. As shown in fig. 5, the semiconductor device 102 of the present embodiment may further include a contact structure CS1, a contact trench TR2, and a back contact structure CS 2. The contact trench TR2 may extend through the substrate 10 from the second side 10B toward the first side 10A of the substrate 10, and the contact trench TR2 and the drain trench TR1 are separated from each other. The back contact structure CS2 may be disposed in the contact trench TR2, and the back contact structure CS2 is electrically separated from the drain DE. In addition, a contact structure CS1 may be disposed on the first side 10A of the substrate 10, and the contact structure CS1 is electrically connected with the backside contact structure CS 2. In some embodiments, the contact structure CS1 may be partially disposed in the second III-V compound layer 14 through the nitride layer 20 and the first III-V compound layer 16 in the first direction D1, thereby forming an electrical connection in contact with the backside contact structure CS2 partially disposed in the second III-V compound layer 14 through the substrate 10 and the buffer layer 12, but is not limited thereto. Contact structure CS1 and backside contact structure CS2 may each comprise a metallic conductive material or other suitable conductive material. The metal conductive material may include gold, tungsten, cobalt, nickel, titanium, molybdenum, copper, aluminum, tantalum, palladium, platinum, compounds, composite layers or alloys thereof, but is not limited thereto. In some embodiments, the contact structure CS1 may be electrically connected to the source SE or the gate GE through another conductive structure (not shown) located on the first side 10A of the substrate 10, or the contact structure CS1 and the source SE may be formed together or the contact structure CS1 and the gate GE may be formed together by the same manufacturing process, so that the source SE and/or the gate GE may be electrically connected to the back contact structure CS2 through the contact structure CS1, but not limited thereto. In some embodiments, the semiconductor device may include a plurality of contact structures CS1 and corresponding backside contact structures CS2, such that wire bonding (wire bonding) processes may be performed on the second side 10B of the substrate 10 to electrically connect the drain electrode DE, the source electrode SE and the gate electrode GE, respectively, thereby achieving the effects of simplifying related wiring layout design and/or simplifying related processes.
Please refer to fig. 6. Fig. 6 is a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. As shown in fig. 6, the difference from the second embodiment is that in the semiconductor device 103, the III-V compound stack between the drain electrode DE and the gate electrode GE and between the drain electrode DE and the source electrode SE may form a mesa (mesa) structure, and the semiconductor device 103 may further include an isolation structure 24 between the mesa structures for achieving the effect of isolating the adjacent mesa structures. Isolation structure 24 may comprise a single layer or multiple layers of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating material. In some embodiments, the contact trench TR2 may be partially disposed in the isolation structure 24 through the substrate 10 and the buffer layer 12, and the contact structure CS1 may be partially disposed in the isolation structure 24, thereby making contact with the backside contact structure CS2 to form an electrical connection, but not limited thereto.
Please refer to fig. 7. Fig. 7 is a diagram illustrating a semiconductor device 104 according to a fourth embodiment of the present invention. As shown in fig. 7, the semiconductor device 104 may further include a trench TR3, a fourth III-V compound layer 42, and a fifth III-V compound layer 44, which is different from the first embodiment described above. The trench TR3 may be partially located in the first III-V compound layer 16 through the third III-V compound layer 18, and the trench TR3 may be disposed corresponding to the gate GE in the first direction D1. The fourth III-V compound layer 42 may be at least partially disposed in the trench TR3, and the nitride layer 20 may be disposed on the fourth III-V compound layer 42 and at least partially disposed in the trench TR 3. The fifth III-V compound layer 44 may be disposed on the nitride layer 20, and the gate electrode GE may be disposed on the fifth III-V compound layer 44. In some embodiments, the fourth III-V compound layer 42 and the second III-V compound layer 14 may be the same III-V compound material but have different doping concentrations, and the fifth III-V compound layer 44 and the second III-V compound layer 14 may be the same III-V compound material but have different types of doping. For example, the second III-V compound layer 14 may include an N-type heavily doped gallium nitride layer, the fourth III-V compound layer 42 may include a gallium nitride layer, such as a UID gallium nitride layer, and the fifth III-V compound layer 44 may include a P-type doped gallium nitride layer, but is not limited thereto. In some embodiments, the fourth III-V compound layer 42 and/or the fifth III-V compound layer 44 can also optionally have a different III-V compound material than the second III-V compound layer 14.
Furthermore, in some embodiments, the semiconductor device 104 may further include a seventh III-V compound layer 40 disposed between the fourth III-V compound layer 42 and the third III-V compound layer 18, and the trench TR3 may further extend through the seventh III-V compound layer 40. The seventh III-V compound layer 40 may include a semi-insulating III-V compound material such as carbon-doped gallium nitride, iron-doped gallium nitride, manganese-doped gallium nitride, or other suitable III-V compound material. In addition, the source electrode SE may be disposed on side surfaces of the third III-V compound layer 18, the seventh III-V compound layer 40, side surfaces of the fourth III-V compound layer 42, and side surfaces and an upper surface of the nitride layer 20, but not limited thereto. The third III-V compound layer 18 of the present embodiment can be regarded as a current blocking layer, the first III-V compound layer 16 can be regarded as a drift region, and the two-dimensional electron gas (2DEG) can be confined in the fourth III-V compound layer 42 and located near one side of the nitride layer 20 (e.g., the dashed line position in fig. 7), while the semiconductor device 104 can be regarded as a Trench type current aperture vertical electron transistor (Trench), but not limited thereto.
Please refer to fig. 8. Fig. 8 is a schematic diagram of a semiconductor device 105 according to a fifth embodiment of the present invention. As shown in fig. 8, the semiconductor device 105 may further include a gate trench TR4 and a sixth III-V compound layer 50, which is different from the first embodiment described above. The sixth III-V compound layer 50 may be disposed on the third III-V compound layer 18, and the gate trench TR4 may be partially located in the first III-V compound layer 16 through the sixth III-V compound layer 50 and the third III-V compound layer 18 in the first direction D1, and the gate GE and the gate dielectric layer 22 may be at least partially disposed in the gate trench TR 4. In some embodiments, the material of the sixth III-V compound layer 50 may be similar to the second III-V compound layer 14, for example, the sixth III-V compound layer 50 may include an N-type heavily doped gallium nitride layer, but is not limited thereto. In some embodiments, the sixth III-V compound layer 50 can also optionally have a different III-V compound material than the second III-V compound layer 14, such as other heavily N-doped III-V compound materials. In addition, the source electrode SE may penetrate the sixth III-V compound layer 50 to contact the third III-V compound layer 18 in the first direction D1, but is not limited thereto.
Please refer to fig. 9. Fig. 9 is a schematic diagram of a semiconductor device 106 according to a sixth embodiment of the invention. As shown in fig. 9, a difference from the fifth embodiment is that the gate trench TR4 in the semiconductor device 106 may be located in the first III-V compound layer 16, and the upper surface of the gate GE may be lower than the uppermost surface (top surface) of the first III-V compound layer 16 in the first direction D1, and the portion of the first III-V compound layer 16 extending upward in the first direction D1 may be regarded as a fin structure (fin structure), but not limited thereto. In addition, the sixth III-V compound layer 50 of the present embodiment may be disposed on the fin structure of the first III-V compound layer 16, the source SE may be disposed on the sixth III-V compound layer 50, and the semiconductor device 106 may be regarded as a fin transistor structure, but not limited thereto.
Please refer to fig. 10. Fig. 10 is a schematic diagram of a semiconductor device 107 according to a seventh embodiment of the present invention. As shown in fig. 10, the semiconductor device 107 may further include an insulating layer 32 at least partially disposed in the drain trench TR1, and the insulating layer 32 may cover the drain DE for forming a protective effect on the drain DE, unlike the first embodiment described above. The insulating layer 32 may include an inorganic insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride), an organic insulating material (e.g., acryl resin), or other suitable insulating material. In addition, in some embodiments, the drain trench TR1 may be filled with the insulating layer 32 and the drain DE, but not limited thereto. It should be noted that when the semiconductor device 107 has a plurality of drain trenches TR1 (such as shown in fig. 2 to 4), the insulating layer 32 may be at least partially disposed in the plurality of drain trenches TR1, and each drain trench TR1 may be filled with the insulating layer 32 and the drain DE, but not limited thereto. In addition, the insulating layer 32 of the present embodiment can also be applied to other embodiments of the present disclosure as needed. For example, when the insulating layer 32 of the present embodiment is applied to the second embodiment shown in fig. 5, the insulating layer 32 may also be partially disposed in the contact trench TR2 to cover the backside contact structure CS2, thereby forming a protection effect, but not limited thereto.
Please refer to fig. 11. Fig. 11 is a schematic diagram of a semiconductor device 108 according to an eighth embodiment of the present invention. As shown in fig. 11, the difference from the first embodiment is that the drain electrode DE in the semiconductor device 108 may include a first conductive layer 30 and a second conductive layer 31. The first conductive layer 30 may be conformally (conformally) formed in the drain trench TR1 and on the substrate 10, and the second conductive layer 31 may cover the first conductive layer 30, and the material of the second conductive layer 31 may be different from that of the first conductive layer 30. For example, the first conductive layer 30 may comprise titanium nitride, tantalum nitride or other conductive materials with good barrier effect, and the second conductive layer 31 may comprise conductive materials with relatively low resistivity, such as copper, aluminum, tungsten, etc., but not limited thereto. In some embodiments, the drain trench TR1 may be filled with the drain DE, and when the semiconductor device 108 has a plurality of drain trenches TR1 (such as those shown in fig. 2-4), each drain trench TR1 may be filled with the drain DE, but not limited thereto. In some embodiments, an insulating layer may also be formed on the second conductive layer 31 as needed, and the drain electrode DE is covered by the insulating layer to form a protection effect. In addition, the first conductive layer 30 and the second conductive layer 31 of the present embodiment can also be applied to other embodiments of the present disclosure as needed.
Please refer to fig. 12. Fig. 12 is a schematic view of a semiconductor device 109 according to a ninth embodiment of the present invention. As shown in fig. 12, a point different from the above-described first embodiment is that, in the semiconductor device 109, a plurality of drain trenches TR1 may be provided within one transistor unit area TA, and the drain DE may be provided in a plurality of drain trenches TR1 within the transistor unit area TA. It should be noted that the manner of disposing the plurality of drain trenches TR1 in one transistor unit area TA of the present embodiment may also be applied to other embodiments of the present invention as needed.
In summary, in the semiconductor device of the present invention, the drain trench and the drain electrode located in the drain trench may be disposed from the back side of the substrate, thereby forming a vertical transistor structure to achieve the effect of increasing the transistor density. The drain electrode grooves can be regularly arranged, so that the uniformity of the manufacturing process of each drain electrode groove is improved, and the effects of improving the qualified rate of the manufacturing process and/or improving the overall electrical performance are achieved. In addition, through the design of the drain electrode groove, the III-V group compound layer can be formed by utilizing the substrate with relatively low cost to carry out an epitaxial process instead of directly using the III-V group compound substrate with relatively high cost, so that the production cost is reduced, and the product competitiveness is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
