阅读说明：本技术 一种用于剔除无效事例的反符合电路及方法 (Anti-coincidence circuit and method for eliminating invalid cases ) 是由 杨海波 千奕 赵红赟 孔洁 苏弘 唐述文 余玉洪 方芳 张永杰 孙志宇 于 2019-09-30 设计创作，主要内容包括：本发明涉及一种用于剔除无效事例的反符合电路及方法,其特征在于,包括IV转换电路、信号求和电路、数字模拟转换器、滞回比较器、微分电路、整形电路和FPGA电路；若干IV转换电路用于将外部输入的一路电荷脉冲信号转换为相应幅度的电压脉冲信号；信号求和电路用于得到一路电压信号；数字模拟转换器用于产生阈值信号；所述比较电路用于对信号求和电路发送的电压信号进行滞回比较得到一路脉冲信号；微分电路用于将该脉冲信号微分转换为尖脉冲波信号；整形电路用于将该尖脉冲波信号整形为固定脉宽的数字脉冲信号；FPGA电路用于确定该数字脉冲信号是否为有效触发信号,并剔除无效的数字脉冲信号,完成无效事例的剔除,本发明可广泛用于空间粒子探测领域中。(The invention relates to an anti-coincidence circuit and a method for eliminating invalid cases, which are characterized by comprising an IV (input/output) conversion circuit, a signal summation circuit, a digital-to-analog converter, a hysteresis comparator, a differential circuit, a shaping circuit and an FPGA (field programmable gate array) circuit; the IV conversion circuits are used for converting one path of externally input charge pulse signals into voltage pulse signals with corresponding amplitudes; the signal summation circuit is used for obtaining a voltage signal; the digital-to-analog converter is used for generating a threshold signal; the comparison circuit is used for carrying out hysteresis comparison on the voltage signal sent by the signal summation circuit to obtain a path of pulse signal; the differentiating circuit is used for differentiating and converting the pulse signal into a sharp pulse wave signal; the shaping circuit is used for shaping the sharp pulse wave signal into a digital pulse signal with fixed pulse width; the FPGA circuit is used for determining whether the digital pulse signal is an effective trigger signal or not, rejecting invalid digital pulse signals and rejecting invalid cases.)

1. An anti-coincidence circuit for eliminating invalid cases is characterized by comprising an IV conversion circuit, a signal summation circuit, a digital-analog converter, a hysteresis comparator, a differential circuit, a shaping circuit and an FPGA circuit;

the IV conversion circuits are used for converting one path of externally input charge pulse signals into voltage pulse signals with corresponding amplitudes;

the signal summation circuit is used for carrying out summation operation on the multi-path voltage pulse signals to obtain a path of voltage signals;

the digital-to-analog converter is used for generating a threshold signal under the control of the FPGA circuit;

the hysteresis comparator is used for carrying out hysteresis comparison on the voltage signal sent by the signal summation circuit according to the threshold signal sent by the digital-to-analog converter to obtain a path of pulse signal;

the differentiating circuit is used for differentiating and converting the pulse signal into a sharp pulse wave signal;

the shaping circuit is used for shaping the sharp pulse wave signal into a digital pulse signal with fixed pulse width;

the FPGA circuit is used for determining whether the digital pulse signal is an effective trigger signal or not, rejecting invalid digital pulse signals and finishing rejection of invalid cases.

2. The anti-coincidence circuit for eliminating invalid cases as claimed in claim 1, wherein the FPGA circuit determines whether the digital pulse signal is a valid trigger signal and adopts a trigger coincidence operation, the specific process is as follows:

finishing trigger coincidence operation in the FPGA circuit, determining whether the digital pulse signal is an effective trigger signal, if the operation result is high level 1, the anti-coincidence trigger is effective, and if the operation result is the effective anti-coincidence trigger signal, discarding the digital pulse signal causing the trigger to eliminate invalid cases; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

3. An anti-coincidence circuit for rejecting null cases as claimed in any one of claims 1 to 2 wherein said signal summing circuit employs an operational amplifier with a power consumption of less than 30mW and a noise of less than-69 dB.

4. An anti-coincidence circuit for rejecting invalid cases as claimed in any one of claims 1 to 2 wherein the comparator within said hysteretic comparator employs a low-delay comparator of less than 10 ns.

5. The anti-coincidence circuit for eliminating invalid cases as claimed in any one of claims 1 to 2, wherein a plurality of the IV conversion circuits receive a path of charge pulse signal sent by a corresponding plastic flash detector through a corresponding photomultiplier tube or silicon photomultiplier tube.

6. An anti-coincidence method for eliminating invalid cases is characterized by comprising the following steps:

1) each IV conversion circuit receives a path of externally input charge pulse signal, converts the charge pulse signal into a voltage pulse signal with corresponding amplitude and sends the voltage pulse signal to the signal summation circuit;

2) the signal summation circuit is used for carrying out summation operation on the multi-path voltage pulse signals and outputting one path of voltage pulse signals to the hysteresis comparator;

3) the positive input end of the hysteresis comparator receives the voltage pulse signal, the negative input end of the hysteresis comparator receives a threshold signal sent by the digital-to-analog converter, and after comparison, a pulse signal with a tail stray signal filtered is output and sent to the differential circuit;

4) the differentiating circuit differentiates the pulse signal into a sharp pulse wave signal and sends the sharp pulse wave signal to the shaping circuit;

5) the shaping circuit shapes the sharp pulse wave signal into a digital pulse signal with fixed pulse width which can be received by the FPGA circuit and sends the digital pulse signal to the FPGA circuit;

6) the digital pulse signal sent by the shaping circuit is used as an anti-coincidence trigger signal, triggering coincidence operation is completed in the FPGA circuit, whether the digital pulse signal is an effective trigger signal or not is determined, invalid digital pulse signals are removed, and invalid cases are removed;

7) the FPGA circuit sends a command with fixed time sequence to the digital-analog converter according to a digital-analog converter receipt manual, so that the digital-analog converter generates a threshold signal and sends the threshold signal to the hysteresis comparator.

7. The anti-coincidence method for eliminating invalid cases as claimed in claim 6, wherein the specific process of step 6) is:

the digital pulse signal sent by the shaping circuit is used as an anti-coincidence trigger signal, trigger coincidence operation is completed in the FPGA circuit, whether the digital pulse signal is an effective trigger signal or not is determined, if the operation result is high level 1, the anti-coincidence trigger is effective, the digital pulse signal causing the trigger is abandoned as the effective anti-coincidence trigger signal, and invalid cases are removed; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

Technical Field

The invention relates to an anti-coincidence circuit and an anti-coincidence method, in particular to an anti-coincidence circuit and an anti-coincidence method for eliminating invalid cases, and belongs to the field of space particle detection.

Background

The space particle detection in China has the following development trend: special satellite detection is developed, particle detection is carried out by using a special satellite, more detecting instruments can be carried, more physical targets are realized, and the orbit height and the satellite attitude are completely controlled by the particle detection purpose; from census to fine measurement, the research of more accurate physical analysis and spatial physical mechanisms now relies on fine measurement of various physical quantities, such as energy spectra and isotopes, which are nowadays increasingly fine; the detection instrument is simple to complex, and common to intelligent, the particle detection instrument is often designed to be more complex for achieving more purposes, one instrument can not only carry out energy spectrum measurement of different energy sections, but also can carry out element identification; anti-coincidence detectors are used to eliminate the effects of charged particles outside the field of view.

The anti-coincidence method is to use an anti-coincidence circuit to eliminate pulse signals meeting coincidence events in a time width. In the anti-coincidence circuit, a channel of a pulse signal of the main detector is called an analysis channel, a channel of the pulse signal of the anti-coincidence detector is called an anti-coincidence channel, and the pulse signal of the anti-coincidence detector passes through the timing circuit and then serves as a gating signal to be used for eliminating the pulse signal meeting the anti-coincidence condition. In an anti-cosmic ray gamma spectrometer, in order to improve anti-coincidence efficiency, anti-coincidence detectors surround the periphery and the bottom of a main detector and are used for eliminating charged particles entering the detector outside a field of view and high-energy charged particles penetrating the field of view, and the design of the anti-cosmic ray gamma spectrometer meets the following technical requirements: shielding most of particle cases outside the field of view, namely eliminating the influence of charged particle cases outside the field of view by utilizing an anti-coincidence mode; particle instances within the shielded field of view that exceed the upper limit of the measured energy are identified by the anticoincidence such that the signal of the charged particles as they reach the main detector is not recorded.

According to the research situation of documents, when the plastic scintillator is arranged around the main detector as the anti-coincidence detector, the integral background counting rate of the detection device at the position of 30 keV-2700 keV of the energy interval can be reduced by five to six times, and in the energy interval with higher energy (more than 10 MeV), the anti-coincidence shielding measures can reduce the background counting of 99 percent of the contribution of the cosmic rays.

However, the conventional anti-coincidence circuit is basically a purchased commercial anti-coincidence circuit plug-in, the number of the anti-coincidence circuit plug-ins is small, the purchased commercial anti-coincidence plug-ins have the problems of high power consumption and high cost on one hand, and on the other hand, due to strong radiation in the universe, the commercial anti-coincidence plug-ins are often subjected to a single event effect and have weak radiation resistance, so that the anti-coincidence circuit plug-ins cannot be used in the universe.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide an anti-coincidence circuit and method for eliminating invalid cases with low power consumption, low cost and strong radiation resistance.

In order to achieve the purpose, the invention adopts the following technical scheme: an anti-coincidence circuit for eliminating invalid cases is characterized by comprising an IV conversion circuit, a signal summation circuit, a digital-analog converter, a hysteresis comparator, a differential circuit, a shaping circuit and an FPGA circuit; the IV conversion circuits are used for converting one path of externally input charge pulse signals into voltage pulse signals with corresponding amplitudes; the signal summation circuit is used for carrying out summation operation on the multi-path voltage pulse signals to obtain a path of voltage signals; the digital-to-analog converter is used for generating a threshold signal under the control of the FPGA circuit; the hysteresis comparator is used for carrying out hysteresis comparison on the voltage signal sent by the signal summation circuit according to the threshold signal sent by the digital-to-analog converter to obtain a path of pulse signal; the differentiating circuit is used for differentiating and converting the pulse signal into a sharp pulse wave signal; the shaping circuit is used for shaping the sharp pulse wave signal into a digital pulse signal with fixed pulse width; the FPGA circuit is used for determining whether the digital pulse signal is an effective trigger signal or not, rejecting invalid digital pulse signals and finishing rejection of invalid cases.

Further, the FPGA circuit determines whether the digital pulse signal is an effective trigger signal and adopts a trigger coincidence operation, and the specific process is as follows: finishing trigger coincidence operation in the FPGA circuit, determining whether the digital pulse signal is an effective trigger signal, if the operation result is high level 1, the anti-coincidence trigger is effective, and if the operation result is the effective anti-coincidence trigger signal, discarding the digital pulse signal causing the trigger to eliminate invalid cases; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

Further, the signal summation circuit adopts an operational amplifier with power consumption less than 30mW and noise less than-69 dB.

Further, the comparator in the hysteresis comparator adopts a low-delay comparator which is less than 10 ns.

Furthermore, a plurality of the IV conversion circuits receive a path of charge pulse signals sent by the corresponding plastic flash detectors through the corresponding photomultiplier tubes or the silicon photomultiplier tubes.

An anti-coincidence method for eliminating invalid cases is characterized by comprising the following steps: 1) each IV conversion circuit receives a path of externally input charge pulse signal, converts the charge pulse signal into a voltage pulse signal with corresponding amplitude and sends the voltage pulse signal to the signal summation circuit; 2) the signal summation circuit is used for carrying out summation operation on the multi-path voltage pulse signals and outputting one path of voltage pulse signals to the hysteresis comparator; 3) the positive input end of the hysteresis comparator receives the voltage pulse signal, the negative input end of the hysteresis comparator receives a threshold signal sent by the digital-to-analog converter, and after comparison, a pulse signal with a tail stray signal filtered is output and sent to the differential circuit; 4) the differentiating circuit differentiates the pulse signal into a sharp pulse wave signal and sends the sharp pulse wave signal to the shaping circuit; 5) the shaping circuit shapes the sharp pulse wave signal into a digital pulse signal with fixed pulse width which can be received by the FPGA circuit and sends the digital pulse signal to the FPGA circuit; 6) the digital pulse signal sent by the shaping circuit is used as an anti-coincidence trigger signal, triggering coincidence operation is completed in the FPGA circuit, whether the digital pulse signal is an effective trigger signal or not is determined, invalid digital pulse signals are removed, and invalid cases are removed; 7) the FPGA circuit sends a command with fixed time sequence to the digital-analog converter according to a digital-analog converter receipt manual, so that the digital-analog converter generates a threshold signal and sends the threshold signal to the hysteresis comparator.

Further, the specific process of step 6) is as follows: the digital pulse signal sent by the shaping circuit is used as an anti-coincidence trigger signal, trigger coincidence operation is completed in the FPGA circuit, whether the digital pulse signal is an effective trigger signal or not is determined, if the operation result is high level 1, the anti-coincidence trigger is effective, the digital pulse signal causing the trigger is abandoned as the effective anti-coincidence trigger signal, and invalid cases are removed; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

Due to the adoption of the technical scheme, the invention has the following advantages: 1. the invention converts the charge signals output by the anti-coincidence detector into voltage signals for summation and accumulation, and then converts the multi-path signals into one-path signals for processing, thereby greatly reducing the use amount of components, saving the cost, reducing the power consumption and reducing the circuit area. 2. The threshold value of the hysteresis comparator is provided by a digital-to-analog converter (DAC), so that a designer can conveniently adjust the threshold value by sending an instruction on the ground, and the hysteresis comparator can be applied to a space particle detection environment to obtain the optimal threshold value. 3. Any small change of the input voltage of a common comparator near the threshold voltage can cause the jump of the output voltage, and the anti-interference capability is poor, particularly, a fast comparator, for example, the delay is less than 10ns, and often has a lot of burrs in the latter half part of the output pulse. 4. The invention selects the components with low noise and low power consumption, can reduce the power consumption and noise of the circuit, and can be widely applied to satellites for space charged particle measurement and the like.

Drawings

FIG. 1 is a schematic diagram of an anti-coincidence circuit according to the present invention.

Detailed Description

The present invention is described in detail below with reference to the attached drawings. It is to be understood, however, that the drawings are provided solely for the purposes of promoting an understanding of the invention and that they are not to be construed as limiting the invention. In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, the anti-coincidence circuit for eliminating invalid cases provided by the present invention includes an IV (current-voltage) conversion circuit 1, a signal summing circuit 2, a digital-analog converter 3, a hysteresis comparator 4, a differentiating circuit 5, a shaping circuit 6, and an FPGA (field programmable gate array) circuit 7.

The IV conversion circuits 1 are used for receiving a path of charge pulse signals sent by the corresponding plastic flash detector through the corresponding photomultiplier or silicon photomultiplier, converting the charge pulse signals into voltage pulse signals with corresponding amplitudes, and then respectively sending the voltage pulse signals to the signal summation circuit 2.

The signal summation circuit 2 is configured to perform summation operation on the voltage pulse signals output by the multiple paths of IV conversion circuits 1 to obtain a path of voltage signals, and send the path of voltage signals to the hysteresis comparator 4.

The digital-to-analog converter 3 is configured to generate a threshold signal with a certain amplitude under the control of the FPGA circuit 7, and send the threshold signal to the hysteresis comparator 4 as a trigger threshold of the hysteresis comparator 4, where a value of the threshold is larger than signal noise, for example, 30 mV.

The hysteresis comparator 4 is configured to perform hysteresis comparison on the voltage signal sent by the signal summation circuit 2 according to the threshold signal sent by the digital-to-analog converter 3 to obtain a path of pulse signal, and send the path of pulse signal to the differentiation circuit 5, so as to eliminate a glitch in a second half zone of the output pulse of the hysteresis comparator 4.

The differentiating circuit 5 is used for differentiating and converting the pulse signal into a sharp pulse wave signal and sending the sharp pulse wave signal to the shaping circuit 6, and the output waveform of the differentiating circuit 5 only reflects the abrupt change part of the input waveform.

The shaping circuit 6 is configured to shape the spike pulse wave signal into a digital pulse signal with a fixed pulse width that can be received by the FPGA circuit 7, and send the digital pulse signal to the FPGA circuit 7, where the fixed pulse width may be determined according to an actual situation or a technical requirement, for example, a pulse value is 500 ns.

The FPGA circuit 7 is used for determining whether the digital pulse signal is an effective trigger signal or not, rejecting invalid digital pulse signals and finishing rejection of invalid cases.

In a preferred embodiment, the FPGA circuit 7 internally performs a trigger coincidence operation to determine whether the digital pulse signal is a valid trigger signal, if the operation result is a high level 1, the anti-coincidence trigger is valid, and if the operation result is a valid anti-coincidence trigger signal, the digital pulse signal causing the trigger is discarded to eliminate invalid cases; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

In a preferred embodiment, the signal summing circuit 2 may employ a low power, low noise operational amplifier with power consumption less than 30mW and noise less than-69 dB.

In a preferred embodiment, the hysteresis comparator 4 is composed of a low-delay (<10ns) comparator, a resistor, a capacitor, and the like, and the circuit adds a hysteresis function, so that an unnecessary signal at the tail of a signal output by the comparator can be processed, and the comparator can only output one pulse signal, wherein a specific structure of the hysteresis comparator 4 is disclosed in the prior art, and is not described herein in detail.

In a preferred embodiment, the shaping circuit 6 is composed of a flip-flop, a resistor, a capacitor, and the like, wherein a specific structure of the shaping circuit 6 is disclosed in the prior art, and is not described herein again.

Based on the anti-coincidence circuit for eliminating the invalid cases, the invention also provides an anti-coincidence method for eliminating the invalid cases, which comprises the following steps:

1) the plastic flash detector is hit by charged particles to generate fluorescence, the fluorescence is photoelectrically converted into charge pulse signals with corresponding charge amount through a photomultiplier or a silicon photomultiplier, and each IV conversion circuit 1 converts one path of the charge pulse signals into voltage pulse signals with corresponding amplitude and sends the voltage pulse signals to the signal summation circuit 2.

2) The signal summation circuit 2 performs summation operation on the multiple paths of voltage pulse signals, and outputs one path of voltage pulse signal to the hysteresis comparator 4.

3) The positive input end of the hysteresis comparator 4 receives the voltage pulse signal, the negative input end of the hysteresis comparator 4 receives the threshold signal sent by the digital-to-analog converter 3, and after comparison, a pulse signal with a tail stray signal filtered is output and sent to the differentiating circuit 5.

4) The differentiating circuit 5 differentiates the pulse signal into a sharp pulse wave signal and sends the sharp pulse wave signal to the shaping circuit 6.

5) The shaping circuit 6 shapes the spike pulse wave signal into a digital pulse signal with a fixed pulse width which can be received by the FPGA circuit 7, and sends the digital pulse signal to the FPGA circuit 7.

6) The digital pulse signal sent by the shaping circuit 6 is used as an anti-coincidence triggering signal, triggering coincidence operation is completed in the FPGA circuit 7, whether the digital pulse signal is an effective triggering signal or not is determined, if the operation result is a high level 1, the anti-coincidence triggering is effective, the digital pulse signal causing the triggering needs to be abandoned as the effective anti-coincidence triggering signal, and invalid cases are eliminated; if the operation result is low level 0, the anti-coincidence trigger is invalid, and the digital pulse signal causing the trigger is not discarded as the anti-coincidence invalid trigger signal.

7) The FPGA circuit 7 transmits a command of a fixed timing to the digital-analog converter 3 according to the digital-analog converter receipt manual, controls the digital-analog converter 3, causes the digital-analog converter 3 to generate a threshold signal of a certain amplitude, and transmits the threshold signal to the hysteresis comparator 4. In space or universe, according to specific conditions, a control command is sent on the ground, the control command is communicated with a satellite in the space through a communication interface and an FPGA (field programmable gate array), and the digital-analog converter 3 is controlled to output a voltage signal with a certain amplitude as the threshold voltage of the hysteresis comparator 4, so that an optimal threshold value is obtained.

The above embodiments are only used for illustrating the present invention, and the structure, connection mode, manufacturing process, etc. of the components may be changed, and all equivalent changes and modifications performed on the basis of the technical solution of the present invention should not be excluded from the protection scope of the present invention.