Self-calibrating time-to-digital converter integrated circuit
阅读说明:本技术 自校准时间-数字转换器集成电路 (Self-calibrating time-to-digital converter integrated circuit ) 是由 殷勤 周国煜 叶尚府 赵亦平 李其霖 于 2019-07-10 设计创作,主要内容包括:本发明公开一种用于基于单光子雪崩二极管(SPAD)的深度感测的自校准时间-数字转换器(TDC)集成电路。电路包含:SPAD矩阵,具有多个以m行和n列布置的SPAD像素,SPAD像素的每一列中的SPAD像素由列总线连接;全域延迟锁相环(DLL)单元,具有n个缓冲器和n个时钟信号;以及图像信号处理单元,用于从列TDC阵列接收图像信号。电路还可包含:行控制单元,配置成针对传输信号启用每一行中的一个SPAD像素;循环n路复用器,用于在全域DLL单元中循环复用n个时钟信号;列TDC阵列,具有n个TDC,每一TDC更包括计数器和锁存器,每一TDC的锁存器连接到用于循环复用的循环n路复用器。(A self-calibrating time-to-digital converter (TDC) integrated circuit for Single Photon Avalanche Diode (SPAD) based depth sensing is disclosed. The circuit comprises: a SPAD matrix having a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each of the columns of SPAD pixels being connected by a column bus; a global Delay Locked Loop (DLL) unit having n buffers and n clock signals; and an image signal processing unit for receiving the image signal from the column TDC array. The circuit may also include: a row control unit configured to enable one SPAD pixel in each row for a transmission signal; a cycle n multiplexer for cyclically multiplexing n clock signals in the global DLL unit; a column TDC array having n TDCs, each TDC further comprising a counter and a latch, the latch of each TDC being connected to a cycle n multiplexer for cycle multiplexing.)
1. A self-calibrating time-to-digital converter integrated circuit, the circuit comprising:
a single photon avalanche diode matrix having a plurality of single photon avalanche diode pixels arranged in m rows and n columns, wherein the single photon avalanche diode pixels in each column of single photon avalanche diode pixels are connected by a column bus;
a global delay-locked loop unit having n buffers and n clock signals; and
an image signal processing unit for receiving the image signal from the column time-to-digital converter array.
Technical Field
The technology described in this disclosure generally relates to self-calibrating time-to-digital converter integrated circuits.
Background
An Integrated Circuit (IC) is an electronic circuit fabricated into the surface of a thin substrate of semiconductor material. ICs are used in almost all electronic equipment today and have revolutionized the electronic device world. Computers, mobile phones and other digital household appliances are now an integral part of the modern social structure, which is made possible by the low cost of producing ICs.
Disclosure of Invention
According to some embodiments of the present disclosure, there is provided a self-calibrating time-to-digital converter integrated circuit, the circuit comprising: a single photon avalanche diode matrix having a plurality of single photon avalanche diode pixels arranged in m rows and n columns, wherein the single photon avalanche diode pixels in each column of single photon avalanche diode pixels are connected by a column bus; a global delay-locked loop unit having n buffers and n clock signals; and an image signal processing unit for receiving the image signal from the column time-to-digital converter array.
Drawings
Aspects of some embodiments of the disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Figure 1A is a diagram illustrating a time-to-digital converter integrated circuit for single photon avalanche diode based depth sensing, in accordance with some embodiments.
Figure 1B is another diagram illustrating a time-to-digital converter (TDC) integrated circuit for single photon avalanche diode based deep sensing, in accordance with some embodiments.
Figure 1C is a diagram illustrating the structure of a TDC pixel according to some embodiments.
Figure 2A is a diagram illustrating a three-dimensional time-to-digital converter integrated circuit with two layers for single photon avalanche diode based depth sensing, in accordance with some embodiments.
Figure 2B is a diagram illustrating a three-dimensional time-to-digital converter integrated circuit with three layers for single photon avalanche diode based depth sensing, in accordance with some embodiments.
Figure 3A is a diagram illustrating a three-dimensional pixel-by-pixel time-to-digital converter integrated circuit with two layers for single photon avalanche diode based depth sensing, in accordance with some embodiments.
Figure 3B is a diagram illustrating a three-dimensional pixel-by-pixel time-to-digital converter integrated circuit with three layers for single photon avalanche diode based depth sensing, in accordance with some embodiments.
Figure 4A is a diagram illustrating a self-calibrating TDC circuit with 4 buffers in accordance with some embodiments.
Figure 4B is a diagram illustrating the operation of a cycle multiplexer having a self-calibrating TDC circuit with 4 buffers, according to some embodiments.
FIG. 4C is a schematic diagram illustrating a self-calibration operation of the cyclic multiplexer shown in FIG. 4B according to some embodiments.
Figure 5 is a diagram illustrating a self-calibrating TDC circuit with N buffers in accordance with some embodiments.
Fig. 6 is a diagram illustrating a balanced clock tree in accordance with some embodiments.
Fig. 7 is a diagram illustrating a cyclic multiplexing digital controller according to some embodiments.
Figures 8A-8C are graphs showing performance with analog time-to-digital converters with and without skew, according to some embodiments.
FIG. 9 is a table illustrating error accumulation in clock cycles according to some embodiments.
Figure 10 is a flow diagram illustrating a method of self-calibration of a time-to-digital converter (TDC) circuit, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and similar terms, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Time-of-Flight (ToF) is a method for measuring the distance between a sensor and an object, based on the Time difference between the emission of a signal and its return to the sensor after reflection by the object. Depth sensing is also referred to as distance sensing. Depth imaging ToF cameras are very advanced LIDAR (light detection and ranging, LIDAR) devices that replace a standard point-by-point scanning laser beam with a single light pulse to achieve full spatial perception. Depth sensing cameras may be implemented to track facial or hand movements, map out rooms and navigate autonomous vehicles, etc.
A single-photon avalanche diode (SPAD) is a solid-state photodetector in which photon-generated carriers trigger a short duration but relatively large avalanche current by the internal photoelectric effect. That is, when a photon is received, an avalanche current is generated indicative of the detection. This avalanche current is generated by a mechanism called impact ionization (impact ionization), in which electrons and/or holes as carriers are accelerated to high kinetic energy by a large potential gradient. If the kinetic energy of the received electrons or holes is large enough (as a function of the ionization energy of the bulk material), additional carriers (electrons and/or holes) are released from the atomic lattice. Thus, the number of carriers increases exponentially from as few as a single carrier to generate an avalanche current. SPADs are capable of detecting different types of low intensity ionizing radiation, including: gamma radiation, X-ray radiation, beta radiation, and alpha-particle radiation along with electromagnetic signals in UV, visible, and IR down to single photon levels. SPAD is also able to discriminate the arrival time of events (photons) with high accuracy within a time jitter of only tens of picoseconds. SPADs differ from Avalanche Photodiodes (APDs) in that they are specifically designed to operate at reverse bias voltages well above the breakdown voltage. SPAD has recently been implemented in lidar, ToF 3D imaging, PET scanning, single photon experiments, fluorescence lifetime microscopy (fluorescence lifetime microscopy), and optical communications, particularly in quantum key distribution.
SPAD-based depth sensing requires a high resolution time-to-digital converter (TDC) to quantify ToF information. Effective resolution Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) limitations of a TDC. Self-calibrating TDCs for SPAD-based depth sensing implement multiplexers from each output terminal of a global-delayed phase-locked loop (DLL) to the same latch unit in a column TDC. Each latch unit is then cyclically routed to one of all output terminals of the global DLL. The digital control logic circuit cyclically multiplexes the routing between the column latches and the global DLL outputs.
Figure 1A is a diagram illustrating a time-to-digital converter integrated circuit for single photon avalanche diode based depth sensing, in accordance with some embodiments. According to some embodiments, the SPAD pixel array includes a matrix of pixels, each pixel being a detector that detects incident photons. The SPAD pixel array is controlled by a row controller and a column controller, which will be discussed in more detail below. The row and column controllers process the information received by each pixel to produce a matrix of pixels representing an image.
Figure 1B is another diagram illustrating a time-to-digital converter (TDC) integrated circuit for single photon avalanche diode based deep sensing, in accordance with some embodiments. According to some embodiments, a time-to-digital converter (TDC) integrated
According to some embodiments, the self-
Figure 1C is a diagram illustrating the structure of a TDC pixel according to some embodiments. According to some embodiments,
According to some embodiments, the
Figure 2A is a diagram illustrating a 3D time-to-digital converter integrated circuit with two layers for single photon avalanche diode based depth sensing, in accordance with some embodiments. According to some embodiments, the 3D TDC integrated circuit 2000 for SPAD-based depth sensing is a 3D implementation of the
Figure 2B is a 3D time-to-digital converter integrated circuit with three layers for single photon avalanche diode based depth sensing, according to some embodiments. According to some embodiments, a third layer is implemented in addition to the two layers in fig. 2A, the SPAD pixel array 2100' is implemented in the top layer, the TDC array 2200' is implemented in the middle layer, and the image signal processing unit 2400' is implemented in the bottom layer. According to some embodiments, the TDC 2200 'in the middle layer is connected to the image signal processing unit 2400' in the bottom layer through a through-silicon via (TSV) or a TSV (e.g., 2401 and 2402). According to some embodiments, the tri-layer implementation in fig. 2B further saves space on the silicon surface, further shortens the wiring and further reduces power consumption and timing delay as compared to fig. 2A.
Figure 3A is a diagram illustrating a 3D pixel-by-pixel TDC integrated circuit with two layers for SPAD-based depth sensing, in accordance with some embodiments. According to some embodiments, the 3D pixel-by-pixel TDC
Figure 3B is a diagram illustrating a 3D pixel-by-pixel TDC integrated circuit with three layers for SPAD-based depth sensing, in accordance with some embodiments. According to some embodiments, similar to the difference between fig. 2A and 2B, a third layer is implemented in addition to the two layers in fig. 3A, the SPAD pixel array 3100' is implemented in the top layer, the TDC array 3200' is implemented in the middle layer, and the image signal processing unit 3400' is implemented in the bottom layer. According to some embodiments, the TDC 3200 'in the middle layer is connected to the image signal processing unit 3400' in the bottom layer through TSVs (e.g., 3401, 3402, and 3403). According to some embodiments, the tri-layer implementation in fig. 3B further saves space on the silicon surface, further shortens the wiring and further reduces power consumption and timing delay as compared to fig. 3A.
According to some embodiments, in the implementations in fig. 1A, 2A, and 2B, a column bus is implemented to connect respective columns of SPADs. At the same time, a row controller is implemented to select a single SPAD in each row. If there are m rows of SPAD pixels in the SPAD pixel array, then m clock cycles are required to scan all m rows of SPAD pixels. Thus, the SPAD pixel arrays in fig. 1A, 2A, and 2B are not capable of capturing a transient image of an object. If the object does not move rapidly, or does not move at all, no distortion will occur. But if the object is moving rapidly, distortion in the final image occurs because the signals in the first and last lines are separated by m-1 clock cycles. By comparison, the implants in fig. 3A and 3B remove distortion in fast moving images by eliminating the column bus and simultaneously transmitting signals to m by n TDCs on all m by n SPAD pixels without waiting to scan m clock cycles.
Fig. 4A is a diagram illustrating a self-calibrating time-to-digital converter circuit having 4 buffers in accordance with some embodiments. According to some embodiments, the self-
According to some embodiments,
According to some embodiments, the
Fig. 4B is a diagram illustrating the operation of a cyclic multiplexer of a self-calibrating time-to-digital converter circuit having 4 buffers in accordance with some embodiments. According to some embodiments, 4220I, 4220II, 4220III, and 4220IV are four modes of multiplexing
according to some embodiments, in a conventional approach, CLK1 is connected to BT1, CLK2 is connected to BT2, CLK3 is connected to BT3, CLK4 is connected to BT4, and cyclic multiplexing is not implemented.
FIG. 4C is a schematic diagram illustrating a self-calibration operation of the cyclic multiplexer shown in FIG. 4B according to some embodiments. According to some embodiments,
According to some embodiments,
According to some embodiments,
According to some embodiments,
Figure 5 is a diagram illustrating a self-calibrating TDC circuit with N buffers in accordance with some embodiments. According to some embodiments, the self-calibrating TDC 5000 is similar to the self-calibrating
In the self-calibrating TDC 5000, σ 1+
Fig. 6 is a diagram illustrating a balanced clock tree in accordance with some embodiments. The clock tree distributes the clock signal from a common point to all elements implementing the clock signal. This function is critical to the operation of synchronous systems, and therefore the characteristics of the clock signal and the electrical network implemented in its distribution are carefully designed.
According to some embodiments, the clock signal load has the largest fan-out and operates at the highest speed of any signal within the synchronous system. According to some embodiments, the data signal is provided with a time reference by a clock signal, the clock waveform having to be clear and sharp. According to some embodiments, the clock signal is affected by technology scale, i.e., the resistance of long global interconnect lines becomes significantly larger as the line size decreases. According to some embodiments, increased line resistance is one of the main reasons that clock distribution is increasingly important for synchronization performance. According to some embodiments, control of any differences and uncertainties in the arrival times of the clock signals severely limits the maximum performance of the overall system and can create catastrophic race conditions where incorrect data signals can latch into registers.
In balanced clock tree 6000, according to some embodiments, routing of wires is implemented such that timing through routing from In1 to Out1 is equal to timing through routing from In1 to Out2, equal to timing through routing from In1 to Out3, and equal to timing through routing from In1 to Out 4. The same applies to In2, In which In2-Out 1-In 2-Out 2-In 2-Out 3-In 2-Out 4. For In3, In3-Out 1-In 3-Out 2-In 3-Out 3-In 3-Out 4; for In4, In4-Out 1-In 4-Out 2-In 4-Out 3-In 4-Out 4.
Fig. 7 is a diagram illustrating a cyclic multiplexing digital controller according to some embodiments. According to some embodiments, 710 is an N frame data collection, comprising: frame 1,
Figures 8A-8C are graphs showing performance with simulated TDCs with and without skew, according to some embodiments. According to some embodiments, the horizontal axis in fig. 8A is the time input axis and the vertical axis is the ND output axis. The black curve in fig. 8A is a simulation corresponding to the ideal case of fig. 8B, and the dashed curve is a phase deviation simulation corresponding to fig. 8C. FIG. 8B shows no ripple, while in the simulation, FIG. 8C shows a ripple of roughly 1 to roughly 4.
FIG. 9 is a table illustrating error accumulation in clock cycles according to some embodiments. According to some embodiments, as discussed above, σ 1+
Figure 10 is a flow diagram illustrating a method of self-calibration of a time-to-digital converter (TDC) circuit, according to some embodiments. According to some embodiments, at
In accordance with some embodiments, a self-calibrating time-to-digital converter (TDC) integrated circuit for Single Photon Avalanche Diode (SPAD) based depth sensing is disclosed. The circuit comprises: a SPAD matrix having a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each of the columns of SPAD pixels being connected by a column bus; a global DLL unit having n buffers and n clock signals; and an image signal processing unit for receiving the image signal from the column TDC array. According to some embodiments, the circuit further comprises a row control unit configured to enable one SPAD pixel in each row for the transfer signal. According to some embodiments, the circuit also includes a cycle n multiplexer for cycle multiplexing n clock signals in the global DLL unit. According to some embodiments, the circuit also includes a column TDC array having n TDCs, each TDC further comprising a counter and a latch, the latch of each TDC being connected to a cycle n-multiplexer for cycle multiplexing. According to some embodiments, the SPAD matrix is implemented in a first tier and the array of column TDCs is implemented in a second tier different from the first tier, each column bus connected to a respective column TDC by a respective hybrid junction. According to some embodiments, each of the n clock signals in the global DLL is connected to one and only one of the n latches in the column TDC array at a given time, each of the n clock signals in the global DLL sweeping through all of the n latches in the column TDC array in n clock cycles. According to some embodiments, the row control units are implemented in the second layer. According to some embodiments, the global DLL unit is implemented in the second layer. According to some embodiments, the loop n multiplexer unit is implemented in the second layer. According to some embodiments, the image signal processing unit is implemented in a third layer different from the first layer and the second layer.
According to some embodiments, the circuit further comprises: a row control unit configured to enable one single photon avalanche diode pixel in each row for a transmission signal.
According to some embodiments, the circuit further comprises: and the circulation n multiplexer is used for circularly multiplexing n clock signals in the full-domain delay phase-locked loop unit.
According to some embodiments, the circuit further comprises: a column time-to-digital converter array having n time-to-digital converters, wherein each time-to-digital converter further comprises a counter and a latch, wherein the latch of each time-to-digital converter is connected to the cyclic n-plexer for cyclic multiplexing.
According to some embodiments, wherein the single photon avalanche diode matrix is implemented in a first layer and the column time to digital converter array is implemented in a second layer different from the first layer, wherein each column bus is connected to a respective column time to digital converter by a respective hybrid junction.
According to some embodiments, wherein each of the n clock signals in the global delay locked loop is connected at a given time to one and only one of the n latches in the column time-to-digital converter array, wherein each of the n clock signals in the global delay locked loop is scanned by all n latches in the column time-to-digital converter array in n clock cycles.
According to some embodiments, wherein the row control unit is implemented in the second layer.
According to some embodiments, wherein the global delay locked loop unit is implemented in the second layer.
According to some embodiments, wherein the cyclic n-multiplexer unit is implemented in the second layer.
According to some embodiments, wherein the image signal processing unit is implemented in a third layer different from the first layer and the second layer.
In accordance with some embodiments, a 3D pixel-by-pixel self-calibrating TDC integrated circuit for SPAD-based depth sensing is disclosed. The circuit comprises: a SPAD matrix having a plurality of SPAD pixels arranged in m rows and n columns, implemented in a first layer; a row control unit configured to enable one and only one SPAD pixel in each row for a transfer signal; a global DLL unit having n buffers and n clock signals; a loop n-multiplexer for loop multiplexing the n clock signals in the global DLL cell to average the phase change; a TDC matrix, arranged in m rows and n columns, implemented in a second layer below the first layer, each TDC being arranged directly below a respective SPAD pixel to which it is connected by hybrid junction; and an image signal processing unit for receiving the image signal from the column TDC array. According to some embodiments, the image signal processing unit is implemented in the second layer. According to some embodiments, the image signal processing unit is implemented in a third layer below the second layer. According to some embodiments, each TDC is connected to the image signal processing unit through a TSV. According to some embodiments, the global DLL is implemented in the second layer. According to some embodiments, the loop n multiplexer unit is implemented in the second layer. According to some embodiments, each TDC further comprises a counter and a latch, wherein the latch of each TDC is connected to a cyclic n-way multiplexer for cyclic multiplexing.
In accordance with some embodiments, a 3D pixel-by-pixel self-calibrating time-to-digital converter integrated circuit for single photon avalanche diode based depth sensing is disclosed, the circuit comprising: a single photon avalanche diode matrix having a plurality of single photon avalanche diode pixels arranged in m rows and n columns implemented in a first layer; a row control unit configured to enable one and only one single photon avalanche diode pixel in each row for a transmission signal; a global delay-locked loop unit having n buffers and n clock signals; a cyclic n-way multiplexer for cyclically multiplexing n clock signals in the global delay locked loop unit to average phase variation; a matrix of time-to-digital converters implemented in a second layer below the first layer, arranged in m rows and n columns, wherein each time-to-digital converter is arranged directly below a respective single photon avalanche diode pixel, wherein the time-to-digital converters are connected to the respective single photon avalanche diode pixels by hybrid junctions; and an image signal processing unit for receiving an image signal from the column time-to-digital converter array.
According to some embodiments, wherein the image signal processing unit is implemented in the second layer.
According to some embodiments, wherein the image signal processing unit is implemented in a third layer below the second layer.
According to some embodiments, wherein each time-to-digital converter is connected to the image signal processing unit through a TSV.
According to some embodiments, wherein the global delay locked loop is implemented in the second layer.
According to some embodiments, wherein the cyclic n-multiplexer unit is implemented in the second layer.
According to some embodiments, wherein each time-to-digital converter further comprises a counter and a latch, wherein the latch of each time-to-digital converter is connected to the cyclic n-multiplexer for cyclic multiplexing.
In accordance with some embodiments, a method for self-calibration of a time-to-digital converter (TDC) circuit is disclosed. The method comprises the following steps: in each frame data collection, the TDC converts the time-of-flight signals from the SPAD array into depth information; forming a TDC from a global DLL having a plurality of phase signals and column-by-column latches sampling the phases; rerouting the global DLL output terminals to the column TDC latches with a cyclic multiplexer in each frame data collection; collecting a plurality of data frames; and averaging the non-uniformity of the TDC. According to some embodiments, the averaging of the non-uniformities of the TDC is performed by a histogram method. In the step of rerouting the global DLL output terminals, the phase signal sequence is shifted clockwise, according to some embodiments. According to some embodiments, in the step of rerouting the global DLL output terminals, the phase signal sequence is shifted counter-clockwise. According to some embodiments, in the step of rerouting the global DLL output terminals, the phase signal is sequentially shifted by at least one phase in each frame data collection. According to some embodiments, after cyclically multiplexing the plurality of frame data collections, all output data forms a histogram having a depth information distribution.
According to some embodiments, a method for self-calibration of a time-to-digital converter circuit is disclosed, the method comprising the steps of: in each frame data collection, a time-to-digital converter converts time-of-flight signals from a single photon avalanche diode array to depth information; forming a time-to-digital converter from a global delay locked loop having a plurality of phase signals and column-by-column latches sampling the phases; rerouting the global delay locked loop output terminal to a column time-to-digital converter latch with a cyclic multiplexer in each frame data collection; collecting a plurality of data frames; and averaging the non-uniformity of the time-to-digital converter.
According to some embodiments, wherein the averaging of the non-uniformities of the time-to-digital converter is performed by a histogram method.
According to some embodiments, wherein in the step of rerouting the global delay locked loop output terminals, the phase signal sequence is shifted clockwise.
According to some embodiments, wherein in the step of rerouting the global delay locked loop output terminals, the phase signal sequence is shifted counterclockwise.
According to some embodiments, wherein in the step of rerouting the global delay locked loop output terminals, the phase signal is sequentially shifted by at least one phase in each frame data collection.
According to some embodiments, after cyclically multiplexing the plurality of frame data collections, all output data forms a histogram having a distribution of depth information.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of some embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of some embodiments of the present disclosure.
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