阅读说明：本技术 一种连接器式加电计时装置及加电计时方法 (Connector type power-on timing device and power-on timing method ) 是由 蒋学东 张伟 姚长虹 滕雨彤 张聪颖 刘勇 于 2019-10-30 设计创作，主要内容包括：一种连接器式加电计时装置,包括连接器和加电计时模块；所述加电计时模块包括电源处理模块、处理器、时钟芯片、存储芯片和通信接口。连接器中安装电路,实现对产品加电状态的监测和产品通电时间的统计,同时不改变被监测产品的状态,不占用被监测产品的空间；通用性强,可以在任意的连接器上进行适配。(A connector-type power-on timing device includes a connector and a power-on timing module; the power-on timing module comprises a power supply processing module, a processor, a clock chip, a storage chip and a communication interface. A circuit is arranged in the connector, so that the monitoring of the power-on state of the product and the statistics of the power-on time of the product are realized, meanwhile, the state of the monitored product is not changed, and the space of the monitored product is not occupied; the universality is strong, and the adapter can be adapted on any connector.)

1. A connector-type power-up timing device, comprising: comprises a connector and a power-on timing module; wherein:

the power-on timing module is mounted within the connector; the power-on timing module comprises a power supply processing module, a processor, a clock chip, a storage chip and a communication interface; the power supply processing module is respectively and electrically connected with the processor, the clock chip, the storage chip and the communication interface; the processor is respectively connected with the storage chip and the communication interface and is used for processing information; the clock chip is connected with the processor and used for providing a system clock;

the memory chip is used for reading/storing information; the communication interface is used for inputting/outputting information.

2. The connector-type power-up timing device of claim 1, wherein: the processor is a singlechip with a USB interface.

3. The connector-type power-up timing device of claim 1, wherein: the clock chip is a temperature compensation crystal oscillator.

4. The connector-type power-up timing device of claim 1, wherein: the memory chip is a NOR FLASH type memory.

5. The connector-type power-up timing device of claim 1, wherein: the communication interface is a wired or wireless interface.

6. The connector-type power-up timing device of claim 1, wherein: and the power supply processing module is connected with a power supply pin of the connector.

7. The connector-type power-up timing device of claim 1, wherein: the device also comprises a display module for displaying information; the display module and the communication interface are connected in a wired or wireless mode.

8. A connector-type power-up timing method, characterized by: the power-on timing device according to any one of claims 1 to 7, comprising:

initialization: the communication interface transmits the received initialization information to the processor, and the processor writes the initialization information into the storage chip; after the power-on timing device is powered on, the processor reads the initialization information, starts timing by taking the initialization information as a starting point, updates a timing result according to timing precision and writes the timing result information into the storage chip;

and (3) reading: the communication interface transmits the reading instruction to the processor, and the processor reads the power-on time information and the user-defined information from the storage chip and outputs the power-on time information and the user-defined information through the communication interface;

and (3) writing: the communication interface transmits the write-in instruction to the processor, and the processor writes the initialization information and the user-defined information into the storage chip and returns the state.

9. The connector-type power-up timing method of claim 7, wherein: the initialization information at least comprises power-on time initial information, a power-on time information storage area and a user self-defined information storage area.

Technical Field

The invention belongs to the field of connectors, and particularly relates to a connector type power-on timing device and a power-on timing method.

Background

Under the environment condition that the product is unattended or inconvenient to operate manually, in order to detect and monitor the power-on condition of the product, a power-on timing function needs to be added at a proper position of the product. The current power-on timing device is single in application, and has no connector type power-on timing device, so that the power-on timing device can be adapted to any connector.

Disclosure of Invention

In order to overcome the defects in the background art, the invention discloses a connector type power-on timing device and a power-on timing method, which realize the monitoring of the power-on state of a product and the statistics of the power-on time of the product.

In order to realize the purpose, the invention adopts the following technical scheme: a connector-type power-up timing apparatus includes a connector and a power-up timing module; the power-on timing module is arranged in the connector; the power-on timing module comprises a power supply processing module, a processor, a clock chip, a storage chip and a communication interface; the power supply processing module is respectively and electrically connected with the processor, the clock chip, the storage chip and the communication interface; the processor is respectively connected with the storage chip and the communication interface and is used for processing information; the clock chip is connected with the processor and used for providing a system clock; the memory chip is used for reading/storing information; the communication interface is used for inputting/outputting information.

Further, the processor is a single chip microcomputer with a USB interface.

Furthermore, the clock chip is a temperature compensation crystal oscillator.

Further, the memory chip is a NOR FLASH type memory.

Further, the communication interface is a wired or wireless interface.

Furthermore, the power supply processing module is connected with the power supply pin of the connector.

Furthermore, the timing device also comprises a display module used for displaying information; the display module and the communication interface are connected in a wired or wireless mode.

A connector-based power-up timing method, comprising:

initialization: the communication interface transmits the received initialization information to the processor, and the processor writes the initialization information into the storage chip; after the power-on timing device is powered on, the processor reads the initialization information, starts timing by taking the initialization information as a starting point, updates a timing result according to timing precision and writes the timing result information into the storage chip;

and (3) reading: the communication interface transmits the reading instruction to the processor, and the processor reads the power-on time information and the user-defined information from the storage chip and outputs the power-on time information and the user-defined information through the communication interface;

and (3) writing: the communication interface transmits the write-in instruction to the processor, and the processor writes the initialization information and the user-defined information into the storage chip and returns the state.

Further, the initialization information includes at least power-on time initial information, a power-on time information storage area, and a user-defined information storage area.

Due to the adoption of the technical scheme, the invention has the following beneficial effects: a circuit is arranged in the connector, so that the monitoring of the power-on state of the product and the statistics of the power-on time of the product are realized, meanwhile, the state of the monitored product is not changed, and the space of the monitored product is not occupied; the universality is strong, and the adapter can be adapted on any connector.

Drawings

FIG. 1 is a schematic diagram of a connector-type power-up timing device;

FIG. 2 is a functional block diagram of a connector-type power-up timing device;

fig. 3 is a schematic diagram of an internal memory area of a memory chip.

In the figure: 1. a connector; 2. a power-up timing module; 3. a connector cable; 4. and a display module.

Detailed Description

The present invention will be explained in detail by the following examples, which are disclosed for the purpose of protecting all technical improvements within the scope of the present invention.

As shown in fig. 1-2, the connector-type power-on timing apparatus includes: the connector and add the timing module, add the timing module and install in the connector body, add the timing module and contain: the device comprises a power supply processing module, a processor, a clock chip, a storage chip and a communication interface. The power supply processing module is used for detecting and monitoring the power supply state of a product and supplying power for the processor, the clock chip, the storage chip and the communication interface, the processor is used for timing and processing power-on information, the clock chip is used for providing a system clock for the processor, the storage chip is used for reading/storing the power-on information, and the communication interface is used for inputting/outputting the information.

The processor in the power-on timing circuit can be a single chip microcomputer with a USB interface, the clock chip can be a temperature compensation crystal oscillator, the communication interface can be a USB interface wired communication interface and a ZigBee wireless communication interface, and the storage chip can be a NOR FLASH type memory.

The communication interface in the power-on timing circuit may have only a wired communication interface or only a wireless communication interface. The connector-type power-on timing device may further comprise a display module, and the display module and the communication interface are connected by wire or wirelessly.

The power-on timing method of the device comprises the following steps:

when the memory chip is used for the first time, initialization information (the initialization information comprises power-on time initial information, a power-on time information storage area and a user-defined information storage area) is written into a specific position of the memory chip through a communication interface, and the content of the initialization information and the area division of the memory chip are shown in fig. 3.

After the power-on timing device is powered on, the processor reads initialization information from a specific position of the memory chip to obtain power-on time initial information, starts timing by taking X as a starting point, updates timing results according to the precision of Y, and writes the timing result information into a power-on time information storage area allocated in the memory chip (which is an operation automatically performed after power-on).

When the power-on timing device executes reading operation, the communication interface transmits a reading instruction to the processor, and the processor selects the following operation according to the received instruction, wherein firstly, the processor reads power-on time information from the storage chip and then transmits the power-on time information to the display module through the communication interface for displaying and storing; the processor reads the user-defined information from the storage chip and then transmits the user-defined information to the display module through the communication interface for displaying and storing;

when the timing device is powered on to execute writing operation, the communication interface transmits a writing instruction to the processor, and the processor selects to perform the following operations according to the received instruction, wherein firstly, the processor receives the initialization information transmitted by the communication interface, writes the initialization information into a specific position of the storage chip, and then returns to the state; and the processor receives the user-defined information transmitted by the communication interface, writes the user-defined information into a user-defined information storage area specified in the storage chip, and then returns to the state.

The present invention is not described in detail in the prior art.